Technology and Trends

Intento Design is working with STMicroelectronics to bring ID-XploreTM EDA software, which is aimed at solving the critical analog design challenges, to FD-SOI process nodes. “ID-Xplore is a disruptive EDA software that accelerates analog design and migration processes by at least one order of magnitude. It reduces the cost and latency inherent to analog design. Currently, there is no similar EDA tool on the market covering the analog design challenges like ID-Xplore,” noted Dr. Ramy Iskander, CEO of Intento Design (see the press release here). ST's FD-SOI design expertise roots, of course, are as deep as they get. “ST’s decision to work with us confirms the relevance of our solution. We are very excited to work jointly with ST teams to take the most benefit out of FD-SOI technology leveraging ST’s pioneering leadership in this area,” continued Dr. Iskander. “We’ve already seen the benefits of ID-Xplore in accelerating the design phase of different analog circuits, thanks to the software’s fast and accurate exploration capabilities in advanced FD-SOI processes,” said Thierry Bion, ST's Hardware Design Director, Aerospace Defense Legacy Division. “By facilitating IP reuse and sharing of design insights between engineers, ID-Xplore™ is helping our teams significantly accelerate new product introductions.” ID-Xplore uses the OpenAccess database standard and is fully integrated within the Cadence design environment. The designer’s implicit and explicit knowledge is expressed as technology-independent constraints, bringing the designers back to their core expertise and creativity. If you want to learn more, the folks over at semiwiki.com have made a number of posts on Intento Design recently. They're really helpful in understanding what the company does, how and why: CEO Interview: Ramy Iskander of Intento Design Edit (by Daniel Nenni) – good backgrounder on the company and product. The Intention View: Disruptive Innovation for Analog Design Edit (by Daniel Nenni) – an excellent interview with Dr. Caitlin Brandon about how the tool works and how it aligns with and supports the way analog designers work. A New Kind of Analog EDA Company Edit (by Daniel Payne) – Daniel Payne started his career as a circuit designer at Intel, and is now a well-known consultant/expert in the EDA world. Here he explores how ID-Xplore actually works and its “cool new automation features”.

Specialty foundry TowerJazz is ramping a 65nm version of its RF-SOI process on 300mm wafers at Fab 7 in Uozu, Japan. To support the ramp, the company has signed a contract with long-term partner, Soitec, guaranteeing a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next years and ensuring supply to its customers, despite a tight SOI wafer market. [caption id="attachment_12108" align="alignright" width="300"] The 300mm 65nm RF-SOI process will be offered at the Uozu, Japan fab, which is operated by the TowerJazz Panasonic Semiconductor Company (TPSCo). (Photo courtesy: TowerJazz)[/caption] Five of TJ's seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch, CEO Russell Ellwanter said in his lead keynote at the SOI Consortium’s 5th International RF-SOI Workshop in Shanghai (spring, 2018). BTW, that was in fact a very inspirational talk about Value Creation, and the importance of treating your suppliers with respect. He credited his company’s close relationship with RF-SOI wafer-supplier Soitec for TJ’s claim to the world’s best linearity. “We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF-SOI partnership,” said Soitec CEO Paul Boudre. “TowerJazz was the first foundry to ramp our RFeSI products to high volume production in 200mm and continues as one of the industry leaders in innovation in this exciting RF market with advanced and differentiated offerings.” According to the TJ press release (you can read it here), with its best in class metrics the TowerJazz 65nm RF-SOI process enables the combination of low insertion loss and high power handling RF switches with options for high-performance low-noise amplifiers as well as digital integration. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals. It's a high-growth market, to be sure. Market researchers Mobile Experts predict that the mobile RF front-end market will reach $22 billion in 2022 from an estimated $16 billion in 2018. TowerJazz says its breakthrough RF SOI technology continues to support this high-growth market and is well-poised to take advantage of next-generation 5G standards, which will boost data rates and provide further content growth opportunities in the coming years. Customers are already getting into position. For example, Maxscend (WuXi, China), a provider of RF components and IoT integrated circuits, is ramping in this new technology. “We chose TowerJazz for its advanced technology capabilities and its ability to deliver in high volume while continuously innovating with a strong roadmap. We specifically selected its 300mm 65nm RF SOI platform for our next-generation product line due to its superior performance, enabling low insertion loss and high power handling,” said Maxscend CEO Zhihan Xu. As longtime ASN readers will know, we've been covering the evolutions of TJ's RF-SOI platforms since the beginning of the decade. It's worth noting, too, that beyond RF, TowerJazz also offers foundry customers other SOI-based processes, such as the new 0.18μm BCD SOI, a 200V SOI technology platform (announced in 2017, press release here) for motor drivers, industrial tools, electric vehicles and more. The previous generation 0.18μm SOI for automotive power management also offers exceptional area savings and is well-suited for high temperature operation. Back in 2014, here at ASN we did a great interview with TJ SVP Dr. Marco Racanelli about when and why they use SOI – and while processes have advanced, the basic drivers are still there, so it's a still a good read. And finally, designers will want to know that the TJ Multi-Project Wafer (MPW) Shuttle Program offers the 65nm RF-SOI process, as well as other SOI-based processes. See the website for scheduling and details.

GlobalFoundries has announced that the company’s 22nm FD-SOI (22FDX®) technology has delivered more than two billion dollars of client design win revenue. With more than 50 client designs, 22FDX is being used in power-optimized chips across a broad range of high-growth applications such as automotive, 5G connectivity and IoT. Their clients chose it for the significant reductions in power and die size relative to a traditional bulk CMOS process, says the company. 22FDX offers the industry’s lowest operating voltage, delivering up to 500MHz frequencies at only 0.4 volts. The technology also delivers efficient single-chip integration of RF, transceiver, baseband, processor, and power management components, “...providing an unparalleled combination of high performance RF and mmWave functionality with low-power, high density logic for devices that require long-lasting battery life, increased processing capability, and connectivity.” 22FDX is in early production, with yields and performance matching client expectations. A recent VLSI Research survey indicated that FD-SOI technology is seen as a complementary technology to FinFET. It's gaining traction in application spaces such as IoT, where power consumption is important and the product life is relatively short. “We’re only just beginning,” said GF CEO Tom Caulfied. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. We will continue to build on our momentum and look for ways to expand our reach to address the evolving needs of the industry.” Here's a sampling of customer quotes from the press release (read more here): “At Synaptics, as we expand upon our industry-leading mobile and PC businesses to include delivering new and innovative products that address the booming IoT market, we require the best available technologies to enable us to deliver top-notch solutions including voice and multimedia processing capabilities for our customers,” said the company's CEO, Rick Bergman. “GF’s 22FDX technology delivers a potent mix of low static and dynamic power along with excellent performance to give us a great platform for our world-class products.” “As our customers increasingly demand more from their mobile experiences, our partnership with GF on its 22FDX technology is critical to differentiate ourselves in the competitive market and deliver powerful and efficient mobile SoCs,” said Rockchip CEO Min Li. “Our goal has always been to provide more secure, connected experiences for drivers. Combining our leadership in radar technology with GF's 22FDX automotive-qualified process, we are able to deliver a cost-effective, high performance, low power solution that opens new opportunities for car manufacturers to provide better experiences for drivers around the world," said Kobi Marenko, CEO of Arbe Robotics. “The automotive industry realizes that assisted driving solutions require more camera information besides Radar and Lidar, integrating information from multiple cameras. The resulting DreamChip multi-core vision processor platform, based on the 22FDX process is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives with a massively reduced time to market," said Dream Chip Technologies CEO Jens Benndorf. “With 22FDX, the value proposition for us is the potential power and area savings, two key metrics for our highly optimized LTE NB-IoT and CAT-M chipsets. In addition, leveraging the growing ecosystems of IP available in the 22FDX process helps to accelerate time to market,” said Peter Wong, CEO at Riot Micro, which designs purpose-built silicon for wireless IoT applications. (Read more about that here.) GF adds that it is preparing to deliver 12FDX™ technology, which will provide a full node scaling benefit and improved power efficiency for a new generation of applications, from edge-node artificial intelligence and AR/VR to 5G networking and ADAS.

That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point. Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings. The original goal of the panel was “...to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet 'always-on' market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.” (Update 2 August 2018: a complete video of this panel is now available on YouTube -- click here to view it.) [caption id="attachment_12035" align="alignnone" width="958"] #55 DAC Expert Panel: How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? Left to right: Brian Fuller, Arm (moderator); Scott Hanson, Ambiq Micro; Lauri Koskinen, Minima Processor; Mahbub Rashed, GlobalFoundries; Paul Wells, sureCore. (Organized by Jan Willis of Calibre Consulting)[/caption] The panelists included: Scott Hanson - Ambiq Micro Mahbub Rashed - GLOBALFOUNDRIES Lauri Koskinen - Minima Processor Paul Wells - sureCore Ltd., Sheffield Brian Fuller of Arm served as moderator. [caption id="attachment_12033" align="alignright" width="200"] Panel organizer Jan Willis, Calibre Consulting[/caption] Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on! #55DAC Expert Panel on Near-Threshold Voltage Sees Growing Opportunity Despite ChallengesFirst published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships Marketing Executive Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25. Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what's not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It's required innovating throughout the design process including test where Scott said they had create their own "secret sauce" to make it work. Later on in the panel, Scott described designers in near-threshold as "picojoule fanatics" to overcome the limitations in design tools which are geared towards achieving performance goals. Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design. Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield. Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor's note: sureCore's CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.] Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it's gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there's been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future. ~ ~ ~ This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original. * As explained by Rich Collins of Synopsys in the TechDesign Forum: "Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. [...] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on. Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. [...] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.

Leti and Soitec have announced a new collaboration and five-year partnership agreement to drive the R D of advanced engineered substrates, including SOI and beyond. This agreement brings the traditional Leti-Soitec partnership to a whole new dimension and includes the launch of a world-class prototyping hub associating equipment partners to pioneer with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits for partners include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, eventually leading to streamlined product viability and roadmap planning at the system level. [caption id="attachment_12066" align="aligncenter" width="644"] CEOs Emmanuel Sabonnadière (Leti) and Paul Boudre (Soitec) announcing the new Substrate Innovation Center during Semicon West '18. (Image courtesy: Leti)[/caption] Leading chip makers and foundries worldwide use Soitec products to manufacture chips for consumer applications targeting performance, connectivity, and efficiency with extremely low energy consumption. Applications include smart phones, data centers, automotive, imagers, and medical and industrial equipment, but this list is always growing, along with the need for flexibility to explore new applications starting at the substrate level. At the Substrate Innovation Center, located on Leti’s campus, Leti and Soitec engineers will explore and develop innovative substrate features, expanding to new fields and applications with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing. “Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate R D collaboration beyond the typical product road maps, beyond the typical constraints,” said Paul Boudre, Soitec CEO. “The Substrate Innovation Center is a one-of-a-kind opportunity open to all industry partners within the semiconductor value chain.” Whereas a typical manufacturing facility has limited flexibility to try new solutions and cannot afford to take risks with prototyping, the mission of the Substrate Innovation Center is to become the world’s preferred hub for evaluating and designing engineered substrate solutions to address the future needs of the industry, inclusive of all the key players, from compound suppliers to product designers. Using state of the art, quality-controlled clean room facilities, and the latest industry-grade equipment and materials, Leti and Soitec engineers will conduct testing and evaluation at all levels of advanced substrate R D. “Leti and Soitec’s collaboration on SOI and differentiated materials, which extends back to Soitec’s launch in 1992, has produced innovative technologies that are vital to a wide range of consumer and industrial products and components,” said Emmanuel Sabonnadière, Leti CEO. “This new common hub at Leti’s campus marks the next step in this ongoing partnership. By jointly working with foundries, fabless, and system companies, we provide our partners with a strong edge for their future products."

Per Arm, the industry's first eMRAM compiler IP is now on Samsung's 28nm FD-SOI technology. The announcement was made in a post by Kelvin Low, VP Marketing for ARM's Physical Design Group (read it here). He said that ARM has successfully completed their first eMRAM IP test chip tapeout. The Arm eMRAM compiler IP will be available from 4Q 2018 for lead partners. Samsung Foundry’s 28nm FD-SOI process technology is called 28FDS. eMRAM (which stands for embedded MagnetoResistive RAM) is a novel non-volatile memory (NVM) option positioned to replace incumbent NVM eFLASH, which has hit its limits in terms of speed, power, and scalability. Arm's new eMRAM compiler IP gives Samsung's 28FDS customers the flexibility to scale their memory needs based on the complexity of various use-cases, explains Low. “What drives the cost-effectiveness of this compiler IP is that eMRAM can be integrated with as few as three additional masks, while eFlash requires greater than 12 additional masks at 40nm and below,” he says. “Also, the eMRAM compiler can generate instances to replace Flash, Electrically Erasable Programmable Read-Only Memory (EEPROM) and slow SRAM/data buffer memories with a single non-volatile fast memory – particularly suited for cost- and power- sensitive IoT applications.” [caption id="attachment_11972" align="alignleft" width="300"] A key slide shown by Arm at the 2017 SOI Consortium's Silicon Valley Symposium (Courtesy: Arm and the SOI Consortium)[/caption] At the SOI Consortium's 2017 Silicon Valley Symposium, Arm said that they were stepping up their support of FD-SOI (read about that here) – and clearly they are! At that event, Arm VP Ron Moore gave a great presentation, which is freely available on our website: Low Power IP: Essential Ingredients for IoT Opportunities. Samsung, btw, has been offering 28FDS for about three years now. (ASN did a 3-part interview with Kelvin Low back in 2015 when he was a senior director of marketing for Samsung Foundry. It's still a useful read – you can get it here.) As of last fall, Samsung said it had taped out more than 40 products for various customers. And at the SOI Consortium's 2018 Silicon Valley Symposium, Hong Hoa, SVP said they'd already taped out another 20 this year (read about that here). https://youtu.be/EB14K8Gq5-w Samsung says the write speed of their eMRAM is 1000x faster than eFlash. They actually announced the industry's first eMRAM testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here). They also did an eMRAM test chip with NXP. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it above or on YouTube here.) As noted in ASN's Silicon Valley 2018 symposium coverage, the basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDS platform will be ready by the end of this year, and eMRAM beginning in 2019.

Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin's cutting-edge EDA tool for safe Power Regulation Networks implementation. THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, €120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology -- read about that here.) “Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.” The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications. Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity. The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization. Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation activity control networks for best SoC PPA. Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. "Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX," Michel Depeyrot, Dolphin Integration's Chairman, said at the time. "As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA." See the Dolphin Integration website for the full catalog of their IP, EDA and ASIC/SoC service offerings, including for GF's 22FDX.

Part 2 of this two-part piece examines the potential benefits to be realized by pairing human Subject Matter Experts with smart silicon assistants, and what these new arrangements mean for semiconductor device manufacturing. Part 1 explores best-practice perspectives on collecting and utilizing smart data in industries outside semiconductor manufacturing, one of the important takeaways from the Smart Manufacturing panel discussion at SEMI ASMC 2018. So what does this observation (i.e. the field of medicine, in what seems at first glance a big data environment, is really just clusters and clusters of loose small data connected by the collective neural network of highly trained doctors and their colleagues) mean for semiconductor manufacturing? We think it means we need to apply the same level of intense focus that we already devote to instrumented data collection and analytics in the fab to something more: we need to better capture the vast expertise of our engineering and operational talent in semiconductor manufacturing. We think we need to record what the subject matter experts (SMEs) in the fab see, hear, and think as they investigate yield excursions or machine-down problems. We need to effectively combine product, process, equipment and component subject matter expertise / subject matter experts (SME) with big data analytics to more effectively solve manufacturing problems, be they killer or be they chronic. And we must provide structured methods for incorporating inputs from and active participation of SMEs throughout the data analysis lifecycle, from collection and aggregation, through filtering, feature extraction, analysis and optimization. Some of the challenge will be in just how do we make it easy to gather information from SMEs in real time, while standing in front of equipment in the fab. Internet of Things (Iot) devices are emerging to capture and label images and sounds to enable machine learning algorithms to recognize and help diagnose manufacturing problems based on sight and sound, complementing the instrumented data. But we also need to record the thought processes our human SMEs go through in those investigations – perhaps by the SMEs talking to a smart AI-based conversational assistant who helps make “rounds.” Doing contextual analysis on this added data, combined with the instrumented data, will create the equation Human + Machine = AI (Awesome Insight). Sounds reasonable, right? We think artificial intelligence becomes too artificial if you leave the human out of the equation. AI should be augmented intelligence, where we take the expertise and creativity of the human, and combine it with the rapid computational capabilities of the computer, in order to put problem identification and solutions on steroids. But with the already huge advancements to date in data analytics, cloud, and the emergence of AI, why do improvements in quality, machine utilization, and the implementation of predictive analytics in semiconductor manufacturing seem to be creeping along incrementally, and not appearing as dramatic, step-function improvements? Call it Smart Manufacturing, call it Connected Enterprise, call it Advanced Manufacturing, or Analytics, or Cloud, or the Digital Twin … there are no shortages of terms, philosophies, and technologies available, but why aren’t we seeing their rapid adoption? It could be it’s the downside that comes with needing people. “Good business leaders create a vision, articulate the vision, passionately own the vision, and relentlessly drive it to completion.” Jack Welch. We see from other industries that smart manufacturing conversations originating with the executives of a company thinking to implement smart manufacturing programs lead to vision; however, we also see from other industries, and from our own, that realizing this vision has often been a challenge. Why is that? One reason may be that the people who are personally vested in solutions they implemented in the past, as well as those who follow a pattern of ‘how we’ve always done things’, create, inadvertently or not, persistent internal barriers hindering innovative action. Another may be that engagements with the working engineers and managers charged to be smart manufacturing implementers leads to the pursuit of low-hanging fruit, and cautious investments, that often utilize solutions that ultimately cannot scale and integrate. Not to mention the disadvantage of dealing with the legacy equipment, the legacy networks, the traditional thinking, and the lack of consistency in metrics adding to the confusion. Addressing all these barriers requires an alignment in strategy and execution, along with a plan to support the overall vision, often across the entire enterprise, which is no small matter. And then there are the standards. Having and adhering to standards in control solutions, networks, and data becomes critical in achieving real benefits from smart manufacturing. And data security. One of the other big impediments in the smart manufacturing transformation is data and IP security, another key concern (maybe the most significant) preventing us from moving forward more quickly (e.g. to cloud-based solutions) in our industry. More about that in a follow-up. Achieving synergy across all of manufacturing, from connecting equipment horizontally, through the production system (machines processes), and vertically, through enterprise systems and across production facilities, can only occur if we build standards, security, infrastructure, and human engagement throughout our ecosystem and supply chain. In simple form, the steps to do so include connecting assets, collecting and contextualizing data, and then driving business transformation with actionable insights gained from the data. With impact on every function, and every person, in the enterprise, from equipment operators in the fab through the C-Suite in HQ. Maintenance, Engineering, R D, Operations, Scheduling, IT, Procurement, Finance, HR all contribute, collaborate and benefit. Regardless of the technology, from device level analytics to predictive maintenance and optimization, the people that reside in these disparate groups need to come together with the smart machines to create a common strategy to achieve transformational results. Aligning an enterprise’s goals with its human capital is paramount to success. Therefore, we must challenge our team members and ourselves to work outside our comfort zones, and we need to be forever aware of the need for us to grow with the technology. Smart manufacturing is not necessarily about having fewer people in the fab, but it does suggest having people in the fab, perhaps with different, or upgraded, skill sets, who are even more efficient in their roles as a result of the boost they are getting from Industry 4.0. Fortunately, we now have techniques that let us combine the best, brightest, and latest and greatest analytics with our invaluable SMEs throughout the data analysis lifecycle. We’ll not only be able to deliver higher quality semiconductor manufacturing solutions all in all, but we’ll also be providing methods to more easily distribute, scale, maintain, and continually refine those hard-earned solutions. We expect that subject matter experts will continue to put the “smart” in machine-based smart manufacturing today, and for the foreseeable future. SME contributions are not an option, but, rather, an imperative for ensuring a semiconductor manufacturer’s sustained prosperity, much less its survival. Nancy Greco (IBM Watson), Dave Mayewski (Rockwell Automation), James Moyne (University of Michigan / Applied Materials), and Paul Werbaneth (Intevac, Inc.), along with Julie Jacob (Ernst Young), and Carson Henry (Micron Technology), were members of the SEMI ASMC 2018 panel discussing Industry 4.0 and the Future of Commercial Semiconductor Device Manufacturing. All opinions here are purely our own. Please contact Paul Werbaneth via email at [email protected]. The SEMICON West (July 9-11, 2018, in San Francisco) Smart Manufacturing Pavilion features working production equipment on the floor and three full days of speakers providing insights on building the infrastructure needed to enable AI. Equipment from Bosch Rexroth, Cimetrix, Rudolph Technologies, INFICON, Final Phase Systems, OMRON, DISCO and Edwards Vacuum will showcase cutting-edge smart manufacturing technologies. For information on the SEMI Smart Manufacturing initiative and how to get involved, please click here.

The CPUs in Summit, the world's new fastest supercomputer are built on 14nm FinFET-on-SOI technology. Yes, those IBM Power9 CPUs are fabbed by GlobalFoundries (you'll also find them in the z14, the most recent in IBM's z-series of servers – a series that's been on various iterations of SOI since its launch in 2003, btw). Summit's at the U.S. Department of Energy’s Oak Ridge National Laboratory (ORNL) in Tennessee, USA. It is now the top US supercomputer, and it's for science. The IBM-built Summit currently claims the spot in the Top500 as the world's smartest and most powerful supercomputer. “It is capable of performing 200 quadrillion calculations per second — or 200 petaflops — making it the fastest in the world,” says IBM's Dr. John E. Kelly, III, SVP, Cognitive Solutions and IBM Research. “But this system has never been just about speed. Summit is also optimized for AI in a data-intense world. We designed a whole new heterogeneous architecture that integrates the robust data analysis of powerful IBM Power CPUs with the deep learning capabilities of GPUs. The result is unparalleled performance on critical new applications.” And if that's not impressive enough for you, it's also #5 on the Green500 list for the world's most energy-efficient computers, posting Power Efficiency (GFlops/watts) of 13.889. [caption id="attachment_11940" align="alignright" width="300"] Summit supercomputer nodes: The IBM-built Summit supercomputer is the world's smartest and most powerful AI machine. It consists of 4,600 individual nodes. Each node contains two 22-core 3.07GHz IBM POWER9 CPUs, which are built on GlobalFoundries' 14nm HP FinFET-on-SOI technology, as well as six NVIDIA Telsa GPUs. (Photo Credit: ORNL).[/caption] As GF noted when they announced the technology in the fall of 2017 (read the GF press release here), their 14HP is the industry’s only technology to integrate a FinFET transistor architecture on SOI. Featuring a 17-layer metal stack and more than eight billion transistors per chip, the technology leverages embedded DRAM and other innovative features to deliver higher performance, reduced energy, and better area scaling over previous generations to address a wide range of deep computing workloads. These technologies have long, deep histories (and were developed in close collaboration with SOI wafer leader Soitec). Here at ASN we have a fabulous archive of pieces contributed by IBM explaining the genesis of the technology – they're great reads and still entirely pertinent: FinFET on SOI: Potential Becomes Reality (by T.B. (Terry) Hook et al, 2013) – this presents the key technical data. IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value (by Terry Hook, 2012) – this great piece busts myths and clearly explains why FinFETs on SOI deliver top performance. IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI (by Terry Hook, 2013) – explains why and how SOI increases operating voltage range, simplifies processing, reduces variation, lowers soft error rate, and enables higher circuit density. Embedded Memories in SOI – (by Subramanian S. Iyer, 2006) explains the importance of SOI in the memory part of the chip design equation. [caption id="attachment_11939" align="alignleft" width="300"] The IBM POWER9 processor delivers unprecedented speeds for deep learning and AI workloads. IBM Engineer, Stefanie Chiras tests the IBM Power System server in Austin, Texas. (Photo Credit: Jack Plunkett/Feature Photo Service for IBM).[/caption] As ORNL noted in its press release (you can read it here), the first projects will apply machine learning and AI to astrophysics, materials science, cancer research and systems biology. BTW, Summit also has a slightly smaller sister machine called Sierra, going in at the Lawrence Livermore National Laboratory (part of the Department of Energy's National Nuclear Security Administration). With 4,320 nodes (each also containing two 22-core 3.07GHz IBM POWER9 CPUs, which are built on GlobalFoundries' 14nm HP FinFET-on-SOI technology, but just four NVIDIA Telsa GPUs), Sierra's claimed the #3 spot on the June 2018 Top500 list of the world's most powerful supercomputers. And the Power 9 is now finding it's way into major data centers – like Google's (read about that here). There have been some good pieces in the press about it, including in Forbes and The Motley Fool. So yes, clearly there are exciting markets for FinFETs on SOI!

Part 1 of this two-part piece explores best-practice perspectives on collecting and utilizing smart data in industries outside semiconductor manufacturing, one of the important takeaways from the Smart Manufacturing panel discussion at SEMI ASMC 2018. Part 2 examines the potential benefits to be realized by pairing human Subject Matter Experts with smart silicon assistants, and what these new arrangements mean for semiconductor device manufacturing. The spacecraft Discovery and its HAL 9000 computer system had a digital twin. Did you know? Stanley Kubrick’s seminal film “2001: A Space Odyssey” had its theatrical release 50 years ago this April. “2001” isn’t just a great science fiction film. Rather, it’s a great work of cinema overall, across any category. (The American Film Institute lists “2001” as #15 in the AFI Top 100; a bit below “Vertigo,” a bit above “It’s A Wonderful Life.”) It’s a film so distinguished and so prescient that its lessons can inform our thinking about smart manufacturing, Industry 4.0, and artificial intelligence (AI) today. Not to give too much away, but the earth-bound digital twin of Discovery / HAL identifies a diagnostic error the onboard, Jupiter-bound HAL 9000 has made, things go awry from there, and one of the mission pilots, astronaut Dave Bowman, is forced to intervene. At the recent SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018, on 02 May 2018 in Saratoga Springs, NY, five diverse panelists representing capital equipment, IDMs, academia, the semiconductor supply chain, and smart manufacturing best practices outside the semiconductor industry engaged in a lively discussion with the ASMC attendees. They explored where “smart” is in our industry today, where it’s headed, and what that’s going to mean for us -- the professionals who have brought semiconductor manufacturing to the current state of smart, and are looking to implement an ever-smarter tomorrow. Not to give too much away, but the panelists and audience agreed that there’s nothing artificial about pairing human intelligence with machine-based smart manufacturing. Implementing an ever-smarter tomorrow in semiconductor manufacturing requires smart people just as much as it requires smart machines. Moving towards “smart” means understanding how to derive useful information and actionable intelligence from the ever-increasing pool of big data created during semiconductor manufacturing. Modern manufacturing sites are extensively instrumented today, and create massive amounts of data to consume, decipher, base decisions upon, or discard. As we dig into this problem we realize that equipment and processes in our industry are both obviously complex, but, also, subtly complex. Semiconductor manufacturing tools easily contain 100s to 1000s of components working together to produce nanometer scale, angstrom scale, or even atomic scale features using complex chemical, physical, and plasma processes. There is a plethora of potential failure points and modes, and despite our best efforts to collect more data, many processes continue to be only poorly observable. On top of that, semiconductor fabrication processes are always drifting, and the operational context is continually changing as we change product mix, process maintenance swap-out kit components, and operating conditions and recipes. Sounds like … hospitals, and healthcare? When you see your doctor, she will collect and look at your instrumented data – blood work, blood pressure, weight, and other quantifiable factors. But, typically, your doctor won’t draw a conclusion based on that analysis alone. Rather, your doctor will sit with you, ask probing questions, and record what she asked, your responses, and what she saw, what she heard, and what she thought. Then she’ll build a hypothesis, combining the “anecdotal” data with the instrumented data, and derive from that data set both a likely diagnosis and an effective course of action. In this case, beyond the instrumented data, two humans, and their natural language input, are part of the equation: the patient, with his observations and thoughts, as well as the doctor, with hers. And it’s been a formula for success. Healthcare has made huge, step-function improvements across a spectrum of deadly diseases, as well as with less-deadly chronic afflictions, by harvesting this complex input, committing the proven disease presentation – disease diagnosis – and disease treatment models to medicine’s collective memory, and then teaching the next generation of healthcare providers both the general methods and the standard protocols essential to maintaining good health and successful outcomes. Maybe, in medicine, what seems a big data environment is really just clusters and clusters of loose small data connected by the collective neural network of highly trained doctors and their colleagues. Nancy Greco (IBM Watson), Dave Mayewski (Rockwell Automation), James Moyne (University of Michigan / Applied Materials), and Paul Werbaneth (Intevac, Inc.), along with Julie Jacob (Ernst Young), and Carson Henry (Micron Technology), were members of the SEMI ASMC 2018 panel discussing Industry 4.0 and the Future of Commercial Semiconductor Device Manufacturing. All opinions here are purely our own. Please contact Paul Werbaneth via email at [email protected]. The SEMICON West (July 9-11, 2018, in San Francisco) Smart Manufacturing Pavilion features working production equipment on the floor and three full days of speakers providing insights on building the infrastructure needed to enable AI. Equipment from Bosch Rexroth, Cimetrix, Rudolph Technologies, INFICON, Final Phase Systems, OMRON, DISCO and Edwards Vacuum will showcase cutting-edge smart manufacturing technologies. For information on the SEMI Smart Manufacturing initiative and how to get involved, please click here.