- Semiconductor Market
- IC Manufacturing process
- ATE system architecture
- ATE Instrument structure
- Introduction of IC test

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최근 초연결성 환경의 구축을 위해 반드시 필요한 RF device 및 marker trend 에 대해 소개하며, 최신(mmWave) 및 전통적으로 사용되고 있는 RF device 들의 test 를 위해 필요한 조건 및 각각의 test 항목에 대한 이해를 통해 보다 effective 한 Test 환경 구축 방법에 대해 이해하는 시간이 되기를 바랍니다.

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LED driver, PMIC, BMIC , IGBT, Silicon Carbide등 Mobile, Automotive향 Power application의 전반적인 구조 및 동작을 설명하고 test에 필요한 기본적인 요소를 이해하도록 한다. 또한 이를 측정하기 위한 ATE hardware및 device의 신뢰도를 최대화할 test방법 및 환경에 대해 설명합니다.

※ 연사정보

- Test Introduction
- Wafer Test Process Overview
- Package Test Process Overview
- Memory Test Hardware System Introduction

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DRAM 등으로 대변되는 메모리소자는 지속적인 크기 축소에 따라 10nm공정기술이 적용되고 있으며 수년내에 그 한계에 도달할 것으로 예측되고 있다. 더구나 모바일기기의 확산으로 초저전력 비휘발성 메모리소자에 대한 기술개발이 강하게 요구되고 있다. 기존 메모리소자를 대체할 수 있는 차세대 비휘발성 메모리 소자로 상변화메모리, 저항메모리, 스핀메모리 소자등이 거론되고 있는데 본 강의에서는 미래 메모리 소자로 주목 받고 있는 소자들을 소개 한다.

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Xin Wu received PhD and MSc from University of California Berkeley USA and Peking University, China, respectively. Since 1993, he has worked in Xilinx (acquired by AMD in 2022) from 0.6um till 2nm generations of technologies and products, from many foundries and suppliers. His responsibilities include silicon, hetero-integration, advanced packaging, thermal mechanical solutions and many other technologies development.

※ Abstract

Mr. Moon is currently working as a technical leader (VP) for package technology development, in SK hynix. He has more than 25 years’ experience in semiconductor package development including wafer level, flip chip and 2.5D/ 3D packaging as well as conventional package.

He previously served as package development project manager for package material, process and equipment until assuming his current role in 2022. And he has been involved in the development and mass production of NAND Flash, DRAM/ Mobile, MCP, RDL, Flip chip, WLCSP and TSV.

He received degree in chemistry from Sogang University in Seoul, Korea.

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Donghan Kim is a leader of Strategy Collaboration Solution Development at Synopsys Korea. He is responsible for leading 2.5D and 3D multi-die system solution business aiming to offer a complete end-to-end solution for efficient multi-die system integration.
He has more than 20 years of experience in semiconductor industry and has worked extensively on SOC mobile chip designs such as Exynos series at Samsung Electronics. He had a strong track record of successfully developing modem, WiFi and Bluetooth chipset products.
He received MS degree in electronic engineering from Sogang university in Seoul Korea where he did research topics on wireless communications and Semiconductor.

Stefan Chitoraga is a Technology and Market Analyst specializing in Packaging and Assembly at Yole Intelligence, part of Yole Group. Within the Semiconductor, Memory & Computing division at Yole, Stefan is focused on advanced packaging platforms and processes, substrates, and PCBs. He is involved daily in the production of technology & market reports and custom consulting projects.

Prior to Yole, Stefan served as a Package Design Engineer at Teledyne E2V for 4 years, where he was in charge of the ceramic package and glass lid development for image sensors, developing mechanical design, routing, electrical and thermal simulations.

Stefan holds a Bachelor’s in Electronics and Computer Science for Industry Applications from the Polytech Grenoble (France).

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Jongsoo Choi, Ph.D. was appointed as head of marketing strategy part at Business Development Team of AVP Business, Samsung Electronics in December 2022, after completing Advanced PKG Task Force for six months. Before his new role, Dr. Choi was responsible for SoC product marketing as a director at System LSI Business from 2014.

Prior to joining the System LSI, Dr. Choi was Principal Engineer, and has led 4G mobile communication standards project at DMC R&D Center (now Samsung Research) since he joined Samsung Electronics in 2005, where he contributed to the 3rd Generation Partnership Project (3GPP) specifications which cover cellular telecommunications technologies, and also served as a vice chairman of 3GPP TSG GERAN from 2007 to 2011.

Dr. Choi received a Ph.D. degree in Electrical Engineering from the University of Ottawa, Ontario, Canada, where he focused research topics on wireless communications and adaptive signal processing.

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Dr. Vikas Dubey, is a senior scientist at Fraunhofer ENAS since 2021 with system packaging department. He is into advanced system packaging for more than 10 years. He is currently leading the research activities related to hybrid bonding, collective die to wafer bonding and several other wafer bonding technologies for MEMS/NEMS integration. Besides, in his current role he is directly responsible for project acquisition, managing public and industrial projects and related to advance system integration, hybrid wafer bonding and assembly.
Prior to joining Fraunhofer ENAS he worked as a technology manager at national nanofabrication center (NNFC) at Indian Institute of Sciences, Bangalore. During his time at APTIV services located in hungary, he was responsible for several six sigma projects which lead to million of euros in earnings.
Dr. Dubey received his PhD degree from materials engineering department from KU Leuven, where he worked at imec with his research focused on self-aligned assembly for fine pitch integration.

Dongshun Bai, Ph.D. has been with Brewer Science, Inc. since 2007. Dongshun works as the Senior Technologist & Business Development Director in the Packaging Solutions Business Unit, in charge of technology roadmap direction of new material development for advanced packaging. He also leads the Business Development team and oversees the global business activities for advanced packaging materials.

Dongshun spent his first 10 years at Brewer Science in its Advanced Technologies R&D group. Working as Senior Program Manager and Senior Scientist, he led an R&D team focused on material design and development for advanced packaging. Many materials developed by his team went to commercialization and became the major products in the portfolio.

Dongshun earned a Ph.D. degree in Chemical Engineering from Vanderbilt University, Nashville, TN, USA and a Master of Engineering degree in Chemical Engineering from the National University of Singapore. Dongshun has published numerous papers and patents and delivered many talks, including invited talks at international conferences. He currently serves as a technical committee member for IMAPS and EPTC.

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SeokHo Na joined Amkor Technology Korea in 1996 and worked for R&D engineer until now with responsibility of semiconductor material & process development. Major work is chip to substrate interconnection technology development such as wire bonding, Material Characterization, Flip Chip package CIP (chip to package interaction) and LAB (Laser Assisted Bonding) technology.

Prior to joining Amkor Technology Korea, Na received a bachelor’s degree and master’s’ degree in Material Science & Technology from Yeungnam University, Korea

※ Abstract

적층(Stack)기술, 특히 3차원 적층 기술은 패키지 공정을 통해서 반도체 제품의 부가가치를 창출하게 하는 핵심 기술이다. 같은 기능의 칩을 적층하면 기능이 배가 되며, 다른 기능의 칩을 적층하면 한 패키지 제품에서 다양한 기능을 수행하게 함으로써 하나의 칩(chip)을 통해 구현할 수 있는 반도체 제품의 특성, 그 이상을 구현함으로써 부가가치를 더 창출하는 것이다. 이 적층 기술에는 패키지를 적층하는 기술과 칩을 적층하는 기술로 구분 되는데, 특히 칩적층에서는 최근 TSV를 이용하여 전기적 특성을 포함한 여러 특성이 향상되게 만들었다. 이 과정에서는 적층 방법에 따른 기술적 난제와 해결 방법에 대해서 정리하였다.

※ 연사정보

WLP(Wafer Level Package)는 전기적 특성 향상, 열 방출 특성 향상 등 많은 장점을 가지고 있어서 그 자체로서 적용 범위가 넓어지고 있지만, 동시에 적층(stack)기술과 함께 SiP(System in Package)의 핵심 기술이 되고 있다. WLP는 fan in WLCSP, fan out WLCSP와 같이 wafer level로 전 패키지 공정을 진행하는 기술도 있고, flip chip, RDL, TSV같이 패키지 공정의 일부를wafer level로 진행하기도 하는 등 다양한 종류가 있다. 본 과정에서는 각 WLP의 종류와 공정순서, 장단점에 대해서 정리하였다.

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반도체 소자 및 전자 패키지에 적용되는 다양한 금속 배선 및 접합구조에 대한 전기적 신뢰성 기술에 대한 심화 연구 내용을 소개하고자 한다. 첫번째로, 전기적 신뢰성(electromigration) 이론 및 평가 방법에 대해 설명한 후, 무연솔더, 미세범프, TSV 등 다양한 전자패키지내 금속 접합부의 소재 및 구조에 따른 최근 전기적 신뢰성 연구결과들을 소개하고자 한다. 또한 전기적 & 기계적 복합하중에 대한 마이크로 범프의 손상기구에 대해서도 논하고자 한다. 본 강의를 통해 반도체 소자 및 전자패키징 배선의 전기적 신뢰성에 대한 기초이론, 평가기술, 실제 적용결과에 대한 학습을 통해 관련 신뢰성 문제 해결 방안 도출에 도움을 주고자 한다.

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반도체 소자 및 전자 패키지에 적용되는 다양한 금속 배선 및 접합구조의 계면 신뢰성 기술에 대한 심화 연구 내용을 소개하고자 한다. 계면접착력 이론 및 평가 방법에 대해 설명한 후, 반도체 소자내 신규 배선, FOWLP RDL 배선, Cu-Cu direct bonding, hybrid bonding 등 다양한 배선 계면에 대한 최근 계면 접착력 및 신뢰성 연구결과들을 소개하고자 한다. 본 강의를 통해 반도체 소자 및 전자패키징 배선의 계면 신뢰성에 대한 기초이론, 평가기술, 실제 적용결과에 대한 학습을 통해 관련 신뢰성 문제 해결 방안 도출에 도움을 주고자 한다.

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