Digitimes Research is predicting a doubling of the global SOI market between 2019 and 2024, "...thanks to significant expansion in applications to mobile devices, communication infrastructure, IoT devices and automotive electronics in the 5G era...". (Read the full article in Digitimes here.) Beyond the continued enormous success of SOI in front-end modules (FEMs) for RF (aka RF-SOI, which as we know is found in every smartphone on the planet), the report cites high growth specialty areas such as imaging chips for smartphones and photonics in data centers. They also predict that FD-SOI will be "massively applied" in 5G, with applications in base stations and data centers. And of course, low voltage and low power consumption will be the big drivers in IoT and wearables. All this is driving Soitec, the major SOI wafer manufacturer, to expand capacity at its facilities in France and Singapore in 2020, says the report. This is happening in strategic cooperation with Shanghai-based Simgui. As noted in ASN about a year ago, Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. At that time the two companies redefined their manufacturing and licensing relationship to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics. Separately, Okmetic of Finland, which specializes in SOI wafers for MEMS, sensors and RF, is also doubling its capacity (we covered their 2019 Shanghai presentation here.) (Image courtesy: Soitec)

Sapphire is a precious gemstone, consisting of aluminum oxide (α-Al2O3) with occasional traces of other elements such as iron, titanium, chromium, vanadium or magnesium. While sapphire stones found in nature mostly go to jewelry applications, the lab-grown sapphire – produced in a scale of up to several hundred tons per year – is widely used by the electronic industry. Now one can hardly find a branch of technology where this crystal is not used.Sapphires are mainly applied in infrared optical components, high-durability windows, wristwatch crystals, and the very thin electronic wafers used as the insulating substrates of solid-state electronics. High thermal conductivity, low reactivity, and appropriate unit cell size make sapphire an ideal material for a wide range of such electronic substrates for manufacturing of components such as LEDs and CMOS chips.SEMI spoke with Ivan Orlov, CEO of Scientific Visual, after his presentation at SEMI Strategic Materials Conference at SEMICON Europa, 12-15 November, 2019 in Munich, Germany, to learn more about the future of sapphire.SEMI: Why is sapphire an ideal material for a wide range of electronic substrates? Orlov: Sapphire undoubted advantages are its chemical inertness and ability to withstand high temperature, radiation and mechanical loads. In addition, it exhibits low dielectric loss and very good electrical insulation that makes sapphire a good candidate for substrates for LEDs and laser diodes or wafers for epitaxial growth. However, the most important advantage is that sapphire crystal lattice does very well matching semiconductor materials deposited to its surface, in particular nitrides of group III elements. To plainly benefit from these features, the grown sapphire must have as few macro- and micro-defects as possible, as substrate defects are inherited by semiconductors layers grown on the substrate surface. Hence the importance to detect defects in the raw sapphire material. This is the area where our team at Scientific Visual contributes. SEMI: Flaws are usually identified only after costly wafering and polishing steps, because rough surface of raw crystals prevents detection of the defects. What can be done to prevent defects?Orlov: Today, major players are investing in growing larger crystals without mastering in depth the growth process. Let’s face it, the semiconductor substrate industry, which is primarily based in Asia, is using empirical research methods. The raw sapphire boules are still inspected manually, and this qualitative assessment is exploited in two folds. The first step is to further process the boule. Furnace operators then adjust the growing parameters depending on the results of the manual inspection.Due to the lack of visibility into internal crystal defects, the crystal growth and its downstream processing remain an art rather than a science. The primary reasons are the difficulty to measure, locate and quantify precisely the defects in the full crystal volume. Scientific Visual equipment enables defects in raw boules to be fully quantified and categorized. With such objective measurements and knowing the full set of growth parameters, the Process Engineering (PE) team can, with the assistance of deep learning algorithms, considerably improve the growing process. Our quality control tools give Process Engineering team the “eyes” to see complete defect distribution in raw crystals, enabling it to make minor modifications in the growth process to improve yields, reduce costs and shorten the time to market for products.SEMI: What lead to those advancements and what problems did your team set out to solve? Orlov: Breakthroughs in immersion tomography, machine vision and parallel computing drove advancements in automated quality control technology. Previously crystal inspection accuracy was limited by the acuity of the operator’s eye and subjective bias. Light distortion and the diffusion of crystals made it impossible to accurately identify internal defects.Scientific Visual equipment give operators an undistorted 3D view of all defects in a crystal boule or ingot. However, only deep learning technology can correlate a hundred thousand growth data points to identify a final defect pattern.Defect pattern in non-processed item cored from EFG sapphire plate. Well visible is a typical wavy pattern of surface layers and sandwich structure in the volume. Color code marks sapphire defect density: from deep blue (non-defective material) to deep red (highest defectiveness.) SEMI: What challenges are addressed by your approach? Orlov: Increasing the yield of semiconductor substrates like Sapphire, Gallium Nitride and Silicon Carbide is paramount to reducing the price of wafers while increasing their quality. The upstream growth and downstream wafering processes are not deterministic. So far, most of the producers can only determine the quality during the late stages of the process. This condition creates huge constraints for teams in charge of production and processing. Automated Quality Control (QC) at the early stage of the production chain relieves all the unknowns, ultimately reduce the cost of material.SEMI: And what are the main opportunities?Orlov: There are massive opportunities to increase the yield and to ease the full processing chain from growth to the wafering process. Objective Quality Control (OQC) paves the way to industry-wide standards that categorize crystal quality at each step of growth to enable full certification of the defectiveness of the material and facilitate its trade and exchange.SEMI: What’s one of your predictions for the future of new materials?Orlov: The explosion of e-mobility and electric vehicles and the development of other green technologies will drive rising demand for low-defect sapphire, silicon carbide and gallium nitride substrates thanks to the streamlining of the full processing chain. Manual quality control will soon give way to full automation as quality control in sapphire and other raw crystals production is the only missing link in a fully automated semiconductor production chain. I believe that in five years, automated raw crystal inspection will become standard in the industry. Our mission is to empower every crystal grower to achieve this important milestone.Dr. Ivan Orlov obtained a Ph.D. in Crystallography from the Federal University of Technology in Switzerland EPFL and an MSc in Solid-State Physics in Moscow, Russia. Ivan co-founded Scientific Visual in 2010 to answer the challenge of the synthetic crystals industry struggling with high defect yield. Prior to this he worked in a company specialized in diamond optics. He has more than 10 years of experience in R D with focus on optical materials, industrial crystals and non-destructive quality control technologies. Dr. Orlov was a SEMI Task Force member for sapphire standard development in China and collaborates with ISO committee in Switzerland to establish industry-wide sapphire quality standards.Serena Brischetto is senior marketing and communications manager at SEMI Europe.

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

When we entered 2019, our priorities in SEMI Global Advocacy were crystal clear: Continue to advance our public policy priorities under the 4 T’s – Trade, Tax, Talent and Technology – and move toward a global reach. We raised SEMI’s profile on the world stage in representing arguably the most strategic industry sector today as we trained our sights on a number of issues across all four pillars, not the least of which was trade. Along the way, we educated key policymakers about the impact of their decisions on the global semiconductor supply chain, member companies and regional economies.While no one organization can resolve current global trade issues, SEMI did exert its influence effectively on behalf of its members. For example, when Japan’s Ministry of Economy, Trade and Industry (METI) announced its decision to tighten export controls with South Korea in July, SEMI immediately engaged METI and Korea’s Ministry of Trade, Industry and Economy (MOTIE) to make clear to METI the potential repercussions of its decision. In parallel, we worked to prevent a retaliatory escalation by MOTIE. Indeed, significant trade challenges remain as tariffs and export controls continue to take their toll on our industry’s globally integrated supply chain. We have much work ahead to ensure our members’ voices continue to be heard. Our well over 100 meetings with government officials this year is only the start of sustained outreach and engagement to better serve our members’ public policy interests. To that end, and based on member input, in 2019 SEMI Global Advocacy made it a priority to restructure to improve communications among our regions around the globe and strengthen member engagement. Each regional office responsible for government affairs is now staffed with a global advocacy liaison. In addition, we have increased staffing in the SEMI Europe office to better address the ever-changing regulatory environment and develop the European Union’s talent pipeline.In SEMI’s advocacy headquarters in Washington, DC, we have filled a new position – Vice President of Industry Advancement and Government Programs – to place greater focus on identifying opportunities to advance programs aligned with member, industry and government interests. We have also filled two additional positions in DC – a Vice President of Global Public Policy and Advocacy and a new Manager of Public Policy and Advocacy – dedicated to public policy work. Both are steeped in experience in trade, export controls and tax policy. In addition, our new Executive Director of the SEMI Foundation boasts expertise in developing and scaling workforce development programs.The end of 2019 culminates the first phase of strategic personnel and program adjustments we envisioned over a year ago and the beginning of more muscular, adaptive advocacy engagement communications. Today, we are in a much stronger position to support you, our members, and meet the public policy priorities established by the SEMI Board of Directors and Board of Industry Leaders. We’re immensely thankful for your continued engagement and look forward to working to advance your interests in 2020 – SEMI’s 50th anniversary!Mike Russo is Vice President of Industry Advancement and Government Programs at SEMI.

In a shining hour for Prof. Mike Czerniak, environmental manager for Edwards Ltd., a SEMI member company, and Chemistry Prof. Simon O’ Doherty of the University of Bristol, the educators presented a case study on efforts by the semiconductor and aluminum industries to mitigate greenhouse gas emissions – part of an online Bristol Futures course that won the National Award in the Next Generation Learning and Skills category of the prestigious Green Gown Awards.The online students hailed the semiconductor industry as an exemplar of applying abatement systems to the reduction of greenhouse gas emissions as well as an excellent example of an engaged industry and true dedication to sustainable development. The course – Unleash Your Potential: Sustainable Futures – encourages students to learn about the sustainability challenges of the modern world and make a positive contribution to society.This four-week online course takes learners on a journey to explore their personal views and understanding of sustainable development, then addresses challenges faced by the city of Bristol and globally before bringing them back to the personal. The case study features academics and industrial partners discussing the challenges of greenhouse gas emissions and the benefits of cutting-edge collaborations aimed at driving long-term solutions.Hosted on the FutureLearn platform and offered three times a year, the free online course is structured around the United Nations Sustainable Development Goals (SDGs) to provide fascinating, solution-based narratives in the era of the Anthropocene.The University of Bristol launched Bristol Futures in 2018 and the initiative centers on three themes: Global Citizenship, Sustainable Futures and Innovation, and Enterprise. The interdisciplinary team that developed the Sustainable Futures theme consisted of myself (Ph.D. candidate, Chemistry/Geography), Chris Preist (Professor, Computer Science and Sustainability) and Aisling Tierney (Ph.D. Archeology); this interdisciplinary approach was introduced by sustainable development pioneers Chris Willmore (Professor of Law and Sustainability) and Martin Wiles (Head of Sustainability)The case studies have one particular strength – a sweeping diversity of contributors to reflect the endless possibilities of sustainable development. The 10-minute videos engage learners with academics, researchers, industrial experts, students, government and non-government organizations and communities. The Head of Unesco for Maritime Affairs, goat herders in Croatia, authors, the Intergovernmental Panel on Climate Change (IPCC), first-year university students – they all add their special flavor to sustainable development.Established in 2004, the Green Gown Awards recognize the exceptional sustainability initiatives being undertaken by universities and colleges. We are extremely proud that this online course has been recognized as sector leading by the Green Gown Awards and thrilled that the Sustainable Futures online course has been taken by more than 5,700 people, including over 2,000 students at the University of Bristol.We hope that the Sustainable Futures family will continue to grow and invite you to join us in this exploration of sustainable development, global challenges and yourself in our next run starting in February 2020!Eleni Michalopoulou is a Ph.D. candidate, Atmospheric Chemistry Research Group, School of Chemistry, at the University of Bristol.

High-tech industry clusters in the bustling northern Taiwan port city of Hsinchu look set for an upgrade. Long a world-class hub of the semiconductor and optoelectronic technology industries, Hsinchu City is laying out plans to work with SEMI to attract more international companies, generate more jobs, promote Hsinchu’s development and help grow Taiwan’s microelectronics industry. High-tech heavyweights such as TSMC, UMC, MediaTek, Realtek, and AUO are all headquartered in The Windy City. The Industrial Technology Research Institute (ITRI), a leading Taiwan research center and incubator, also calls Hsinchu home, and the city boasts one of the highest concentrations of educational institutions in the region, a roster that includes National Chiao Tung and National Tsing Hua universities. Hsinchu’s thriving relations with these industry, academic and research partners have made it a hotbed of innovation, with numerous large Taiwanese and foreign companies having opened local offices. No less than these partners, the city – like SEMI – is committed to innovation.In a recent visit to the SEMI Taiwan office in Taipei, a Hsinchu City government team led by mayor Lin Chih-Chien, met with Terry Tsao, global SEMI chief marketing officer and president of SEMI Taiwan, to explore collaboration opportunities in areas such as technology subsidies, policy, education, and infrastructure. The meeting built on a relationship between the city and SEMI Taiwan that sprouted after SEMI executives and Hsinchu officials joined ITRI to host the Autonomous Driving System Platform in Open Fields kick-off ceremony – an initiative to accelerate Taiwan’s adoption of smart transportation technologies – at SEMICON Taiwan 2019.At the meeting, Mayor Lin highlighted that Hsinchu has long attracted high-tech companies by cultivating a business-friendly climate through incentives such as subsidies for infrastructure buildouts. He hopes to work with SEMI to promote to members the benefits of setting up local offices in Hsinchu City.With both Hsinchu’s high-tech clusters and SEMI’s global members deeply reliant on skilled workers for sustaining innovation and growth, Tsao and Mayor Lin agreed that inspiring students to pursue an education and careers in science, technology, engineering and mathematics (STEM) is vital to building a high-tech talent pool. One collaboration opportunity SEMI Taiwan is eyeing is to launch Taiwan’s first SEMI High Tech U (HTU) program in Hsinchu to spark the interest of school-age children through STEM educational activities at school camps or art and cultural centers. SEMI’s STEM discovery program offers hands-on activities and experiential learning led by industry volunteers. Since 2002, HTU has reached some 8,000 high-school students in 12 U.S. states and nine countries.Emmy Yi is a marketing specialist at SEMI Taiwan.

The industry continues rewarding luminaries of the SOI ecosystem. Recently recognized are Jean-Pierre Raskin for RF-SOI, Lattice Semi and NXP for FD-SOI products, and Bich-Yen Nguyen for her work in SOI. The SOI Consortium extends hearty congratulations to all the winners and their teams. Professor Jean-Pierre Raskin was awarded by the prestigious Médaille Ampère 2019 for the originality of his scientific work in the field of RF-SOI technologies for wireless communication. The international award was delivered by Mr. François Gérin, president of the SEE - Société de l'électricité, de l'électronique et des technologies de l'information et de la communication, on December 3rd, 2019, in Paris, France. We’ve long covered the work of Professor Raskin and his UCLouvain team – which is largely responsible for why SOI is in every smartphone on the planet. It’s a great story (read it here) and it goes on! In his Ampère acceptance speech, Professor Raskin said, “...significant industrial research and development is being performed toward fully integrated SOI front-end-modules. Notably, the 45nm PD-SOI [RF-SOI] and 28nm and 22nm FD-SOI nodes are being extensively designed with to develop 5G mm-wave low-noise amplifiers (LNA), power amplifiers (PA) and switches, in particular at 28 GHz. […] Overall, SOI is expected to be a big contender as a technological platform to enable mass production of millimeter wave 5G and ultra-low power RF IoT devices and products in the near future.” [caption id="attachment_27119" align="alignleft" width="294"] Lattice CEO Jim Anderson (left) and Mark Lipacis (right), Managing Director of Jefferies (Courtesy: GSA Lattice Semi)[/caption] Lattice Semiconductor was the recipient of the Global Semiconductor Alliance’s (GSA) 2019 Analyst Favorite Semiconductor Company award based on technology and financial performance. The GSA awards recognize the achievements of top performing semiconductor companies and the 2019 winners were announced at the annual GSA Awards Ceremony held on December 5, 2019. In thanking his team, Lattice CEO Jim Anderson, added, "We are even more excited about the solid execution of our product roadmap, specifically, the accelerated product rollouts of both CrosslinkPlus and our next generation FPGA platform based on FDSOI technology, which will be key catalysts to our achieving sustained long-term revenue and profitability growth.” [caption id="attachment_27120" align="alignright" width="71"] (Courtesy: NXP)[/caption] NXP was a recipient of a Best-in-Show Award at the 2019 Arm TechCon this fall. As was noted by Brandon Lewis, Editor-in-Chief of Embedded Computing Design, “The i.MX RT1170 crossover MCU marks a technology breakthrough in MCUs, running up to 1GHz while maintaining low-power efficiency. It is architected to deliver a record-setting performance, with a 6468 CoreMark score and 2974 DMIPS while executing from on-chip memory. The solution uses advanced 28nm FD-SOI [note: fabbed by Samsung Foundry] technology, making NXP the first company to build MCUs in this advanced technology node. This new MCU family is redefining the "edge" and MCU landscape, bringing unprecedented performance and high levels of integration to propel industrial, IoT, and automotive applications.” And finally, Soitec Senior Fellow Bich-Yen Nguyen was elevated to the status of IEEE Fellow in the Class of 2020 “for contributions to silicon on insulator technology”. As previously noted in her IEEE bio, “Her honors and awards include the Dan Noble Fellow, the highest technical award at Motorola; the Master of Innovation Award; and the first national Women in Technology Lifetime Achievement Award. She holds over 200 worldwide patents and has authored more than 180 technical papers on integrated circuit technologies.”

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

We live in the New Industrial Age. Manufacturing is undergoing a profound transformation, driven not only by technological (e.g. Artificial Intelligence, robotics, IoT) but also societal, market and regulatory developments that have fundamental implications for the workforce competency requirements. How can education and training systems keep pace with this unprecedented change? How does a future-proof curriculum look like?This topic has been extensively addressed by the Curriculum Guidelines for Key Enabling Technologies (KETs) and Advanced Manufacturing Technologies (AMT) initiative (2017-2019) of the Executive Agency for SMEs (EASME) and DG GROW of the European Commission. Carried out by PwC, the initiative focuses on the promising ways of organising learning experiences of individuals and groups in the New Industrial Age. The initiative produced the Curriculum Guidelines 4.0 that aim to equip all key stakeholder groups with the knowledge base needed to transform the existing curricula.The guidelines were developed based on the extensive state-of-play analysis and active stakeholder contribution by means of expert workshops, pan-European online surveys, in-depth interviews and individual expert consultations. All key stakeholder groups were involved in the preparation of the guidelines, including the representatives of education and training providers, industry, policymakers and supporting structures (e.g. industry associations, cluster organisations and trade unions), as well as learners themselves. SEMI was among the key contributors. The guidelines were presented to the public at the EU Conference on Skills for Industry: Curriculum Guidelines 4.0 in Brussels on 26 November, 2019.The guidelines aim to be applicable for both designing fundamentally new educational offers and/or advancing the existing curricula, depending on the level of required change. They address non-tertiary vocational education and training, higher education and on-the-job training for the manufacturing-related domains.The guidelines follow a holistic approach covering a broad spectrum of dimensions relevant to curriculum design and implementation, namely: Strategy: defining core values, commitments, opportunities, resources and capabilities of an educational/training institution Collaboration: promoting practices that move beyond the typical institutional collaboration patterns and engaging individuals and communities Content: defining the nature of educational content, including specific principles related to the actual content of the curricula Learning environment: creating specific environment during the program, e.g. stimulating multidisciplinary orientation, design thinking, team spirit, collective problem-solving, risk-taking behaviour, experimental approaches Delivery mechanisms: establishing means by which learners experience and access education/training; paying special attention to technology-enabled learning Assessment: identifying most appropriate forms of assessment, including advantages and disadvantages Recognition: exploring appropriate formal and informal ways of recognition Quality: identifying the determinants of education training quality: what makes learners’ and employers’ perception different? Based on the results of the pan-European survey, the four key elements that require the most substantial change are Strategy, Collaboration, Learning Environment and Content.The guidelines will be tested in practice in the context of METIS (Microelectronics Training, Industry and Skills), a project recently launched by SEMI and 19 partners from 14 countries. Aligned with the Curriculum Guidelines 4.0, METIS will establish a Microelectronics Observatory and Skills Council consisting of representatives from industry, academia, NGOs, think tanks and government. The consortium will develop a New Skills Strategy for the microelectronics industry in Europe with a focus on raising occupational profiles and skills critical to the future of the sector.METIS will enable a new industry-driven curriculum with 43 modules integrating online education and work-based learning in microelectronics design and manufacturing. Training will focus on chip design, system design, basic of manufacturing and key competencies. METIS is a Sector Skills Alliance co-funded by the Erasmus+ Program, receiving 4 million EUR funding from the EU.Preparing students for lifelong learning, offering Big Picture education, creating effective learning ecosystems, applying problem-based and student-centric approaches, shifting from human-robot interactions towards human-machine collaboration – these are just some examples of the curriculum guidelines principles highlighted in the guidelines.The guidelines aim to offer key highlights, indicate a variety of possibilities and identify sources for more detailed information and inspiration. The guidelines by no means aim to serve as a standardised detailed recipe for organising education and training processes, as there is no one best way to approach it. The diversity of learners’ needs and contexts per definition implies a need for multitude of approaches, which could also be combined in their own unique/customised education and training solutions.The Curriculum Guidelines 4.0 will be publicly released in January 2020, and will be available on the EU Publications. More information about this and related initiatives can be found at https://skills4industry.eu/. Dr. Kristina Dervojeda leads the PwC Innovation Research Centre in the Netherlands.

With all major global electronic equipment OEMs having now reported their third quarter financials, we estimate that combined equipment sales increased 0.4 percent in 3Q’19 versus 3Q’18 and 2 percent sequentially from the second versus the third quarter of this year.