Part 1 of this article discussed the Memory Inventory Cycle Index and compared it with memory device sales and memory fab equipment investments. This article, the second of the two-part series, illustrates how the Memory Inventory Cycle Index starts to weaken before memory sales of the top three memory suppliers decline. It also shows how the Memory Inventory Cycle Index peaked in the fourth quarter of last year along with YoY growth rates for both memory sales and memory fab equipment investments.In addition to the weakening signaled by the Memory Inventory Cycle Index, memory suppliers are facing headwinds in the form of tariffs as mentioned in Micron’s most recent earnings call. The U.S.-China trade dispute could reduce Micron’s profitability; China granted a preliminary injunction to prevent Micron’s Chinese subsidiary from manufacturing and selling in China this July. However, it is very difficult to quantify the risk the tariffs pose to the future of the memory market.On the other hand, the YoY growth rate of semiconductor sales according to the World Semiconductor Trade Statistics is closely tied to China’s manufacturing sector as shown by the Purchasing Managers Index (PMI) New export orders and Orders in hand sub-indexes. Figure 3 shows that as the growth rate of new exports and order backlog slows, the YoY growth rate of semiconductor sales will be adversely impacted. As the largest consumer of semiconductors in the world, China will bear the brunt of the slowing market. Figure 3. Memory Inventory Cycle Index China manufacturing sector PMI’s sub-indices * RemarksChina PMI’s sub-indices are on the basis of the data published by NBS (National Bureau of Satistics of China). Also those data were calculated based on 12MMA (12-month moving average) to minimize seasonal fluctuation. The YoY growth rate of the 3-month moving average of semiconductor sales in China alone, China and Asia Pacific, and all regions showed additional declines in July (Figure 4). Monitoring the Orders in hand and New export orders sub-indices for China and China’s semiconductor consumption and WSTS sales revenue in China can help track the risk of trade disputes. Figure 4. YoY growth rate of semiconductor sales revenue in China and Asia Pacific * Remarks1) Regions as defined by WSTS’ Bluebook.2) Sales revenue were calculated based on 3MMA (3-month moving average value). A review of the relationship between the Memory Inventory Cycle Index, semiconductor sales, and memory fab equipment investment growth rates suggests we have passed the peak in the current cycle. However, bear in mind that the Work In Process (WIP) to Finished-goods inventory ratio has sharply increased since 2017 as shown in Figure 5. The increase in WIP inventory could be attributed to the increasing technical challenges associated with 3D NAND stacking and DRAM scaling. As a result, the proportion of finished-goods inventory in total inventory remained low until the second quarter of 2018, possibly implying that memory demand remained healthy in spite of the contraction modeled by the Memory Inventory Cycle Index. Figure 5. The proportion of finished-goods inventory in the total inventories * Remarks 1) All inventories data from 3 companies’ financial reports were calculated based on 4-quarter moving average.2) Total Inventory accounts for the sum of Finished-Goods, WIP, and Raw materials inventory.3) Company data complied by SEMI. The Memory Inventory Cycle Index has entered a period of contraction, which is supported by Micron’s weak guidance for its fiscal first quarter of 2019 (September to November). The outlook for memory sales and memory fab equipment investments reported by WSTS and SEMI, respectively, also suggests that a market correction is underway. While the low proportion of finished-goods inventory does not threaten the market yet, it should remind industry observers to view high WIP inventories with caution. Unlike past inventory cycles, the high inventory levels could burden the memory market in the absence of sustainable demand.Sungho Yoon is a senior market research analyst in Industry Research and Statistics at SEMI. SEMI China IC Ecosystem ReportLearn more about 30 new fab construction projects underway or planned in China in the newly released SEMI China IC Ecosystem Report. The research report is a comprehensive update and analysis of China's IC manufacturing ecosystem with charts, graphs, tables and maps.

SEMI met with Heinz Martin Esser, managing director at Fabmatics GmbH, to discuss how existing 200mm semiconductor fabs can master the challenges of a 24x7 production under highest cost and quality pressure by implementing intralogistics automation solutions. The two spoke ahead to his presentation at the Fab Management Forum at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Looking at the latest production capacity data for 2018 – it is a 200mm fab boom. Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment. Do you think this trend will continue the next years or is it only a short term run on 200mm fabs?Esser: We at Fabmatics believe in a long-term trend. The emergence of the Internet of Things and growing digitalization in all areas of life will continue to increase demand for integrated circuits (ASICs), analog ICs, high-performance components and micro-mechanical sensors (MEMS) in the coming years. Many of these semiconductor elements should be produced in 200 mm fabs.SEMI: How does Fab automation contribute to increase capacity of existing, mature 200mm fabs?Esser: We are convinced that fab automation is one of the greatest potentials for older 200mm factories to effectively master increased demand, increasing efficiency, quality assurance and flexibility at the same time. In particular, material flow automation, which is often the missing link between existing equipment in different production areas, can help increase productivity in an elementary way.If you analyze how long valuable tools typically wait for loading and unloading, you can see a direct effect of the intralogistics automation system, which leads to a significantly higher utilization of process equipment by making the material flow independent from human performance. Additional side effects such as reduced cycle time, stable fab flow factor or flattened WIP shafts further increase the contribution of material flow automation to get the most out of existing mature factories. Older does not mean obsolete.SEMI: What are the biggest challenges for a successful implementation?Esser: There is no single challenge when you automate an existing mature fab. Instead, you face a whole variety of challenges you have to tackle, ranging from historically grown non-aligned fab layouts over non-linear material flows and older non-standardized equipment to “automation unfriendly” fab environment. Also you should not underestimate the efforts to overcome the practice manual fab operation people in the cleanroom are so familiar with for many years. Before doing automation you have to think automation, i.e. you have to question all processes to make them ready for automation.SEMI: What are the key drivers to automate a mature fab today: costs, process stability, quality or a combination of them?Esser: This question should be better asked to our customers, but we believe it is a mix of many impacts. Most likely everybody sees the cost reduction at first, but we get more aware of process and performance stability as well as quality requirements – and here our customers’ play the most important role – become more and more focused.SEMI: What do you expect from SEMICON Europa 2018 and why do you recommend attending the Fab Management Forum?Esser: This year SEMICON Europa will co-locate with electronica. So it`s going to be the greatest trade fair for electronics manufacturing in Europe. We will meet innovators and decision-makers across the whole electronics supply chain. The Fab Management Forum addresses a highly topical question that concerns all semiconductor manufacturers not only in Europe - how to handle complexity and enable the necessary flexibility to cope with customers' needs. High-ranking speakers will give an insight into the latest technologies and best practices. I am looking forward to the lively exchange with the participants and taking away new impulses for our business. Heinz Martin Esser is managing director at Fabmatics GmbH, responsible for sales and marketing, customer service and administration. He studied supply engineering at the University of Applied Sciences in Cologne and later earned a university degree in business administration. Serena Brischetto is a marketing and communications manager at SEMI Europe.

Even for someone who has been in this industry since the days of the TI Datamath 4-function calculator and the TMS1100 4-bit microcontroller (yes, that’s been a LONG time – the movie Grease premiered the same year!), it is sometimes hard to grasp the scope and complexity of what happens in today’s leading-edge semiconductor gigafabs. In fact, the only way to comprehend the enormous volume of transactions that occur is to consider what happens in a single minute – this is illustrated in the infographic we have labeled “The Gigafab Minute.”* It’s amazing enough to think that a single factory can start 100,000 wafers every month on their cyclical journey through 1500 process steps… and have 99%+ of them emerge 4 months later to be delivered to packaging houses and then on to waiting customers. It’s quite another to realize that all of this happens continuously (24 x 7) and automatically. “How is this possible?” you ask.Well, a big part of the solution is the body of SEMI standards which have evolved since the early 80s to keep pace with the ever-changing demands of the industry. From an automation standpoint, many of these standards deal with the communications between manufacturing equipment and the factory information and control systems that are essential for managing these complex, hyper-competitive global enterprises.A significant characteristic of these standards is that they have been carefully designed to be “additive.” This means that new generations of SEMI’s communications standards do not supplant or obsolete the previous generations, but rather provide new capabilities in an incremental fashion. To appreciate the importance of this in actual practice, consider how the GEM, GEM300, and EDA/Interface A standards support the transactions that occur in a single Gigafab Minute.Starting at 1:00 o’clock on the infographic and moving clockwise, you first notice that 2.31 wafers enter the line. Of course, these are actually released in 25-wafer 300mm FOUPs (Front-Opening Unified Pod), but 100K wafers per month translates to 2.31 per minute. Since these factories run continuously, once the line is full, it stays full. And with an average total cycle time of 4 months, this means that there are 400K wafers of WIP (work in process) in he factory at any given time. This number, and the total number of equipment (5000+), drive the rest of the calculations.GEM (Generic Equipment Model) – SEMI E30, etc.The GEM messaging standards were initially defined in the early 90s to support the factory scheduling and dispatching applications that decide what lots should go to what equipment, the automated material handling systems that deliver and pick-up material to/from the equipment accordingly, the recipe management systems that ensure each process step is executed properly, and the MES (Manufacturing Execution System) transactions that maintain the fidelity of the factory system’s “digital twin.”Every minute of every day, GEM messages support and chronicle the following activities: 240 process steps are completed (i.e., 240 25-wafer lots are processed), 300 recipes are downloaded along with a set of run-specific adjustable control parameters, and 600 FOUPs are moved from one place to another (equipment, stockers, under-track storage, etc.). For each of these activities, the factory’s MES is notified instantaneously.GEM300 – SEMI E40, E87, E90, E94, E157With the advent of 300mm manufacturing in the mid-to-late 90s, a global team of volunteer system engineers from the leading chip makers defined the GEM300 standards to support fully automated manufacturing operations. Starting at 5:00 o’clock on the infographic, the number of transactions per minute jumps almost 3 orders of magnitude, from the monitoring of 900 control jobs across 4000 process tools to the tracking of 360,000 individual recipe step change events. This level of event granularity is essential for the latest generation of FDC (Fault Detection and Classification) applications, because precise data framing is a key prerequisite for minimizing the false alarm rate while still preventing serious process excursions. In this context, more than 6000 recipe-, product- and chamber-specific fault models may be evaluated every minute.Simultaneously, the applications that monitor instantaneous throughput to prevent “productivity excursions” and identify systemic “wait time waste” situations depend on detailed intra-tool wafer movement events. In a fab with hundreds of multi-chamber, single-wafer processes, 75,000 or more of these events occur every minute. EDA (Equipment Data Acquisition) – SEMI E120, E125, E132, E134, E164, etc.Rounding out the SEMI standards in our example gigafab is the suite of EDA standards which complement the command and control functions of GEM/GEM300 with flexible, high-performance, model-based data collection. The EDA standards enable the on-demand collection of the volume and variety of “big data” required from the equipment to support the advanced analysis, machine learning, and other AI (Artificial Intelligence) applications that are becoming increasingly prevalent in leading semiconductor manufacturers. As EUV (Extreme Ultraviolet) lithography moves from pilot production to high-volume manufacturing at the 7nm process node and beyond, the litho process area will become a major source of process data by itself, generating 10 GB of data every minute. This is in addition to the 100 GB of data collected from other process areas. The End ResultThe final wedge (12:00 o’clock) in our infographic highlights the real objective – which is producing the millions of integrated circuits that fuel our global economy and provide the technologies that are an integral part of our modern way of life. Assuming a nominal die size of 50 square mm (typical of an 8 GB DRAM), the 2.31 wafers we started at 1:00 o’clock result in almost 3200 individual chips. But none of this would be possible without the pervasive factory automation technology we now take for granted. So, as you finish reading this posting on whatever device you happen to be using, take a micro-moment to acknowledge and thank the hundreds of standards volunteers whose insights and efforts made this a reality!You may not be responsible for running a gigafab anytime soon, but the SEMI standards used in this setting are no less applicable to any Smart Manufacturing environment. Give us a call if you’d like to know more about how these technologies can benefit your operations for many years to come.Alan Weber is Vice President, New Product Innovations, at Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University. For more information on SEMI Standards, please click here.

SEMI spoke with Balaji Nandhivaram Muthuraman, Package and Material Simulation engineer at Dialog Semiconductor, about the state of reliability testing for wafer-level chip scale packages ahead of his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Since the beginning of package development reliability testing has played a key role in Wafer Level Chips Scale package (WLCSP) investigation. Lately, the role of simulation and predictive reliability significantly contributed in reducing package development time. To what extend can we predict potential failures for WLCSP packages in an early design phase by simulation?Muthuraman: Reliability testing is essential and crucial for the electronic packages. It is during the package development phase that several design iterations need to be considered and, in some cases, many feasibility studies for the package are executed. This means we require significant reliability test measurements, which could influence product-development time. For example, Temperature Cycling on Board (TCoB) reliability testing would take approximately 65-75 days for testing the package reliability subjected to 1500 temperature cycles. Each cycle involves exposing the device at hot and cold temperatures with a specified temperature profile. Executing such Board Level Reliability (BLR) tests for all feasible package designs is a tedious process that could lead to an increase in package development time. This is the stage where numerical simulation methodology helps us to foresee potential failures in Board Level Reliability. Predicting delamination or cracking of passivation/metal interface layers based on the WLCSP design layout and estimating the characteristic life of smart device subjected to temperature load are some classic examples of predicting WLCSP package behavior in an early design phase by simulation methodology.SEMI: We can definitely say that predictions occurring during the early stage are key to success. But how exactly can numerical simulation help estimating?Muthuraman: From a thermal reliability point of view, determination of the optimum material combination – bill of materials for device – is used to predict whether a heat sink is required for the device to meet thermal performance. This is not all. At an early design stage, the simulation methodology can be used to estimate device performance under varying thermomechanical loads. Numerical simulation at early package development phase helps the researchers by predicting the possible temperature contour field and stress contour field of the smart device under a given loading condition. The estimation accuracy of potential issues through numerical simulation depends on the material models implemented and consideration of realistic load condition under which the package operate in real life situation. For example, engineering judgements can be made using numerical simulation of Solder Joint Reliability (SJR) analysis to decide whether an Underfill material is required between the Package and the Printed Circuit Board (PCB).SEMI: Are all conditions tested during the reliability investigations specific to fit a certain type of applications or do these vary?Muthuraman: Reliability investigations are based on the end application of the electronic devices. For example, handheld device applications will be exposed to a reliability condition up to a maximum of +85oC, whereas smart devices designed for an automotive application would be tested with a typical temperature of +125 oC or up to +150 oC. In some cases, the testing conditions are customized based on specific customer requirements. Moreover, reliability conditions can also be customized to study some specific failure mechanism. SEMI: Can you describe for which one?Muthuraman: Thermal cycling profile is based on device application and/or specific requirement from our customer. For example, handheld devices use a typical temperature range of +85°C to -40°C with 20°C/min ramp time and 20 minutes of dwell time. There is possibility of adjusting the ramp and dwell time of the Temperature Cycling qualification test, provided such accelerated test does not lead to other failure modes.SEMI: What failure mechanism was the subject of the study in this specific case?Muthuraman: Electronic package reliability behavior without and with underfilled devices is explained in this study with the help of temperature cycling on board (TCoB) measurements and validated with numerical simulation. In the paper to be presented at SEMICON Europa, failure occurring at the interface of the solder and Under-Bump Metallization (UBM) structure is discussed. Behavior of such failure mechanism is illustrated with different WLCSP package sizes subjected to varying thermal load condition. One of the key aspects of the subject is the board-level reliability (BLR) measurement and simulation validation showing how the failure mode could be shifted from solder joint to the metal interface layers between UBM and interconnection to Silicon Chip, depending on the WLCSP design layout. The reasons for such shifts in Failure phenomenon are explained and necessary design optimization is suggested for improvement. Another key aspect of this study is determination of Fatigue Life Model for WLCSP family using the SACQ solder. SEMI: Are you currently working and experimenting on something particularly exciting?Muthuraman: Recently, we concluded our engineering analysis of thermomechanical reliability of Large Wafer Level Chip Scale packages. In September 2018, I presented this research work in an International Conference held in Dresden, Germany. Dialog Semiconductor GmbH was awarded the “Best Paper Presentation for the year 2018” for this work. This success is attributed to the entire team of Package and Material simulation experts at Dialog Semiconductor GmbH lead by Mr. Baltazar Canete and IC Package-Design Simulation group managed by Mr. Rajesh Aiyandra. We have started our investigation on the influence of Board Level Reliability of WLCSPs due to varying metal concentration of inter-metallic layer. We, at Dialog, are also working on possibility of thinner WLCSP. All these activities would include extensive Temperature Cycling on Board (TCoB) measurements, Statistical Analysis of measurement Data and would then be validated by Numerical Simulation. SEMI: What are your expectations for the future and why would you recommend attending SEMICON Europa Advance Packaging Conference?Muthuraman: SEMICON Europa is an important platform for Dialog Semiconductor GmbH to showcase the latest developments in the semiconductor industry. It is an opportunity to meet other industry experts, partners, and customers, and exchange various innovative ideas and to get new insights. Many semiconductor companies are based around the Munich area as well world-class universities. We are particularly interested in innovation, workforce and talent development themes. SEMICON Europa gives us a platform for greater interaction with the academicians and research scientists. This way, we bridge the gap between industry and University researches, thereby moving forward in innovative technologies. We, as Dialog Semiconductor GmbH, have also a development center near Munich (Germering). Our expectations for the future are very positive and vibrant. We are always ready to take up the industry challenges and demands and provide the best-in-class solutions to our product users. Dialog Semiconductor GmbH is certainly poised for higher growth in coming years. Balaji Nandhivaram Muthuraman BioBalaji Nandhivaram Muthuraman is a Packaging and Material Simulation engineer at Dialog Semiconductor GmbH, Germany. He has authored/co-authored conference publications including in the area of molecular dynamics simulation on assembly of carbon nanostructures; Analysis of thermoset material used in smart devices and reliability of wafer level packages. Recently, he has been awarded with the “Best Paper Presentation for year 2018” in the area of Board Level Reliability of Wafer Level Chip Scale Packages, in a recently held international semiconductor conference. His current areas of working interest include reliability investigation of electronic packages and developing fatigue models for reliability assessment of Dialogs products. He obtained his Bachelor’s degree in Aeronautical Engineering from Anna University, India and Master’s degree in Computational Mechanics of Materials and Structures from University of Stuttgart, Germany. Serena Brischetto is a marketing and communications manager at SEMI Europe.

Micron, one of the top three memory semiconductor companies, reported solid results for the fourth quarter of fiscal 2018 (June to August) to extend a multi-quarter string of strong growth. However, the company’s mediocre guidance for the current quarter has raised concerns that memory demand will start to slow.To shed light on this super memory cycle, which began in the second half of 2016, this article examines correlations among the top three memory suppliers’ sales revenue, quarterly inventory levels, World Semiconductor Trade Statistics (WSTS) market data, and memory fab equipment investments reported by SEMI.The Memory Inventory Cycle Index, which is based on financial data reported by Samsung, SK Hynix and Micron, is the difference between the year-over-year growth rates of sales (or shipments) and inventories. The index explains business cycle fluctuations such as expansions and contractions, trending up in expansions and declining in contractions. Figure 1 shows both historical Micron sales (blue dotted line) and the quarterly Memory Inventory Cycle Index (black solid line). To minimize seasonal fluctuations, both were calculated based on a four-quarter moving average of sales and inventories. Figure 1. Memory Inventory Cycle Index Compared to Memory Sales* Remarks1) Memory Inventory Cycle Index = YoY growth rate of memory sales revenues - YoY growth rate of memory total inventoris value on a four quarters moving average.2) Calculated memory sales and inventoris are based on Samsung, SK Hynix, and Micron public announcements.3) South Korea Won were converted to US$ based on the quaterly average value released by FRED.4) Companies’ sales data were calculated based on 4-quarter moving average.5) Company data complied by SEMI. As shown in Figure 1, the Memory Inventory Cycle Index has been declining since peaking in the fourth quarter of 2017, mirroring the previous two contractions – in 2010 and 2014 – in which memory sales slowed or stagnated after four quarters of the index decline. Accordingly, if this relationship holds between the Memory Inventory Cycle Index and sales, Micron’s sales will slow in the coming quarters and is consistent with Micron’s guidance for the current quarter. Moreover, the index suggests that the sum of three companies’ sales (the solid red line) will exhibit a similar trend of decreased growth in the coming quarters, which will impact the annual growth rate of global memory sales.WSTS recently increased its 2018 forecast for memory sales to 30.5%, up from 26.5% projected in June of this year. However, the 3-month moving average of memory sales shows that memory sales already increased by 48% YoY in the first half of the year, which means growth is expected to be lower in the second half of the year. Other signs pointing to a weaker end to the year include front-end equipment investments by the top three memory suppliers. SEMI is modeling an annual increase of only one percent for the year for these suppliers, with spending down 23% in the second half relative to the first half of the year.Figure 2 shows the historical trend of the Memory Inventory Cycle Index, the YoY growth rate of memory sales, and YoY memory fab equipment investments. The Memory Inventory Cycle Index increased faster than memory sales and fab equipment investments in the past two cycles. In the most recent memory cycle, these three indexes are moving in tandem, each peaking in the fourth quarter of 2017. Figure 2. Memory Inventory Cycle Index, Memory Sales and Memory Fab Equipment Investments* Remarks1) Both sales and memory fab equipment investments data were calculated based on 4-quarter moving average to minimize seasonal fluctuation.2) All data are from SEMI, except memory sales (WSTS) While overall memory sales continue to be strong this year, memory ASPs have shown signs of weakening right after the inventory index peak. NAND flash ASPs have been trending downward since the first quarter of 2018. With the recent inventory correction and short-term CPU shortage, DRAM ASPs are expected to soften in the fourth quarter of 2018. The looming memory market slowdown has memory makers adjusting their capacity expansion plans for the rest of this year. Some new capacity additions, especially for DRAM, have been pushed out to 2019. The memory inventory cycle index has to some extent foretold the slowdown of the memory market. In the second and final part of this article, we will discuss the correlation between the Memory Inventory Cycle Index and China’s semiconductor sales and Purchasing Managers Index. We will also look at the increasing level of memory inventory in the past few quarters and its composition including Work-in-Progress and Finished goods. Clark Tseng is director and Sungho Yoon is senior market research analyst in Industry Research and Statistics at SEMI. SEMI World Fab ForecastFor the latest worldwide memory fabs forecast including company details, please see the SEMI World Fab Forecast. The report includes quarter-to-quarter fab data from planning to production for both DRAM and NAND Flash companies.

On June 1st, 2018, Toshiba sold Toshiba Memory, Toshiba’s memory business, to an investment group led by Bain Capital. Toshiba Memory was then owned by a consortium of American, Japanese and Korean companies.After the long and tough negotiations, Toshiba Memory moved forward at full throttle, holding a groundbreaking ceremony for its new 3D NAND fab (100,000 WPM) in Kitakami in July and, in September, celebrating the opening of Fab 6 Phase 1 (50,000 WPM). To be sure, NAND memory is a key feature of Japan’s semiconductor industry. But the sector’s reach extends well beyond memory with its rich and versatile product portfolio nourished by active investment.Born in the early 1950s, Japan’s semiconductor industry today boasts more than 30 companies with fabs. Many feature 200mm and smaller wafer lines with legacy technologies, form factors that account for the bulk of the world’s semiconductors and are the oxygen of Japan’s chip industry. Clearly, the world is not built only with the state-of-art 7nm processed chips on the latest generation 300mm lines. Japanese chipmakers are flourishing.Automotive SemiconductorsRenesas Electronics remains a giant in microcontrollers (MCU) and system on chip (SoC) devices for automotive applications. According to IHS Markit, Renesas automotive semiconductor revenue in 2017 reached $3.6 billion while Inineon Technologies and NXP Semiconductors revenues were $3.4 billion and $3.7 billion, respectively. The three companies dominate the global automotive MCU global market. The company recently acquired Integrated Device Technology (IDT), a U.S. fabless company specializing in analog/mixed signal chips, to strengthen its automotive semiconductor portfolio. Renesas operates four volume production fabs, according to the latest World Fab Forecast from SEMI. Renesas’s microcontrollers for automotive applications (Source: Renesas Electronics) Power SemiconductorsWith power semiconductors the chips of choice for boosting the efficiency and performance of motors and batteries used in equipment, demand for the devices is rapidly growing, especially for automotive applications. Power semiconductor companies in Japan are legion and include Denso, Fuji Electric, Fujitsu Semiconductor, Hitachi, Kyocera, Mitsubishi Electric, New Japan Radio, Origin Electric, Phenitec Semiconductor, Renesas, Rohm, Sanken Electric, Sansha Electric Manufacturing, Seiko NPC, Shindengen Electric Manufacturing, Sumitomo Electric Device Innovations, Toshiba and Toyota Industries. The companies account for 26% of global power semiconductor capacity and will spend $317 million for construction and equipping in 2018.CMOS SensorsSony dominates the CMOS image sensors market with 42% share in 2016, according to Yole Développment. To meet growing demand for high-end CMOS image sensors, Sony has acquired several legacy 300mm wafer fabs and retooled them for CMOS sensor manufacturing. What’s more, Sony’s May announcement of its mid-term corporate strategy includes a 1 trillion Japanese yen investment in CMOS image sensors targeted to automotive applications by March 2021.Sony’s 7.42 effective megapixel stacked CMOS image sensor for automotive cameras (Source: Sony Corporation) MEMSMEMS is perhaps the most wide-ranging device market: Every application requires different capabilities and functions. The latest World Fab Forecast report lists 17 MEMS companies in Japan, though three makers of fast-growing RF MEMS, typically known as surface acoustic wave (SAW) or bulk acoustic wave (BAW) filters, are coming to the attention of semiconductor manufacturers. All are familiar passive electronic components suppliers – Murata Manufacturing, Taiyo Yuden and TDK – and all acquired legacy semiconductor fabs to manufacture RF MEMS.Their high-performance radio wave filters make mobile phones usable around the world. Research companies like Yole expect the introduction of 5G cellular mobile communication systems to fuel another wave of growth of the RF MEMS market. Murata Manufacturing’s SAW filters for smart phones (source Murata Manufacturing) Japanese Supply Chain Meets All Different NeedsJapan’s semiconductor supply chain provides one third of the world’s semiconductor manufacturing equipment and more than half of the industry’s materials. But Japanese suppliers also work with small and midsize makers of highly versatile chips critical to enabling the explosion of smart applications.Meet these versatile Japanese suppliers at SEMICON Japan to find solutions to your unique needs and help the world get smarter. Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI (artificial intelligence), Internet of Things (IoT) and Smart technologies. Featuring more than 750 exhibitors from around the world, the event is the gathering place to connect the people, technologies and business across the electronics manufacturing supply chain, from semiconductor manufacturing to autonomous cars, robotics and other smart applications. For more information about SEMICON Japan, visit www.semiconjapan.org.Yoichiro Ando is a marketing director at SEMI Japan.

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.

Last week, SEMI joined a coalition of business groups in calling for Ambassador Robert Lighthizer, U.S. Trade Representative, to enact an exclusion process for the most recent tranche of tariffs on $200 billion in goods imported from China. While an exclusion process was provided for in the previous tariff lists, which cover about $50 billion in goods, the administration has said that no similar process will be provided on the most recent tariffs on $200 billion (List 3), which took effect Monday. SEMI members will face millions of dollars in additional duties as a result of these tariffs. This action will also curb growth, stifle innovation, and introduce significant uncertainty in the semiconductor industry. Americans for Free Trade is a diverse coalition, which includes hundreds of companies across the United States, to illustrate the impacts of tariffs on American businesses, consumers and manufacturers. SEMI is a member of this coalition. The full text of the letter can be found here. Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Process power and reactive gas subsystems for semiconductor manufacturing equipment have grown at a CAGR of 21% since 2013. The segment growth is considerably above the critical subsystems industry average of 9.5% and is attributable to higher demand for vacuum processing equipment over the period.Process power and reactive gas subsystems now account for approximately 12% of all expenditures on critical subsystems used on semiconductor manufacturing equipment, up from 7% in 2013. The main driver of this exceptional growth has been the rise in vacuum processing steps (deposition and etch) during the manufacturing processes of both logic and memory devices. Most deposition and etch processes require an RF generator to provide a plasma energy source in the chamber, increasing demand for tools with power subsystems such as RF power supplies and matching networks.Multiple patterning and the advent of 3D NAND in high-volume manufacturing have significantly increased the number of deposition and etch processing steps and, in the case of 3D NAND, longer and more difficult etch processes are requiring a wider range of power solutions. Further analysis shows that 3D NAND has been the principle growth catalyst, with the total share of power subsystems going to memory applications increasing 8 percentage points since 2013. Memory applications now account for almost half of all power subsystems demand in 2018. Interestingly, investigation of power subsystems by tool type reveals that a clear majority of power subsystems (60%) find their way on to etch tools with only 40% on deposition tools. This can be explained by the fact that more delicate etch processes can require multiple RF power solutions per tool, whereas deposition does always use plasma energy sources, for example in thermal deposition processes.Despite the staggering growth performance of the power subsystems segment over the past five years, we expect the growth rate to moderate significantly in the run-up to 2023. Now that 3D NAND has been adopted in high-volume manufacturing, we expect the rate of increase in vacuum/plasma processing steps to slow down. The introduction of EUV also has the potential to taper demand for vacuum processing equipment. However, it is not expected the reverse the trend as multiple patterning techniques will still be needed in conjunction with EUV to achieve the desired improvements in device density and performance. The future growth trend for power and reactive gas subsystems is forecast to be in line with the critical subsystems industry average at approximately 2.0% CAGR until 2023.For more information about Critical Subsystems and VLSI Research, please visit www.vlsiresearch.com/public/csubsJulian West is a technical and market analyst at VLSI Research Europe.

Korea is on track to top all other regions in fab investment, spending $63 billion between 2017 and 2020, with powerhouses Samsung Electronics Co. and SK Hynix leading the way, according to latest World Fab Forecast Report by SEMI. Samsung Electronics increased fab investments $770 million to $12 billion this year, and SK Hynix upped its spending a significant $2.8 billion to $7.25 billion in 2018.Korea's investment companies anticipate continued growth for both companies in the second half of 2018.Under this halo of extraordinary investment, nearly 380 SEMI Korea members and industry analysts gathered for 2018 SEMI Korea Members Day on September 13 to share insights on semiconductor market trends and new technologies that could help members bolster their competitiveness. Following are key takeaways from the event. Korea semiconductor market to grow 16% in 2018That’s according to IDC Korea VP Kim Soo-kyung, who noted that data center, memory and Internet of Things (IoT) are becoming key growth drivers for the semiconductor industry. He encouraged semiconductor companies to closely track development of automotive technology and the industry semiconductor market, both key growth areas. SEMI Korea president H.D. Cho opens SEMI Korea Members Day 2018 Continuing fab investment will lead to oversupply, but display will shineMarket entry by Chinese companies will also spur the oversupply, said Jeong Won-Seok, an analyst at HI Investment Corp. He noted that the oversupply will force Korea into stiffer competition with other regions. However, with OLED used for a wide variety of devices and the display industry seeing rapid growth, the sector will remain ripe for growth among Korean companies.Interconnecting various applications is a big semiconductor industry trendThe need for these interconnections will stand out in the mobility and high-performance computing (HPC) markets, said Park Sung-Soon, principal research fellow at Amkor Technology Korea, who addressed trends in packaging technology. He also emphasized interconnection cost efficiency as key to maximizing competitiveness.Smart Manufacturing is driving mass customizationAs semiconductor industry growth continues, production methods are shifting from ‘mass production’ to ‘mass customization,’ increasing the importance of Smart Manufacturing in driving greater production efficiency, noted BISTel VP Jeon Kyeong-Sik. Building a Smart Manufacturing platform to support large-scale production of specialized database and artificial intelligence (AI) chips will boost production efficiency, reduce costs and improve risk management. Virtual simulation will be a key enabling technology. SEMI analyst Clark Tseng presenting at SEMI Korea Members Day 2018 Surge in data volume and technology advances to drive long-term semiconductor industry growthThese key industry drivers will continue to power fab investment growth, with spending focused on 3D NAND, DRAM, and foundry, said Clark Tseng, director of Industry Research and Statistics at SEMI. China alone will see eye-watering growth with the region’s investments in domestic companies surging 46% from 2018 to 2019 and fab investment by Chinese domestic companies outpacing spending by foreign companies in China, Tseng predicted. SEMI membership rises with industry growthCulminating the event, SEMI Korea president H.D. Cho said, "With the growth of the semiconductor market, the number of SEMI members is gradually increasing, and we will help member companies grow with various activities such as Korea Members Day.”Jaegwan Shim is a marketing specialist at SEMI Korea.