In 2016, the then-Secretary-General of the United Nations, Ban-Ki Moon, stated “Saving our planet, lifting people out of poverty, advancing economic growth. These are one and the same fight. We must connect the dots between climate change, water scarcity, energy shortages, global health, food security and women’s empowerment.” The SEMI Talent Forum, 2-3 May, 2019 in Bristol, UK will explore new opportunities and challenges of the digital era and the industry’s need for talent and the knowledge and skills in automation, computerization and digitization to drive tech innovation. Serena Brischetto of SEMI spoke with professor Michael Czerniak, Environmental Solutions Business Development Manager at Edwards, about how digitalization impacts all these key areas and will be instrumental in helping humanity shape the future. SEMI: The preservation of the global environment and the talent shortage are probably two of the most critical challenges confronting the semiconductor industry. What is the Edwards position on these issues? Czerniak: When I started in the industry, climate change was a new concept and scientific investigation was in its infancy. Now it is a well-understood phenomenon and its impacts will only be minimised by the implementation of better technologies, nearly all of which depend on digital technology and a talented workforce to drive new innovation. This is mission-critical not only to Edwards, but also to the digital industry, and indeed our common future.SEMI: Edwards celebrates 100 years of empowering innovative people. How do you help electronics shape the future and advance life standards? What is your secret recipe?Czerniak: Edwards plays a key role in enabling semiconductor manufacturers by making the electronic circuits, also commonly known as chips, on which the Digital Age is built. Our secret recipe is: nothing! We literally have no molecules at all, i.e. vacuum, which enables the intricate processes like plasma chemistry taking place. Those are the processes used to sequentially deposit and remove the thin films that constitute a modern semiconductor device. We also remove harmful and global-warming gas exhausts from these processes to minimise the environmental impact of this amazing industry.SEMI: What is stimulating about semiconductors and could you give us an example of how Edwards is helping remove harmful and global-warming gases?Czerniak: I work in environmental science both at Edwards and also here in Bristol in the School of Chemistry. My least-favorite gas is called CF4. Not only is it thousands of times more impactful as a global warming gas, but also it has an atmospheric lifetime of 50,000 years. Using abatement technology pioneered by Edwards, emissions of this gas into the atmosphere produced by this industry, have been reduced by up to 95%. That’s certainly something to make you feel good about after a day at work!SEMI: Edwards was honored with the SEMI Diversity and Inclusion award and also for the company's 100th anniversary at the Industry Strategy Symposium (ISS) Europe in Milan in early April. What is particularly exciting about Edwards?Czerniak: Edwards is and always has been a very inclusive place to work, not least because it is a global company, reflecting the scope and geographical reach of the semiconductor industry as a whole. This provides a great variety of career paths locally at one of our many global manufacturing sites, or on a global scale, as we need to be where our customers are.SEMI: What are your expectations regarding the forum in Bristol, and for the future ahead? What is the status of the semiconductor workforce development scenario in your opinion? What can we do more?Czerniak: My main hope for the Talent Forum in Bristol is that the profile of the semiconductor industry will be raised amongst students considering their future career options to the point where they seriously consider applying for positions in this field. This applies to students from all disciplines as they are all needed to help develop the Digital Age, and more events like this can only help spread the message about the exciting opportunities and challenges available.Michael Czerniak started his professional career in the semiconductor industry with Philips, initially in the company’s UK R+D labs and subsequently in the fab in Nijmegen, Holland. He then held marketing roles at UK-based OEMs Cambridge Instruments, VSW and VG Semicon before joining Edwards 21 years ago. Michael has authored numerous published articles and patents, co-chairs a SEMI standards committee, participates in the IRDS, is a UK PFC expert on IPCC and has authored chapters on Vacuum and Environmental issues in the Semiconductor Manufacturing Handbook. Michael became a Professor in the School of Chemistry at the University of Bristol in September 2018. Serena Brischetto is a marketing and communications manager at SEMI Europe.

Two of the big, recent breakthroughs in memory technology – eMRAM and ePCM – have gotten their start in volume manufacturing on 28nm FD-SOI. In conjunction with the 2019 IEEE International Memory Workshop, SOI Consortium members Leti and Applied Materials have teamed up to give a technical program to explore short-term and long-term memory solutions. While the workshop is not specific to SOI, given the recent foundry announcements about ePCM and eMRAM for FD-SOI, the organizers predict it will be of particular interest to those following the greater SOI ecosystem. The event takes place at the end of the Sunday IMW tutorial day, starting at 5:30pm at the Hyatt Regency in Monterey, CA. Please see this page for the program and registration information. Here is the program: Emerging Non-Volatile Memory Promises Toward New Energy-Efficient Design and Applications - Michael Tchagaspanian, VP Business Development, CEA-Leti Technologies That Enable MRAM and PCRAM in Volume Manufacturing - Kevin Moraes, Vice President, Metal Deposition Products, Applied Materials Technology Improvements Directions of Emerging Non-Volatile Memory for New Applications Solutions - Etienne Nowak, Head of Memory Laboratory, CEA-Leti Integration Schemes and Challenges for New Memories in a New Artificial Intelligence Era -Michel Frei, Director, Advanced Product Technology Development, Applied Materials Jean-Eric Michallet, Head of Leti’s Microelectronics Components Department, Silicon Component Division is one of the organizers. Here is his overview: FD-SOI is expected to be a long-lived technology. It enables planar CMOS scaling and accommodates a great deal of More-than-Moore developments where its ability for low power and great analog performance can make a difference for IoT, Automotive, Machine Learning or 5G applications. But to do this it requires a high-performance and cost-effective non-volatile embedded memory option. The incumbent Flash cell is reaching the end of its roadmap due to the difficulty of shrinking the bitcell and manufacturing, as well as the finished wafer cost increase. Back-end integrated Random Access Memory in advanced CMOS process has been explored for many years now as a competitive solution for fast-write and low-voltage non-volatile embedded memories. Foundry availability of embedded Magnetic RAM and Phase Change RAM for FDSOI 28nm platforms has been announced recently, showing that these technologies have now reached industrial maturity. CEA-Leti and Applied Materials invite you to attend a technical program to explore short-term and long-term memory solutions, from early research to industrialization. Registration is open, free, and available to all IMW attendees, and others. However, as seating is limited and as we have already several participants pre-registered, registration is by invitation only and early registration is recommended. If you are interested, please email Jean-Eric Michallet. The event is presented in conjunction with the 2019 IEEE International Memory Workshop, to be held on Sunday, May 12th, 2019, Hyatt Regency, Monterey CA, starting at 5:30 pm.

Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot. Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available - click here to get them.The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.NXP: In the Sweet SpotNXP VP Ron Martino presenting at the 2019 SOI Symposium in San Jose.NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D 3D graphics they need for wearables and portables in consumer and industrial applications.NXP slide 10, SOI Symposium, San Jose '19 (Courtesy: NXP)Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.As shown at Embedded World '19, automotive app for NXP'x i.MX 8, which is on 28nm FD-SOI. (Courtesy: NXP)Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard...it’s amazing.”BTW, in another presentation, CoreAVI, which builds avionics, automotive and industrial products on NXP’s i.MX 8, addressed safety. You can get that here.FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).Samsung: Enabling LP Endpoint ProductsTim Dry, Samsung Foundry Director of Edge Endpoint, SOI Symposium, San Jose '19Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it's 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.Samsung Foundry FD-SOI IP slide, SOI Symposium, San Jose '19 (Source: Samsung Foundry Keynote at SOI Symposium 2019, USA)Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).ARM’s Biased ViewsKelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers. Slide 9 from Arm's presentation, Silicon Valley SOI Symposium 2019.At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML. There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.Slides 6 and 11 from Arm's presentation, Silicon Valley SOI Symposium 2019. The goal of POP IP is to enable partners to implement and tapeout Arm cores with the fastest turn-around time and best-in-class PPA while maximizing the benefits of process technology.Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!That's all for this post. The next post -- part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave -- is now available. Click here to read on.

New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require.Yet MEMS design also presents some specialized challenges, such as a strong coupling between fabrication technology and design. Complex physical structures that exhibit non-linear behavior, custom packaging requirements, and a final product that requires integration with surrounding CMOS circuitry are just a few examples. What’s more, there is a lack of standardized processes and process validation in MEMS design ecosystems. Pressure Sensor (Courtesy: X-FAB) As with other products based on MEMS technology, designers must increasingly customize pressure sensors for higher performance – sensitivity and linearity, in this case – while decreasing their package size. Designers can accomplish the task by studying sensor performance and manufacturability using computer models prior to fabrication. This can ensure that the sensor meets its required specifications while simultaneously reducing manufacturing cycles and cost.The Power of CollaborationThis is where strong collaboration among EDA providers, MEMS technologists and designers delivers tangible benefits. EDA providers and MEMS foundries can collectively help MEMS designers to incorporate foundry process constraints into their designs.In the semiconductor industry, first-pass successful silicon relies on standardized manufacturing processes, thorough technology characterization, accurate model generation, established simulation and verification, and extensive reuse of proven design blocks. In the MEMS world, where processes and products are developed concurrently, and processes change with every product, is it possible to adopt standardized processes, design methodologies, and tools that enable efficient reuse of existing technology and design knowledge? The challenge lies in maintaining the flexibility to optimize products for a diverse array of requirements. The ideal design platform should ease sharing of technology and design data between the foundry and its customers, enabling two-way collaborative development and allowing foundry technologists to easily perform a feasibility assessment of a customer’s project. This approach offers important benefits, allowing designers to explore and evaluate the suitability of a foundry’s process technology in their unique application. It also supports accurate prediction of device performance prior to fabrication and reduces costly build-and-test cycles. Combining standardized manufacturing processes, MEMS process design kits (PDKs), and a proven design flow are the starting point for development of manufacturing-ready designs.A Real-Life Example using Pressure SensorsAn EDA company, Coventor (a Lam Research company), along with MEMS foundry partner X-FAB, collaborated to develop a PDK that would ensure that manufacturing constraints are automatically considered early in their design process. The design flow is based upon an X-FAB fabrication platform that supports multiple process options for the manufacturing of absolute and relative MEMS pressure sensors. The PDK is a “golden container” for all the process and material characteristics of the silicon membrane and substrate, glass, passivation layers, and piezoresistive components. It enforces material properties and guarantees their correct implementation during the simulation. It also includes a component library containing ready-to-use, 3D parameterized devices (such as membranes and resistors), all pre-designed with foundry-supported materials to support their respective design rules. The components are readily partitioned for optimized meshing and simulation, saving design and simulation time. Figure 1: The elements and design flow of the PDK designed by Coventor and X-FAB. (Courtesy: Coventor)Designers can use components from the library to create a custom design — which might include different membrane shapes and sizes, and resistors of varying shape, size and position — to simulate the impact of different technology variants (such as resistor doping profiles, membrane and substrate thickness, glass material properties, and passivation schemes). This allows them to anticipate the effect of these design changes on sensor sensitivity for varying pressure and temperature regimes.Extensive validation of the pressure sensor design platform is currently underway. So far, the simulations have exhibited very good correlation to actual device measurements across a range of pressure and temperature conditions, including predictions of non-linear behavior for various pressure sensor designs. At the same time, the simulation accounts for mechanical membrane properties and piezoresistivity. With this type of design platform, a foundry can provide guidelines to help customers select both the fab technology and design features that lead to an optimal design solution. Figure 2: Simulation results depicting mechanical displacement in a pressure sensor design (Courtesy: X-FAB) Let’s Face the Next Challenges…A complete design platform for MEMS must eventually include not only MEMS device design, but system integration functions, such as the application-specific integrated circuit (ASIC) design and packaging/assembly of the product. In addition to the design verification that the PDK provides, additional partnerships among foundries, integrated device manufacturers (IDMs), research centers, equipment suppliers, and EDA vendors will help to define requirements and solutions that address every level of design and production. These might include tasks such as describing standardized material properties and process specifications, creating accurate foundry-proven design models, and defining requirements for system-level simulation. In the future, PDK simulations might even include up to tape-out and physical verification. To learn more about this collaborative PDK development work, please click here for the whitepaper.Christine Dufour, MEMS PDK Program Manager, CoventorChristine Dufour is the MEMS PDK program manager at Coventor. She has more than 20 years of experience in the semiconductor industry, leading process design kit development for BiCMOS and CMOS processes at several major semiconductor companies. Ms. Dufour has also worked as a product manager in the RF design environment area. In addition to her extensive experience in MEMS PDK development, she is an expert in all aspects of MEMS design flow and design tool development. Ms. Dufour received an engineering degree at Technological University of Compiegne.For more information on Coventor, a Lam Research Company, visit: https://www.coventor.com/ Viraja Sharma, Development Engineer, MEMS Simulation Design, X-FABViraja Sharma is a development engineer for MEMS Simulation Design at X-FAB. Her work involves the design and simulation of MEMS inertial and pressure sensors. Prior to her tenure at X-FAB, Ms. Sharma performed similar duties for other semiconductor companies. She received her Master of Science degree in Micro and Nano Systems from TU Chemnitz, where she studied MEMS and micro technologies.For more information on X-FAB, visit: https://www.xfab.comCoventor and X-FAB are members of SEMI-MEMS Sensors Industry Group that connects the MEMS and sensors supply network, enabling members to address common industry challenges and explore new markets. 1 Market research firm Yole Développement predicts that MEMS pressure sensors alone will become a $2 billion market by 2023. See: https://yole-i-micronews-com.osu.eu-west 2.outscale.com/uploads/2019/01/YD18018_MEMS_Pressure_Sensor_Market_Yole_Developpement_2018_Sample.pdf

When will the memory market likely show signs of bottoming out? Following is an analysis of the current memory climate using the Memory Inventory Cycle Index introduced in this SEMI two-part article series in October 2018.

The turnaround is not “around the corner” but at least we can follow its progress!

How are flexible electronics impacting the automotive sector? How will medical diagnostics and life sciences be changing with the advent of flexible, conformable electronics? How does space exploration intersect with the continued development of flexible sensors and Internet of Things (IoT) systems? The upcoming 2019FLEX Japan / MEMS SENSORS FORUM in Shinagawa, Tokyo, May 22-23, 2019, will explore these questions and more. The event, the third FLEX Japan, is expected to gather 300 designers, technologists, researchers, analyst and product developers to hear presentations, discuss their approaches, and create connections. The transformation of the automotive industry will receive special attention with speakers from Yole Développement and a deep exploration of the new sensor form factors and capabilities. Professor Shoji Kawahito of Shizuoka University will discuss the impact of image sensors on automotive LIDAR, night vision and monitors for the driver and passengers. Dr. Yoshifumi Sakamoto of IBM Japan will share his views on key trends in smart transportation and what they mean for the supply chain. Beck Oh, president and CEO of PNI Sensor, will share how parking sensors are transforming our driving – and parking – experience. Hideo Fukunaga, project manager for Velodyne LiDAR, will discuss his work using LIDAR, often seen as the most promising and the most difficult and expensive component of autonomous driving. Jerome Joimel, CTO of ISORG, will discuss integration of organic image sensor behind display.Medical and home electronics devices are moving out of their boxes and hospitals, and flexible electronics, new sensor designs and new power options are playing a major role in that transformation. Jenax, Kobe University, Toyo University, Osaka University, and Daiwa House are just some of the presenters in this area. Researchers are steadily overcoming key technology hurdles, such as electronic interconnects between soft and rigid surfaces, and energy harvesting techniques for no-power devices, as well as ultra-thin RF components, and advanced microfluidic systems. Space, the final frontier, will be the backdrop for the general keynote talk of Mayya Mayyappan, chief scientist for exploration technology at NASA’s Ames Research Center. His team is investigating new printed and flexible sensors and electronics that can be printed in zero-gravity and how these devices will enable IoT.The only event in Japan focused on flexible and printed electronics, with special focus on the complementary areas of sensors and MEMS, 2019FLEX Japan / MEMS SENSORS FORUM provides an excellent opportunity to meet with industry players considering integration and application of new form factor electronics. More than 20 exhibitors will showcase the building blocks for conceptualizing and designing new products immediately.Register now!

April 9, 2019Une interview de Carlos Mazure, CTO de SOITEC et Président du SOI Industry ConsortiumUne interview de Jean-Éric Michallet, responsable du département micro-électronique du LETI

Creating a custom Internet of Things (IoT) IC is challenging because it involves multiple design domains (digital, analog and RF). Creating a sensor-based IC that combines electronics that use the traditional CMOS IC design flow with a MEMS sensor on the same silicon die, however, can seem impossible. Couple the co-design and verification challenges with a lack of traditional process design kit (PDK) support for MEMS, and you have a tough road to travel to get your IoT designs to market.What can we do to make the sensor-based IoT design community successful?Understanding the ChallengesThe sensor-based IoT IC typically features a MEMS sensor (and optional actuator) that interact with the real world. Analog and digital circuitry processes the signals and sends them to a CPU. The CPU provides the “smarts” to process the data from the sensor and then sends processed data via a radio to the Internet; alternatively, the CPU could activate the actuator. A typical sensor-based IoT IC (Source: Mentor: A Siemens Business) Based on the complexity of the system, designers face many co-design challenges: Analog design requirements imposed by MEMS: MEMS devices often require high voltages and multiple power supplies; they emit small signals that need amplification and conditioning; and they are sensitive to the environment and require calibration. Design flow interactions: Parasitics from MEMS devices might affect circuits and vice versa. Circuit designers need MEMS models for impedance and timing. Integration: MEMS devices operate at different timescales than circuits, which adds a layer of complexity. Compounding the problem is a lack of MEMS PDKs and methods to tie together ICs and MEMS PDKs for integration and cross-verification. After conquering the co-design challenges, the design team has to address mixed-domain simulation challenges that include: Simulating the system: This requires verification of MEMS, digital, analog and RF circuitry with embedded software that runs on the CPU. Timescales: These vary widely, from a single deflection of the MEMS transducer in femtoseconds to a seconds-long simulation of the embedded software performing a measurement and transmitting data. Simulation time: Simulation of a behavioral digital design is extremely fast. However, the system simulation requires stand-in models that incorporate the behavior of the analog and MEMS block to simulate in an acceptable amount of time. The challenge of timescales for co-simulation. (Source: Mentor: A Siemens Business) MEMS is the KeyThe reality is that it’s the MEMS device that adds extra complexity to the sensor-based IC design and verification flow. To amplify the problem, the MEMS manufacturing process is not nearly as mature as the standardized IC process. For example, the standardized IC process includes ready-made PDKs that include everything designers need to move through design and verification flows. Foundries often provide soft and hard IP to quickly build-out design, and EDA tools provide high levels of automation enabled by abstraction and a standardized IC flow. How will MEMS-based design evolve?MEMS-based design must catch up to the standardized IC process. The first step is providing MEMS PDKs that include: Multi-physics domain design rules and material properties Packaging information Wafer and bonding information Fabrication information We must also tackle issues associated with these PDKs, including: Ownership, distribution and maintenance of the PDKs Consensus on the contents of the PDKs Merging of CMOS and MEMS PDKs The industry needs to move toward standardized MEMS manufacturing processes with available PDKs. Companies must provide IP and recommend structured design methods for co-design and verification of ICs that incorporate MEMS. How can EDA help with these flows?The EDA ContributionEDA companies must work with teams in the MEMS IC co-design space, collaborating with MEMS fabricators to help enable PDKs. By incorporating PDK support within their own tools, EDA companies can provide an integrated custom IC flow that allows teams to design and verify MEMS-based ICs. For details about this flow, click here to download the Mentor whitepaper: Fusing CMOS IC and MEMS Design for IoT Edge Devices.Greg Lebsack brings 25 years of executive and technical management experience — along with a proven track record of building strong teams and delivering predictable results — to his role as general manager of the ICDS division of Mentor, a Siemens Business. Lebsack joined Mentor in 2015 after that company acquired Tanner EDA, where he was president. Prior to Tanner EDA, he held management and technical positions in a number of different industries and companies, including Sprint, General Electric and McKinsey Co. Greg holds a bachelor’s degree in business administration from Northern Arizona University.Greg Lebsack recently presented on the topic of Integrated Co-design of MEMS/IC at the MEMS Sensors Technical congress, a technical conference organized by the MEMS Sensors Industry Group.

Driven by the increased complexity of leading edge fabs and the growing vacuum intensity of semiconductor manufacturing, both the volume and the value of critical subsystems for this part of the market is on the rise.