Technology and Trends

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.Based on this work, the SCIS Seals Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).The second document published by the Seals Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)The Seals Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1. Figure 1: Elastomer seal test jig developed by the SCIS Seals Valves Group.The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.Figure 2 illustrates how the jig is connected to the gas sources. Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line. The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.Developing just a test jig is not sufficient. The Seals Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.At this point, the Seals Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.Currently, the SCIS Seals Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

I really don’t know clouds at all. – Joni MitchellThe semiconductor industry is finally on the cusp of joining the cloud revolution. The cloud has offered the promise of greatly expanded resources for years, but adoption has been slow due to lingering concerns. The biggest contributing factor for the concern over moving from on-premise EDA servers to cloud-based servers is, surprisingly, the rise of third-party IP. In the old days, if you were developing 100 percent of your own IP, and if you put that IP on a public cloud, and it somehow leaked out, well shame on you. That would certainly be bad for business. It might hurt your reputation a bit. But these days, with so much third-party IP being embedded into chips, if that third-party IP leaks out, that’s a lawsuit-fest in the making.Consequently, semiconductor companies now have even more incentive to protect IP with advanced security. Surprisingly, cloud-based security is far, far better than on-premise security. Why? Because keeping customers’ data secure is the central mission of cloud service suppliers, so they’ve developed a rich set of security tools to protect the data that’s entrusted to them by their clients. In many ways, you can maintain much better security in the cloud than you can with on-premise tools. Image credit: Markus Spiske temporausch.com from Pexels Amazon Web Services: Exemplifying the benefits of cloud computingTake Amazon Web Services (AWS) as an example. (Note: AWS is not the only vendor in the cloud space, but it’s one I’m very familiar with.)AWS has developed the concept of security groups – firewalls that you throw up around any network interface to allow only specific traffic into that secured network. You can do that for just one server or for a fleet of servers, in just seconds. Most on-premise server networks won’t let you work that quickly, or as easily, or with such fine control because most such networks lack the security tools to do this.In addition, AWS allows you to encrypt every bit of data stored on and flowing through its cloud-based storage systems. You can encrypt data at rest in on-premise storage but it’s a lot harder to encrypt data flying through the on-premise network. Amazon’s Elastic File System (EFS), a managed NFS file service, offers the ability to easily encrypt NFS traffic on the wire, a difficult feat at best with an on-premise solution.AWS built-in encryption key-management service can rotate encryption keys automatically. The cloud also allows you to have key policies that are easy to implement and maintain.Internal corporate networks rely heavily on perimeter firewalls for security. Perimeter defense just cannot deliver sufficient security against determined hackers and everyone realizes this. We’ve built big, open, on-premise networks that are just not well-suited to implementing adequate security protocols. Trying to retrofit these network architectures with additional security is time-consuming and costly, and it hurts engineering productivity. Moving to the cloud gives you a greenfield opportunity to right some of the wrongs of the past.Continuing with AWS as an example, here are some additional advantages of EDA in the cloud: AWS provides physical security that’s far above and beyond on-premise security. It doesn’t publish the physical locations of its data centers. It also has professional security staff 24/7, keycard access, and additional security features that far exceed typical on-premise physical security. AWS automatically manages security patches and access controls for their managed services such as database services. AWS gives you plenty of security tools to automate security processes, audits, and so forth to protect your data. AWS gives you so much flexibility that you can get yourself in trouble in you are not careful. If you want, you can create the same sorts of security holes that already exist with on-premise networks. You shouldn’t of course, but you can if you’re not thoughtful about things. You just need to hire the right people to implement and maintain your cloud security.Here are five very big differences between AWS (cloud-based) and on-premise server networking: Elasticity: Cloud-based systems enable you to scale up in minutes. That ability has pluses and minuses depending on how disciplined you are. On the plus side, you can quickly grow your EDA infrastructure as big as you want and then shrink it back down when you no longer need the additional capacity. All you need to do is tell the cloud service that you need more capacity and it will bring that extra capacity online for you in minutes – and will charge you for it. (That’s the minus side.) When you’re done, you can turn off the extra capacity (and stop paying for it) with the same speed. If you want to provision more EDA capacity for your on-premise network, you’ll need to beg, borrow, or steal existing capacity from someone else on your network, or you can order more servers, get the vendor to build and ship them, install them in your server room, provision them, and bring them online. That will take months. Fault tolerance: On-premise networks rely on large, monolithic service architectures, which saddle EDA vendors with more than 30 years of technical debt. The cloud operates on a different model, one that’s based on containers and microservices. This is inherently a redundant, fault-tolerant computing model if you write your code correctly. The difference between redundancy in the cloud and in on-premise networks is night and day. There’s no comparison. No private networks can match the available and growing redundancy of cloud systems, which have redundant servers inside of a data center and redundant data centers in multiple, worldwide geographic locations, which protects your data from natural and man-made disasters. Network segmentation: Many semiconductor developers have several design centers distributed around the world and there may be IP in use on a project that cannot be shared with certain geographic locations either by law or by contract. Cloud networks are already set up with automated tools for network segmentation that can enforce geography-specific rules through VPCs (Virtual Private Clouds), which are easy to set up. VPCs allow you to set up subnets with restrictions based on routing tables so that IP management and control become highly automated. Removal of single points of failure: The typical EDA grid configuration has several built-in single points of failure. For example, a central job dispatcher generally runs on one single node. If that node dies, all EDA work halts. The same is true for EDA license servers and for configuration-management and version-control servers. Again, because cloud networks are based on the microservices concept, the cloud simply doesn’t need to have the same single-point-of-failure vulnerabilities that on-premise networks have. On-premise networksTo get these same advantages with on-premise networks, the grid architecture must fundamentally be changed, starting with the replacement of NFS. EDA systems need to replace huge, monolithic file systems specifically developed for EDA with object storage. That's a tall order – one that requires the rewriting of fundamental assumptions that serve as EDA software’s foundation.In the 1980s, 1990s, and early 2000s, small EDA startups appeared to fill gaps in the offerings of the large EDA players. If they succeeded and grew, they’d eventually be gobbled up by a larger EDA vendor. That flowering of EDA startups seems to have damped down. The market has really matured.Next wave of EDA startups to offer cloud-first toolsGoing forward, I expect the next wave of EDA startups will be offering cloud-first tools that are not burdened by three decades of technical debt. They’ll be able to architect their tools specifically for the cloud.We’re starting to see this happen. For example, Metrics, a Canadian EDA startup, offers a pay-by-the-minute, cloud-based simulator and verification manager. Although one job on one cloud server might run slower than a monolithic simulator running an on-premise server, Metrics has architected its tools so that you can throw more servers at the problem, allowing you to run all of your jobs at once. Here, multiple simulation jobs running concurrently on multiple servers will ultimately finish faster than running the jobs serially on one slightly faster on-premise simulator.That’s the kind of innovation that we’re going to see. That’s the future of EDA.Derek Magill is executive director and president at HPC Pros. Derek has 20 years of experience supporting semiconductor engineering functions. His main focus has been in system architecture and technical management, but over the years he has been involved with technologies such as EDA licensing, ClearCase, HPC architecture, IP management and engineering software support. Derek spent 15 years at Texas Instruments in various technical and managerial roles. He is currently a senior manager, IT at Qualcomm managing the Global License Infrastructure team as well as the lead technical architect for the company's engineering cloud activities. The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, is the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. As an international association of companies providing goods and services throughout the semiconductor design ecosystem, it provides a forum to address technical, marketing, economic and legislative issues affecting the entire industry. The ESD Alliance also stages events that promote networking, learning and collaboration among member companies. To learn more about the ESD Alliance and how to join the group, visit www.esd-alliance.org or contact Bob Smith at [email protected].

Going to CES? Check out the demo by Saankhya Labs. They just announced the launch of their latest next-gen digital terrestrial TV demodulator chipsets, SL3000 and SL4000. As reported by The Times of India and many other media outlets, the chipset is part of the Pruthvi-3 series, and it's being manufactured on Samsung Foundry's 28nm FD-SOI technology. Saankhya Labs says they'll be sampling in the 1st Quarter of 2019. [UPDATE 9 January 2019: Per a press release issued at CES, the chipset was launched by ONE Media 3.0, LLC, a subsidiary of Sinclair Broadcast Group, and Saankhya Labs in collaboration with VeriSilicon and Samsung Foundry. This announcement follows Sinclair Broadcast Group’s recent commitment to a nationwide roll-out of ATSC 3.0 ("Next Gen TV") service and its past announcement to fund millions of chipsets giveaways for wireless operators. Sinclair is a major TV station operator in the US. The PR goes on to say that the demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option.] [caption id="attachment_13581" align="alignright" width="300"] (Courtesy: @SaankhyaLabs)[/caption] The Pruthvi-3 is an upgrade of Saankyha's Software Defined Radio (SDR) chipsets for Direct to Mobile (DTM) applications, which address video bandwidth congestion and other challenges, including internet access for the vast populations of rural users found in India and worldwide. (DYK half the world still lacks access!?) The company says the SL300x will be the industry’s first SDR-based DTV Demodulator that supports all the leading broadcast terrestrial, cable and satellite TV standards including the ATSC 3.0. The SOC is designed to deliver high performance and high throughput in static and multipath environments. A power-efficient, small footprint device, it targets DTV receiver applications such as digital televisions, set top boxes, home theatres and automotive entertainment systems. The SL400x – for mobile phones and tablets – is designed to be the most technologically advanced and highly-integrated single chip Mobile DTV Receiver in the industry. The full featured front-end SOC integrates UHF RF tuner, baseband DTV demodulator, FEC decoder, de-interleaver memory and Analog to Digital Converter (ADC) in a single chip. Here is a brief YouTube video of the company's CEO at the launch event, explaining why they see this chipset as a game changer. India Times reports that there are already 5 million of the chipsets in pre-order to companies in the US and China.

4 Key Takeaways from SEMI Taiwan Member ForumThe rapid development of artificial intelligence (AI) has accelerated the digital transformation in various industries and has now fused with Internet of Things (IoT) to exploit the value of both technologies in reshaping the electronics industry value chain. As it emerges from the shadows of its parent technologies, AIoT is giving rise to new opportunities in manufacturing, healthcare, transportation, and even energy. AIoT is fast rising in prominence as an enabler of key electronics manufacturing process improvements and the creation of add-on value to existing products – both critical to the success of many businesses.SEMI and the SEMI MEMS Sensors Industry Group (SEMI-MSIG) held a technical forum on smart sensing and its applications in AI and AIoT, inviting renowned experts in sensors and edge computing to share in-depth insights into the latest AIoT technologies and applications with more than 100 industry professionals in research and development, marketing and sales. Here are four key takeaways from the SEMI Taiwan member forum.1. Steady Growth for Global Sensors MarketThe global sensors market’s steady growth is expected to expand at a CAGR of 6.6 percent from 2017 to 2023, with Asia driving the biggest gains and automotive leading the segments – including healthcare and education – with the strongest growth. Automotive alone is expected to reach US$34 billion in 2023.2. Integration Critical to MEMS Sensors DesignsWith AI booming, MEMS sensor designs need to drive toward greater integration —not only integrating data collection with sensors, but also streamlining data processing on the backend – making 3D models of today’s MEMS mechanical designs critical. The differences between 3D and entrenched 2D models are dramatic, elevating the importance of specifying manufacturing steps in MEMS designs. As new sensors and applications continue to emerge, companies that develop the most powerful integrated designs will win. 3. Growth of Smart Voice-Control Applications to ExplodeAIoT is also accelerating the development of smart voice-control applications and the rise of new related business opportunities. Just 50 million voice-controlled devices shipped worldwide in 2017, a number predicted to swell to 436 million in 2021 with smart home devices such as set-top boxes and smart TVs the major growth drivers.4. AIoT Eyed to Make Human-Robot Collaboration SafeSafety is an essential feature for human-robot collaboration. Tactile sensing technologies give robots a layer of “skin” with capabilities rivaling human touch. To ensure humans and robots work together safely in work environments, sensors on this layer of skin are concentrated – less than 8mm apart, equivalent to the width of a human finger, with a response time of less than 5ms on contact. More than 4 million robots worldwide are expected to be upgraded with these sensing technologies and are on track for deployment in pilot plants in the next three years.SEMI-MSIG is committed to strengthening connections across all sectors in the MEMS and sensors supply chain, working closely with the industry to accelerate the development of related technologies and applications in both mature and emerging markets. In addition, SEMI-MSIG hosts regular events to inspire business opportunities and technology exchange for innovative applications, while enhancing the visibility of members among global customers and partners to help them forge new partnerships. To join the group, contact SEMI Taiwan’s Helen Chen at [email protected] Yi is a marketing specialist at SEMI Taiwan.

Semiconductor fabs have been getting smarter and smarter over the past 30 years. It’s a natural evolution – the direct outcome of numerous continuous-improvement efforts. The really important difference on the road to smarter fabs, the one change that’s enabling the Industry 4.0 revolution, is the concept of a cyber-physical system or digital twin. If you don’t have a thorough, detailed, high-fidelity digital twin of your entire fab operation, then you cannot have “Smart Manufacturing.” That’s really the definition of a smart site. A digital twin is simply a requirement for all smart factories of the future. One caveat: No matter what you build today from a smart perspective, your digital twin’s fidelity will improve over the next 20 years. A factory’s digital twin has two facets: the operational aspect and the yield aspect. Each of these two facets places different requirements on a database including the types of data, the frequency of data generated, the retention of data, and even the AI/ML techniques used to analyze the data. A combination of these data requirements are needed to create a digital twin – the virtual representation of your entire factory operation, whether it’s on the wafer-fab front end or the assembly and test back end. What’s most important here is that facility-wide data sets and databases must be able to communicate with each other using refined summary statistics to create a practical digital twin. For example, a lot of information is collected on the yield side to feed the deep-learning models needed to manage processes. However, the factory scheduler, driven largely by the smart operational database, needs only summary statistics from the yield database to be able to act in the next moment or over the next 24 hours. Figure 1 illustrates the needs of and the interaction between a smart operational and a yield database. Figure 1: The Operational and Yield databases in a Smart Factory need to exchange summary statistics. Today, we find that although these databases generally speak to each other in smart factories, they’re still not sufficiently connected to permit the use and analysis of data needed to realize the full potential of a smart factory. That level of interconnectedness is still in the future. Some solution providers have created what is essentially a “smart learning warehouse” (“database” has become too limited a term here). This warehouse collects, analyzes and learns from the extensive amount of information that a fab generates. Game-changing, more holistic applications become possible when this information can be combined in new and informative ways. As it turns out, a data source is just a data source, but users in different factory areas need to extract different information from these common data sources. They need different applications and portals – in other words “views” – that are adapted and adjusted for each area’s needs. Aren’t we smart enough? Some people think that 300mm fabs are already smart. That’s true. They are. But, they could be a lot smarter. No 300mm fab in use today has attained the full, utopian vision of what a smart factory can deliver over the next 10 years. When you finally integrate all of the disparate databases in a fab – when you’re able to use all of those different data sources as one common data source – that’s when your Smart Factory will have the ability to self-optimize its future actions and react quickly to real-time events. The largest semiconductor manufacturers tend to develop these smart factory applications on their own. The remaining semiconductor fabs need to work together with other fabs and their solution providers to develop these smart factory applications. Why now? Why is everyone talking about “Smart” now? It’s because the semiconductor industry has helped to create all of the enabling technology: the compute power, the networking and networking standards, and even the industry’s maturation into a multi-tiered organization of solution providers. We’ve reached the point where we can collect data from a widespread sensor network along with tool-health data and we can then warehouse this data so that it can be applied to more intelligent decision-making. While there may be one or two sensors on a tool today, in the future there will be many such sensors connected over an IoT network or networks that provide mountains of data to the warehouse. All of this data will feed into the digital-twin version of the fab. One of the biggest changes on the horizon made possible by all of this accessible data is advanced scheduling. Despite all of the automation advancements made over the past 25 years, including robotic handling, it’s still hard to decide “where, what, and when?” for every single lot in the factory. Today, no factory in the world is more complex than a semiconductor fab. Optimizing a semiconductor manufacturing process is the most complex manufacturing-optimization task in the world. Do it for ROI ROI is the chief reason for having a digital twin. Once you can make a truly smart, holistic schedule of the fabs operations — not a dispatch or rule-based dispatch list — then you can create an operationally smart factory. Rule-based dispatching systems primarily focus on tools and tool-centric views. Although they incorporate knowledge from current WIP and tool conditions to make decisions better than simple dispatch systems, smart factories are not just about tools and the current WIP at them. Smart factories use the status of every tool and lot in the factory to make fab-centric optimizations instead of tool-specific optimizations. Once you have a digital twin, you’re optimizing for global functions such as line linearity and on-time delivery. These functions are not just about the moment. The transition to a smart factory thus represents a huge philosophical change. When you know exactly what’s going to happen in a factory over the next 12 hours for every single lot, every single wafer carrier, and every single entrance port of every tool in the factory, then you suddenly have control over the factory’s idle time. You know when you can optimally perform PM (preventive maintenance). You know how to best redirect material or labor resources to maximize output. You can create a smart schedule for every maintenance person in the factory that comprehends each person’s skill set and tool downtime so that there’s no negative impact on the factory’s productivity. You can only do all of this when you know the future. Figure 2 illustrates the opportunity. Imagine that a factory contains 1,500 tools. Use of these tools is scheduled for the next twelve hours. The information depicted in Figure 2 encompasses process changes from one chemistry to another, implant changes, reticle changes, and the status of every single consumable for all 1,500 tools. The white spaces that appear between processes in Figure 2 represent opportunities to intelligently schedule events such as maintenance to maximize factory productivity. Figure 2: Smart scheduling permits factory-wide optimization to maximize productivity. Once you have a schedule, you need to translate that schedule into actions or movement. It’s not easy to do this and most material-control systems today make overly simplistic decisions based on modeled assumptions and typical cases rather than the actual time each lot needs to be at a precise location, which can only come from a schedule. Once the data from all of the tools is connected, a smart scheduling system can use the digital twin to make far better process decisions. The larger the factory (or more complex the factory), the more important it is to make smarter decisions. Note: SEMI has a Smart Manufacturing Technology Community. For more information or to get involved, click here. If you would like to discuss Smart Manufacturing more with John directly, he can be contacted at [email protected]. John Behnke is general manager of the Final Phase Systems product line at INFICON.

The Single Device Traceability Task Force emerged from SEMI CAST’s identification of the need for device traceability through the supply chain — not just traceability for devices but for component parts such as semiconductor die, lead frames, epoxy, bond wires, and printed circuit boards. Eventually the work led to a draft document and preparation for SEMI’s standardization process.The Single Device Traceability Task Force’s charter is “To develop standards enabling traceable device-level identification (ID) throughout the IC manufacturing, test, and assembly processes to the point of use in the final system.” The scope of this work is to develop standard(s) focusing on key concepts, behaviors, and requirements as well as standards for enabling device ID and traceability, with considerations for various types of implementations. In addition, the Single Device Traceability Task Force is looking at anti-counterfeiting, which is closely associated with traceability.The motivation for this particular traceability standard comes from systems companies that purchase and use semiconductors in boards and systems. These companies need the ability to track devices through the supply chain for various reasons. They do not want an ad hoc situation where each system vendor develops its own requirements and specifications for device traceability. They want a standard to reduce traceability’s cost and complexity.In effect, customers want a standard that can be cited in a purchase order to their suppliers. This will require the supplier to mark (ECID, 2D code, RFID, etc.) their products with an ID unique for that supplier. The customer will verify the ability to read the ID and will reject devices that cannot be read, or disagree with the shipping information. This arrangement should propagate throughout the supply chain. As a result, the traceability draft standard developed by the Single Device Traceability Task Force looks at traceability from a system integrator’s perspective.Figure 1 captures the business problem for device traceability. Figure 1: Single Device Identification and Traceability Needs Permeate the Semiconductor Industry.Each time that a company ships product to the next company in the supply chain, it’s desirable to have traceability for the products being shipped while preserving the security of the information associated with those products. Initially, the only information that should be transferred is the device identification. In other words, the device traceability ID should not identify what the device is, nor should it provide any additional information relating to the device or its manufacture. In addition, the Traceability ID should not specify the number of devices shipped, the lot number associated with the devices, or any other information that might be of value to hackers or competitors. There is quite justifiable paranoia about the security of this information based on lessons learned.However, the whole point of traceability is to be able to backtrack a device through the supply chain when there’s a problem. Ultimately, any QA effort will need to know where the device was manufactured, when it was manufactured, the conditions under which it was manufactured, and other details that might help to discover the root cause of any problems.To get the additional information needed to troubleshoot a quality or manufacturing problem, a business relationship and NDAs (shown in Figure 1) must be in place between the various member companies in the supply chain. Traceability IDs based on the Single Device Identification and Traceability Standard will not carry that sort of information. They will simply allow analytic data to be obtained through appropriate business relationships.Figure 2 illustrates the types of fact finding that a Single Device Identification and Traceability standard would enable. Figure 2: Types of fact finding enabled by a Single Device Identification and Traceability standard. In this example, a Fabless or System manufacturer (shown in the center of the figure) might make an assembly that incorporates an MCM (multi-chip module) obtained from an OSAT (outsourced assembly and test) vendor. The MCM would bear a traceability ID on or inside the package. If a failure occurs in the MCM, the Fabless vendor contacts the OSAT, using an existing business relationship and NDA, and requests a comprehensive manufacturing report for the specific device using the traceability ID to identify the device in question. The OSAT then supplies a report to the Fabless company that provides the requested manufacturing data and any additional traceability IDs for the component parts in the MCM.The component traceability IDs in the OSAT’s report provide the Fabless vendor with the ability to track the MCM’s component die and package back to the semiconductor foundries and packaging vendor where these components were manufactured. These traceability IDs allow the Fabless vendor to request manufacturing reports for the components in question from the supplying foundries and the package vendor. Note that the reason that the reports go directly from the semiconductor foundries to the Fabless vendor as shown in Figure 2 is that the OSAT may not have comprehensive information about the function of these die and the Fabless vendor may want to keep that information private.The proposed new standard is called the “Specification for Single Device Traceability for the Supply Chain” and is SEMI Draft Document #6450. It addresses the first part of the systems integrators’ desire of being able to hold their suppliers accountable for having an established traceability scheme that would permit data analysis should the need arises. As of the end of November, the ballot proposal passed Technical Committee review and will undergo a procedural review process as part of the SEMI Standards development requirements. Once, these approval requirements are met, the specification will be prepared for publication and ready for industry adoption. Meanwhile, SEMI’s CAST Working Group and Standards Task Force will continue standardization efforts for device security and anti-counterfeiting. To join SEMI Standards activity, visit SEMI Standards or go directly to the Standards Membership Application.Dave Huntley is in business development at PDF Solutions.

Gas plasmas have become a fundamental building block in many semiconductor manufacturing processes. Plasma torches used to create these gas plasmas have three components: an induction coil, a plasma confinement tube, and a gas distributor or torch head that introduces multiple gases into the torch. RF generators supply the high-frequency electrical energy needed to transform the plasma-forming gases flowing through the torch, typically oxygen or a fluorine-bearing gas, into a plasma. The RF generators used for semiconductor manufacturing typically operate in the low megahertz or tens of megahertz frequency range and are expected to output high RF power at those frequencies for long periods. For example, ALD and CVD processes use RF generators with output powers on the order of a few kilowatts.About three years ago, a major semiconductor device maker experienced a recurring problem with its RF generators. The company found that more than half of the RF generators it deployed in its manufacturing lines were failing within the first two years of service. Further, the same model RF generators obtained from the same RF generator vendor simply were not behaving similarly when used for exactly the same processes under exactly the same conditions. Nor were these supposedly identical generators operating for consistent lengths of time before failing. Clearly there was variation from one generator to the next, even within the same model.A further complication occurred during procurement of these RF generators. Procurement people were acquiring generators using general specification requirements and these requirements were, at times, opaque to the intended process application. In some cases, equipment was being purchased in bulk quantities and then assigned to different processes on the semiconductor manufacturing lines. When these generators were deployed, they had not been designed or optimized for the specific task to which they were assigned, exacerbating the reliability problem.The RF generator suppliers felt that they would be able to supply more reliable generators if they could collaborate with their customers so that they could purpose-build their generators for the intended uses. However, the semiconductor makers preferred to keep the specifics of the manufacturing process applications for these generators proprietary, for obvious reasons. To make matters worse, customers did not always return failed units to RF generator vendors for analysis. Instead, the RF generators were sometimes sent out to be refurbished by third parties or repair depots, and then redeployed. As a result, failure analysis proved challenging to obtain.This is exactly the type of situation that SEMI’s Semiconductor Component, Instrument and Subsystem (SCIS) technical community exists to address. SCIS develops test methods aimed at measuring component defects for the greater semiconductor manufacturing community. SCIS tackled this RF generator problem and developed a standard test method for measuring specific RF generator characteristics. Using this test method, RF generator manufacturers can publish results for their generators in a standardized way that allows their customers to make fair, application-specific comparisons among models and vendors.Many aspects of an RF generator needed to be considered. A key aspect that interested integrated device makers (IDMs) and capital equipment OEMs was a transient-response test for RF generators.A transient-response test standard established by the SEMI-E135 standard did exist, but its tests were run only with 50-ohm RF output loads. SCIS decided to expand this transient-response test by adding high- and low-impedance load tests to the existing 50-ohm load test.The initial response to this plan was not enthusiastic. The semiconductor makers feared that this simple expansion of an existing test standard would not produce a test regimen that would help solve what they considered to be the real problem: RF generator reliability. However, a major semiconductor equipment OEM differed, and felt that the two additional load conditions would provide a much better understanding of an RF generator’s capabilities. A second major semiconductor equipment OEM also got involved by providing additional, valuable feedback on the developing RF generator testing standard.In the end, the general feeling in the community is that this newly revised standard levels the playing field and makes it easier for customers to compare RF generators from different generator vendors. Now that this revised SEMI-E135 standard with the additional output load resistances has been published, the SCIS technical community has gained broader support and is now digging into the creation of a reliability test standard for RF generators to meet the greater semiconductor manufacturing community’s strong need for such a standard.How SEMI Standards are MadeThis sequence of events illustrates how standards are developed at SEMI. The SCIS technical community (or some other technical community within SEMI) develops and incubates test methods until a document is ready for standardization. At that point, a SEMI Standards task force is created. Companies within SCIS work with the task force (or become the task force) to ready the document for standardization. For the SEMI-E135 revision, the list of participating companies encompassed the entire semiconductor manufacturing community including RF generator suppliers, semiconductor capital equipment OEMs, and IDMs. All stakeholders participate.Figure 1 illustrates the sequence of events that occurred during the revision of the SEMI-E135 standard, after the test methods had been developed by SCIS as discussed above. Figure 1: Timeline for SEMI-E135 RF generator test standard revision after SCIS had developed the new load tests. Balloting, as illustrated in Figure 1, is the main way that SEMI obtains global consensus in the standards-making process. To achieve this, SEMI sends out the standard ballot proposal, or in this case a major revision of an existing standard. The changes to SEMI-E135 were sufficiently extensive that it was treated as a complete rewrite to this standard.On first ballot, the revised SEMI-E135 standard received several rejection votes, which also included suggested modifications that would remove the objections. These ballot rejections caused the proposed standard to be further revised, with both technical as well as editorial changes, triggering a SEMI Standards process called a Ratification Ballot. This approach takes less time than starting the balloting process over again. The final revised standard was published in September 2018.Having all stakeholders participate in the early development of the revised standard helped move the standard through the balloting process immensely, but customer participation was especially important. In the end, the semiconductor device makers and equipment OEMs are the ultimate beneficiaries of a standard like SEMI-E135. When end customers help to drive a standard’s development, there’s added pressure to move the standard along in the standardization process and the standard is far more likely to be useful for their purposes.And that’s a very good thing.For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

There were over 220 participants at the recent SOI Academy FD-SOI Training event organized in Shanghai. The event extended over two days, with the first day covering a basic introduction to the technology as well as the ecosystem worldwide and in China. The second day was hands-on professional training. Attendees got a comprehensive understanding of how to leverage the benefits and flexibility of FD-SOI design techniques for low-power chips including logic, mixed-signal/RF and analog blocks. They had a great line-up of experts from whom to learn – check out the agenda here. There was also a follow-up press release (in Chinese) from SITRI here. There will be more of these SOI Academy events in cities across China in the year to come – we'll keep you posted (and of course, keep checking back for news on the Consortium's Events page). [caption id="attachment_12981" align="aligncenter" width="1000"] SOI Academy '18 keynotes by: Dr. Mark Ding, CEO, SITRI; Dr. Carlos Mazure, EVP Soitec and Chairman/Executive Director SOI Consortium. Dr. Julien Arcamone, EVP Leti. (Images courtesy: SITRI). Lower right: the hands-on FD-SOI training.[/caption] The two-day seminar and hands-on FD-SOI design training was (superbly!) co-organized by SITRI and Leti, with the support of the SOI Industry Consortium at the Jiading SIMIT campus outside of Shanghai. Just to put this in perspective, SIMIT and SITRI are absolutely key players in China's chip ecosystem. SIMIT is the Shanghai Institute of Microsystem and Information Technology, one of the most venerable institutes in the Chinese Academy of Science (CAS) and one of the world's earliest pioneers in SOI. SITRI is the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating innovation and commercialization of More-than-Moore for IoT. Both institutions are under the aegis of Dr. Xi Wang, Chairman of SITRI, Director General of SIMIT, Academician of CAS, and champion of all things SOI in China. At this Shanghai event, the participants came from industry (including big companies, SMEs and startups) and technical institutions. In fact as well as attendees from Shanghai people voyaged from other cities such as Shenzhen and Chengdu. The designers participating to the FD-SOI training day were all experienced in design and highly motivated in learning FD-SOI design, notes Carlos Mazure, Chairman Executive Director of the SOI Industry Consortium, and Executive VP of Soitec. “This made it possible to dive into the specificities of FD-SOI,” he said, adding that, “The focus on RF was very timely.” Day 1: Intro to FD-SOI The first afternoon opening keynotes were made by SITRI CEO Dr. Mark Ding and Leti EVP Dr. Julien Arcamone. These were followed by overview talks by execs from Soitec, Verisilicon and GlobalFoundries. After a lively networking break, three talks delved into FD-SOI technology. The first was by Professor Sorin Cristoloveanu, Laureate of the IEEE Andrew Grove Award and Director at the CNRS (the French National Center for Scientific Research – the largest governmental research organization in France and the largest fundamental science agency in Europe). He covered device physics and characterization techniques. This was followed by talks on the technology by Soitec Fellow Bich-Yen Nguygen, and by Dr. Christophe Tretz, IBM Sr. Engineer on product design methodology. The day ended with a dinner, where Professor Cristoloveanu says enthusiastic technical discussions continued unabated (and continued even further in follow-up emails), lots of business cards were exchanged, and opportunities for further education were explored. Day 2: Hands-on Training The second day, designers got hands-on training from Leti experts using FD-SOI PDKs, first in the morning on digital, then in the afternoon on RF. Everyone loved the lively discussion and in-depth exchanges between the experts and the designers. They agreed that FD-SOI has important applications and differentiated competitive advantages for IoT, 5G, automotive, AI and other fields. At the end of the training, Leti and SITRI jointly issued SOI Academy certificates of completion to the designers. Feedback from participants was very good. Some asked for further education and for hands-on testimonials from companies that are already designing and manufacturing products on FD-SOI. “The participants were focused, motivated, involved, with good knowledge, which helped make the three hours of Digital training effective,” said Dr. Alexandre Valentian, Leti Sr. Expert, Digital Design. “The IT team was very helpful in setting up the training, the students accounts and the hardware infrastructure.” “The training on Basics of FD-SOI RF circuit was a great success thanks to the efficiency of our Chinese partners and also thanks to the enthusiasm and the good level of our trainees. As senior Expert of CEA Leti I was really impressed by the professionalism of the organization team. For all these reasons, I’m very glad to have had the opportunity to contribute to the 2018 SOI Academy,” said Dr. Baudouin Martineau, Leti Sr. Expert, RFIC Design Technologies. “The professionalism, efficiency and enthusiasm of our Chinese partners and the level and technical relevance of all trainees made the training on Basics of FD-SOI RF circuit a great success and fruitful experience,” added Frédéric Hameau, Sr. RF Research Engineer, Leti Project Leader, Architecture, IC Design Embedded Software Division, RF Architectures and ICs Laboratory. “It was a pleasure to get the opportunity to be part of this first edition of SOI academy 2018.” The organizers would like to thank the sponsors, including: the SOI Consortium and its members Soitec, VeriSilicon, GlobalFoundries, Simgui and Cadence, as well as Mentor, ProPlus and other companies and institutions in China and worldwide. Dr. Mazure notes that special recognition must go to Dr. Julien Arcamone, EVP, Leti-CEA and to Qing Wang-Bousquet, SITRI representative, for the perfect and smooth organization, and to the Leti instructors, who are international experts and highly committed. “As one of the main initiators and organizers of the 2018 SOI Academy, I wanted to personally thank all of you for your respective contribution to this first edition of the SOI Academy,” concludes Dr. Arcamone. “Undoubtedly, it was a great success, very well organized and fluid and we can be proud of that.”

When developing industry forecasts, market analysts gather data from hundreds of companies to provide actionable insights on established technologies and to identify near-term business opportunities. As a developer of new MEMS and sensor technologies for a range of commercial applications, clients often ask us, “What’s going to be hot?” Gauging the promise of emerging technologies that are five to 10 years from commercialization requires taking a different tack.History tells us that most of today’s blockbuster MEMS products were born as academic research projects. Years of hard work by entrepreneurs, funded by millions of dollars, have turned proof-of-concept research into new commercial products. To identify up-and-coming technologies, we gather information straight from the source: academic conferences and articles.Chirp Microsystems is a good proof point of our research methodology: In my 2012 report on emerging technologies, I highlighted research from UC Berkeley and UC Davis on “In-Air Ultrasonic Rangefinding and Angle Estimation Using an Array of AlN Micromachined Transducers.” Soon after publication, the authors incorporated Chirp Microsystems to commercialize their technology for gesture- and fingerprint-recognition applications.After five years of development work, Chirp’s products are entering the marketplace. In February 2018, the global supplier TDK InvenSense acquired Chirp, underscoring the company’s commercial potential. At October’s SEMI-MSIG MEMS Sensors Executive Congress in Napa, Calif., Chirp’s CEO, Dr. Michelle Kiang, held attendees rapt as she described her company’s journey from startup to wholly owned subsidiary.There’s a methodThis year, I reviewed over 100 papers from top researchers presenting noteworthy technologies at the Hilton Head Workshop on Solid-State Sensors, Actuators and Microsystems. My criteria for selection were: commercial relevance; offers a solution to a known or anticipated problem; and technology game-changers. The following caught my eye: Event-driven sensors: Cleverly designed silicon MEMS that consume no power while standing by. A triggering mechanical or thermal event closes a contact within the sensor to activate its circuitry and telemetry. These sensors leverage existing fabrication methods, so they could become commercial products within five years for event monitoring and security applications. (UT Dallas, Northeastern University). Figure: 5-bit accelerometer having zero standby power. The device is open circuit until a threshold acceleration closes a mechanical contact. Source: University of Texas at Dallas. Thin film piezoelectric resonators: Advances in PZT deposition methods and process integration with CMOS were used to create monolithic acoustic waveguides for RF filtering in 5G applications. This new filter design, using existing scalable processes, is ripe for commercialization. (Purdue University, Texas Instruments) Intra-body communications: MEMS ultrasound transceivers, made from aluminum nitride, can send data directly through flesh at Mbit/s data rate. With trends toward networks of multiple implanted or wearable medical devices, this innovation would enable medically safe, secure, intra-body wireless communication. This early-stage work still needs in vivo validation and would likely require 10 or more years for development and regulatory approval. (Northeastern University) Screen- and 3D-printed sensors: One example of many exciting innovations using screen- and 3D-printing are potentiometric nitrate soil sensors. Low-cost and biodegradable, these sensors could be spread over huge areas to monitor a farm’s soil quality. Table-top and hobbyist tools are currently used to make screen- and 3D-printed devices, so new manufacturing equipment and infrastructure must be developed before commercial production could occur. (Purdue University) Biodegradable batteries: A paper-based battery that can deliver 0.5 uW of power, ingeniously using bacterial metabolism as the electrolyte. These batteries dissolve in water and could one day be used to power temporary medical implants or biodegradable sensors. This exciting proof-of-concept prototype will require significant process development and new manufacturing infrastructure for commercialization. (SUNY Binghamton) Figure: Paper-based battery dissolves in 60 minutes after immersion in water. Source: SUNY Binghamton To read more about these technologies, please download my presentation from SEMI-MSIG’s MEMS Sensors TechXpot at SEMICON West 2018.Alissa M. Fitzgerald, Ph.D., is the founder and managing member of A.M. Fitzgerald Associates, LLC, a MEMS and sensors development company in Burlingame, CA. She has over 20 years of engineering experience in MEMS design, fabrication and product development and now advises clients on the entire cycle of product development, from business and IP strategy to manufacturing operations. She is a frequent speaker at industry conferences and currently serves as a director of the Transducer Research Foundation, sponsor of the Hilton Head Workshop. She received her bachelor’s and master’s degrees from MIT and her doctorate from Stanford University in Aeronautics and Astronautics.For more information, visit: www.amfitzgerald.com

Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here). The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS sensors), and the SOI manufacturing ecosystem. The 1st day panel discussion was so interesting we'll give it a post of its own, then follow up with round-ups of the presentations from both days. And now to ramp! The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF's CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019. [caption id="attachment_12578" align="aligncenter" width="875"] Panel on FD-SOI and RF-SOI end-user deployment, SOI Workshop Japan, 2018. Giorgio Cesana, SOI Consortium Executive Director, Moderator; John Carey, ST Director; Adam Lee, Samsung Director; Subramani Kengeri, GF CTO; Wayne Dai, VeriSilicon CEO; Mostafa Emam, Incize CEO. (Courtesy: SOI Consortium)[/caption] VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI. ST Director John Carey noted that ST's been using FD-SOI since 2014. They've fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they've got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT. The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it's in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded. Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung's Lee said they've already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST's Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained. With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing. 5G – What's First? The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung's seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons. Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that's what tier-one players want. Carey brought it back to RF-SOI (noting that ST's introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won't be the bottleneck he said, so what's the FD-SOI/mmWave roadmap? Kengeri responded that GF's ready. Lee said Samsung is also ready, and you'd see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it's qualified. Carey said ST sees it first in consumer premises equipment that's connected by satellite. The right enabler Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn't give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it's very important. In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.