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The Japan semiconductor manufacturing supply chain is a global semiconductor industry workhorse, producing about one third of world’s chip equipment and more than half of its semiconductor materials. In contributing the vast majority of these products, SEMI Japan member companies hold the high distinction of enabling continuous development of the worldwide semiconductor industry. Aptly, then, technology powerhouses IBM, Nissan Motors and Toshiba offered insights into the latest trends and innovations in computing and smart cars at the late-May SEMI Japan Members Days in Tokyo with 133 technologists from member companies in attendance. As the audience discovered, chip innovation never sleeps and, as futuristic as it can be, invariably gives rise to possibilities beyond the human imagination. That was the message of kickoff presentation “Computing Reimagined – AI/Quantum/IoT” – by Dr. Shintaro Yamamichi, Senior Manager, Science Technology at IBM Research-Tokyo. Dr. Yamamichi cited three examples of how semiconductors uncover new technology frontiers. Computational materials discovery, a novel methodology, is the application of theory and computation to unearthing new materials and the key to enabling an ongoing stream of semiconductor innovation. In particular, using cognitive technology to mine huge volumes of literature reveal new insights into materials that uncover even more functionality such as greater conductivity and heat resistance. With new materials the oxygen of ever more advanced semiconductor chip manufacturing, the semiconductor industry will surely benefit from this methodology. The opportunity to accelerate quantum computing innovation is now. Launched in May 2016, the IBM Quantum Experience gives students, researchers and general science enthusiasts hands-on access to IBM’s experimental cloud-enabled quantum computing platform. The online platform features a forum for discussing quantum computing topics, tutorials on how to program IBM Q devices, and other educational material about quantum computing. Dr. Yamamichi encouraged the audience to join the program. The world’s tiniest computer, unveiled by IBM at the company’s Think 2018 conference in Las Vegas, packs several hundred thousand transistors and, IBM claims, the equivalent power of a 1990s x86 chip into a package smaller than a grain of salt. The computer’s small form factor (less than 1mm x 1mm) and low manufacturing cost means it can be embedded in product price tags and packages as an anti-fraud device using blockchain technology. Vehicles need to be both electric and intelligent as countries become more populous and traffic density increases. More drivers extend average drive time, boost greenhouse emissions, devour precious energy resources and lead to more traffic congestion and accidents. Dr. Haruyoshi Kumura, fellow at Nissan Motor, highlighted these issues in stressing the importance of a new era of intelligent mobility. To mitigate these problems, Nissan is focusing on the electrification and intelligence of its vehicles: Nissan’s electric vehicle, Leaf, reduces accidents with electric intelligence systems such as e-Pedal, which uses an accelerator pedal only for both acceleration and deceleration, and ProPILOT Park, a feature that automatically parks the car by using multiple cameras and ultrasonic sonars to detect pedestrians and other objects around the vehicle. With more than 90 percent of traffic accidents caused by driver error, Nissan plans to introduce autonomous driving on multi-lane highways by the end of 2018 and on city streets by 2020. By 2022, the company plans to roll out full autonomous driving to reduce traffic accidents caused by inattentive drivers. For full autonomous driving to materialize, sensor fusion technology must incorporate a combination of technologies – radar systems, light detection and ranging (LiDAR) systems and cameras – to identify the shapes and locations of nearby moving objects and measure their speed. Sensed information is then processed by a 3D graphic analyzer to make electric throttle, braking and steering decisions. The outlook for automotive industry includes car sharing and more electrification – both insights from Yoshiki Hayakashi, general manager, automotive solution strategic planning division at Toshiba Electronic Devices Storage, who offered his perspectives on trends in Japan’s automotive industry and beyond. To meet the requirements of the COP21 Paris agreement, the global automotive industry is shifting to electrification. Toshiba estimates 60 percent of new cars will be electric vehicles by 2040 to meet the International Energy Agency’s global EV outlook. In Japan, autonomous driving or advanced driver assistance systems (ADAS) will be offered in certain areas by 2020, the year of the Tokyo Olympic games. Growth of these advanced driving systems hinges on infrastructure development. Supporting data centers, intelligent transport systems, vehicle-to-everything connections, and smart city are all necessary components. Car ownership will begin to cede ground to car sharing with technology elites such as Tesla, Apple and Google leading the way. To expand the car-sharing industry, new alliances will take shape between new and old-guard automotive companies and electronics manufacturing services (EMS) providers. Autonomous driving requires precise 3D renderings of actual roadways using sensors for route mapping. While sensor fusion must be deployed for these capabilities, LiDAR offers better sensing range and space resolution precision than ultrasonic sonars, radars, and cameras. The next SEMI Japan members day is scheduled for October 30 in Tokyo. SEMI holds similar events in most regions where SEMI and its members operate. For the members events in your region, contact the SEMI office nearest you. Yoichiro Ando is a marketing director in SEMI Japan.
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Storage and memory chipmaker and SEMI China member Tsinghua Unigroup is gearing up to meet burgeoning product demand with huge investments in its manufacturing plants. But the high-tech enterprise under Tsinghua University is eyeing a much bigger prize – growth of the region’s semiconductor industry and the realization of its ambition to become a more prominent force on the global stage.Inspired by the national strategy, the Tsinghua Unigroup’s big spends include USD 24 billion in Wuhan (Yangtze Memory Technologies Co., Ltd.,) USD 30 billion in Chengdu, USD 30 billion in Nanjing and USD 100 billion in Chongqing, said Liu Hongyu, senior vice president of Tsinghua Unigroup, speaking at the SEMI China Equipment and Materials Committee meeting last month.Advanced packaging is another rich vein of opportunity the region is tapping for expansion, said Liu Hongjun, vice president of China Wafer Level CSP Co., Ltd., another SEMI China member attending the event, hosted by NAURA in Beijing. Hongjun sees strong growth for Fan-in, Fan-out, FCBGA, 2.5D and 3DIC, with Fan-out out front. Liang Sheng, administrative commission director at BDA, a business advisory firm supporting high-technology manufacturing in the E-Town economic development zone, pointed to 5G chips and smart, networked electric automobiles as drivers of the next growth phase of Beijing’s integrated circuit (IC) industry.Global tailwinds are lifting China’s semiconductor industry and the region’s hopes, with SEMI and major industry analysts raising their semiconductor industry growth projects for 2018 to between 9 percent and 16 percent. According to SEMI’s latest market report, global semiconductor industry manufacturing equipment revenue reached USD 17 billion in the first quarter of 2018, logging all-time highs after jumping 12 percent from the previous quarter and 30 percent year-over-year. Korea was the top-performing region at USD 6.26 billion, followed by China at USD 2.64 billion.Tighter integration with the rest of the global semiconductor industry is critical to the growth of China’s chip sector, and SEMI China is squarely focused on this assimilation, said SEMI China president Lung Chu. The spearhead of this effort is the SEMI Innovation Investment Platform (SIIP) China, established by SEMI China last year to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. To strengthen ties with other regions, SIIP China will stage a number of innovation and investment forums this year including Chinese Night at SEMICON West (July 10-12) and a SIIP China Forum in Silicon Valley (July 15). In August, representatives from the Korea chip industry will visit counterparts in China (August), and a China delegation will travel to Japan for meetings (October). SIIP China is also strengthening the region’s links with Germany and Israel as SEMI serves as a crucial bridge between China’s semiconductor sector and the global industry.At the invitation of Shanghai authorities and the Ministry of Commerce of the People’s Republic of China, SEMI China in November will join the China International Export Import Exposition in Shanghai, an event that will underscore China’s commitment to the openness and cooperation of its semiconductor industry with the international chip community. As part of the exposition, SEMI will work with the Ministry of Commerce and domestic chip manufacturers to begin development of a special integrated circuit (IC) zone. SEMI China members are welcome to participate.With workforce development no less vital to the future of China’s semiconductor industry, the Equipment Materials Committee offered potential solutions to the industry’s talent gap. Measures included targeting university students and engineers with industry lectures and courses in key cities, campus recruiting, talent training that members said they are willing to help SEMI coordinate and stage and, much like the push to better integrate China with the global semiconductor industry, mobilizing member resources around a campaign to polish the image of the industry to make it more attractive to students and young workers. Members of the SEMI China Equipment Material Committee gathered at NAURA in Beijing in June for a warm and lively discussion about global semiconductor industry cooperation and growing China’s semiconductor sector.Cherry Sun is a marketing manager at SEMI China.
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Standing-room only keynote speeches. A future awash in data amassed by transformative technologies and applications, with semiconductors at their core. Smart everything: Cars, medicine, manufacturing, workforce, you name it. The sheer numbers impressed as a record lineup of SEMICON West keynote speakers offered a glowing portrait of the future: The semiconductor industry stands on the cusp of a breakout expansion. Standing and seated shoulder-to-shoulder in the packed-to-gills opening keynote, the audience learned, indeed, that the best was yet to come: “This is the best SEMICON West, ever,” observed SEMI CEO Ajit Manocha. Here’s a glimpse of the keynotes by the numbers, starting with the luckiest of all. 7 – The number of keynotes – among the brightest lights in technology – sharing their visions of the future through the lens of breakthrough technologies that are nearly ready to make their indelible mark. Dozens of expert panelists also weighed in at SEMICON West, the annual U.S. flagship microelectronics gathering in San Francisco. 90 – The percentage of all data ever generated has been created in just the past two years as the cloud mushrooms with tweets, texts, emails, Facebook posts, YouTube videos, medical records and all manner of business information, noted Bill Bottoms, president and CEO of Third Millennium Test Solutions. In the years ahead, an almost unimaginable wealth of data will require analysis by artificial intelligence (AI) embedded in semiconductors to enable applications that go well beyond smart. 12-18 – That’s how many months it will take for data volume to double, predicted John Kelly III, IBM’s Senior VP, Cognitive Solutions. And it will double again and again, every 12-18 months. Kelly foresees a scale of growth “that will dwarf previous eras of computing … the number of opportunities is enormous.” Kelly’s four decades in computing gave considerable weight to his point that “in the industry, there has never been a more exciting point in time than today.” First – Technology is being re-born. Using baseball lingo, several speakers noted that we are just in “the first inning,” “the top half of the first inning” or “the beginning of the first inning” to make clear in the most emphatic terms the duration of prosperity that lies ahead for the industry. AI embedded in chips and demand for real-time analysis of AI data will be its fuel. As SEMI Americas president Dave Anderson observed with a smile, “We all know how long baseball games can go.” Third – That’s the current wave of machine learning the world is now experiencing, according to Sandia National Laboratories’ Principal Member Conrad James. Computers are now capable of solving many increasingly complex problems on their own, with no human intervention necessarily required, he said. 1000x – As spectacularly fast as computing power already is today, the industry will need to double that the rate of performance in the years ahead, predicted Applied Materials president and CEO Gary Dickerson. Demand for this herculean processing capacity will spur a “tremendous focus on innovation” among SEMI members, their customers and their customers’ customers. 5 to 15 – The remarkable amount of silicon that power today’s mobile devices will be overshadowed by the chips – equivalent in computing capacity to 5 to 15 cell phones – that will be the engine of self-driving and other features in future automobiles, predicted Pierre Ferragu, New Street Research Managing Partner, during the SEMI Bulls and Bears session. Automobiles with this souped-up computing capacity will sell in the millions worldwide in the years ahead, generating never-before-seen opportunities for the chip industry, he noted. 10,000 – It’s not just cars. Ten thousand is the number of sensors that will be built just into the wings of new Airbus A380-1000 aircraft, AMD CTO Mark Papermaster explained during his keynote. 10 terabits – The staggering amount of Facebook data uploaded daily in to the cloud, Papermaster noted. 1 Trillion – SEMI’s 2020 forecast that the industry will reach $500 billion in revenues by 2020 was eclipsed by one analyst, speaking at the SEMI Market Symposium on the first day of the event, predicted that the industry would top $1 trillion in the foreseeable future. SEMI’s Manocha later added that $1 trillion in industry revenue is possible by 2030, “maybe sooner.” 1 (sexy) coda – Coders are hip and software applications are the apple of the world’s eye. Even the most casual mobile device user knows that software apps makes it whirl. But “hardware is becoming sexy again,” said Applied Materials’ Dickerson, adding that equipment and other semiconductor hardware developed by SEMI members will enable the next great wave of global economic growth. Scott Stevens, SEMI
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White House-led panel to address U.S. goal to lead in development of next-generation microelectronicsSEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.Next Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R D) in technology innovation has become an economic priority.The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.MEDIA WHO WISH TO ATTEND MUST CONTACT IN ADVANCE SCOTT STEVENS AT +1.512.288.4050 TO OBTAIN ACCESS BADGES PANEL: National Strategy for Semiconductor and Microelectronic Innovation TIME AND DATE: 10:30 to 11:30 a.m., Wednesday, July 11 LOCATION: Yerba Buena Theater, 700 Howard St., San Francisco MODERATOR: Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy PANELISTS: Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory Dr. Jeremy Muldavin, Deputy Director of Defense Software Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.MEDIA CONTACTS:Mike Hall, SEMI Global, +1.408.943.7988Scott Stevens, for SEMI Americas, +1.512.288.4050
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Strong global semiconductor industry growth is helping power rapid expansion of China’s IC manufacturers in 2018, and continuing technology innovation is inspiring the region’s optimism over the long term, said Du Shanshan, senior analyst of SEMI China, at the recent SEMI China Member Day. The chief driving force behind this year’s growth of China’s IC industry is its equipment and materials market, with the sector riding a wave of a strengthening industrial infrastructure, a rapid increase of wafer manufacturing capacity, global leadership in new fab projects and large memory investments, Shanshan added. NAURA, a leading domestic provider of high-end IC equipment, is seeing robust growth after its push to recruit highly skilled talent and bolster its technology infrastructure, customer service system and supply chain, said Zhou Yang, vice president of Procurement at NAURA, which hosted the event. Yang said the key to NAURA’s success has been its unblinking focus on technology, product quality, fast product delivery, responsiveness to customer needs, cost controls, and environmental and social responsibility. Before visiting a NAURA factory, attendees reflected on how China’s IC manufacturers, using equipment and materials sourced domestically, seized the opportunity of global semiconductor growth to drive rapid local expansion. Excited about the growth potential of China's chip industry, members expressed their commitment to contributing to its independence and self-reliance. SEMI China Membership Grows Opening SEMI China Member Day, SEMI China president Lung Chu highlighted another expansion – SEMI China’s membership growth to nearly 400 companies, behind only the U.S. and Japan. Chu credited the increase, in part, to the steady growth of the global semiconductor industry. Chu said the increase also stems from the recognition that SEMI China is the China semiconductor industry’s best partner for fulfilling its ambition of becoming a more prominent player on the world stage. SEMI China’s member services platform that includes exhibitions and conferences, industry technical standards, industry research and analysis, a publicity apparatus and a talent development initiative provides powerful ways for the industry to Connect, Collaborate and Innovate. The platform enabled SEMICON China 2018 to set a booth and visitor record for the event, with attendees numbering 91,252, a highly successful 32 percent year-over-year growth. More than 50 SEMI member companies attended the 2018 SEMI China Member Day on June 6th in Beijing to explore opportunities for the global and Chinese semiconductor industry. Cherry Sun is a marketing manager at SEMI China.
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The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-Tencor, a speaker at the TechXPOT, for insights about the readiness of inspection and metrology tools for EUVL applications at 5nm and 3nm. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-TencorSEMI: In general, how would you characterize the readiness of inspection and metrology tools intended for EUVL applications at 5nm and 3nm? In particular, what are some of the remaining research and development challenges that need to be addressed for each of these nodes?Neeraj Khanna: KLA-Tencor is working closely with its customers to qualify and ramp EUV. Our suite of inspection, metrology and data analytic solutions are being implemented to enable EUV infrastructure readiness including, for example, new reticle and resist qualification, scanner qualification, and EUV ramp preparation. These EUV integration activities require process control systems that support a wide range of applications, including hotspot discovery, lithography modeling, focus/dose process window qualification, reticle print check, mask blank inspection, and process and tool monitoring.As with any major technology inflection, it is critical to understand sources of process variation to enable ramp at optimal yield. For example, stochastics result in random pattern variations, which have a major impact on EUV yield. To manage stochastics, IC manufacturers are deploying process control solutions that support fast modeling of stochastic variations coupled with high-sensitivity, high-coverage wafer defect inspection. Another example is a methodology called hybrid scanner utilization whereby, when EUV scanners are implemented in production, they will only be used for a few layers, while all other layers will be patterned with 193i scanners. This technique requires tighter control and monitoring of overlay budgets.SEMI: How are you able to achieve this tighter control and monitoring?NK: To understand why hybrid scanner utilization requires tighter control and monitoring of overlay budgets, it’s important to outline how this differs from current scanner implementation. For critical layers in current process flows using 193i lithography, pattern layers for a given wafer are printed using the same stage/chuck on the same scanner. The overlay performance achieved using this lithography strategy is called dedicated chuck overlay (DCO). Use of a dedicated scanner and chuck for lithography reduces inter-scanner and inter-chuck distortion effects, resulting in DCO overlay error of less than 1nm. When EUVL is first implemented in production, it will be used for a few layers – likely, cut masks and contacts with eventual migration to metal 1 layers. All other layers will be patterned with 193i scanners. This hybrid scanner operation eliminates any possibility of using a dedicated scanner and dedicated chuck to support tight overlay performance specifications. Instead, fabs will be forced to optimize mix-and-match overlay (MMO), with the overlay performance obtained using different scanners for printing different layers on a given wafer.With overlay specifications for advanced DRAM and logic at ~2.5nm, fabs will need to implement strict 193i-to-EUV scanner matching strategies or risk consuming 60 to100 percent of the overlay budget on just MMO. To achieve tighter overlay control and monitoring required for MMO, fabs need to implement dense, in-field overlay error measurements that feed into scanner fleet management systems. KLA-Tencor’s ATL™ overlay metrology system supports a high measurement speed and the use of small in-die targets, enabling dense in-field overlay measurements with high accuracy. Our 5D Analyzer® data analytic and management system includes scanner fleet management capability that enables automatic product-based corrections to minimize MMO error, helping fabs reduce the risk to yield loss associated with a 193i-EUV mixed scanner implementation. SEMI: What other challenges do you see coming to the fore at 5nm and 3nm?NK: Overall, the 5nm and beyond design nodes will face challenges associated with new lithography technology, potential new device structures and smaller pattern pitches. IC manufacturers will require process control solutions that not only identify process windows, but also monitor patterning parameters and defectivity at multiple points to identify process shifts. To monitor dynamic processes at these advanced nodes, inspection and metrology tools will need to have both sensitivity to critical parameters/defects and robustness to process variation in order to provide IC engineers with smart feedback for efficient control of their processes.SEMI: Could you elaborate on what will be required to monitor patterning parameters and defectivity at multiple points? How different will the techniques be at 5nm/3nm vs. at say, 7nm or 10nm?NK: As an example of monitoring at multiple points, consider the transition to EUV lithography. With EUV, the cost per scan goes up dramatically. Thus, IC manufacturers will monitor parameters at multiple points to maximize yield and minimize risk: EUV reticle qualification requires inspection and metrology throughout the entire flow from mask blank manufacturing, to the mask shop, to the IC fab. For the advanced design nodes associated with EUV, wafer qualification requires monitoring and control of wafer defectivity, shape and geometry throughout the wafer manufacturing process. It also requires control of fab incoming wafer qualification while ensuring that fab-wide processes are meeting defect and shape standards necessary for printing smaller feature sizes. EUV resist characterization and qualification requires comprehensive lithography simulation, wafer defect inspection, and film thickness and uniformity measurements to help reduce development time and prepare the litho stacks for production ramp. As EUV scanners are ramping, fabs are faced with finding any unknown particle sources within the new scanner chambers. This situation is driving the need for tighter and more frequent PWP (particles per wafer pass) chamber monitors to ensure scanner cleanliness. In addition, EUV scanner qualification requires reticle front and backside particle checks, and hotspot discovery and process window qualification using optical wafer defect inspection and e-beam review. EUV process monitoring encompasses overlay error monitoring, focus/dose monitoring, critical dimension (CD) and 3D device shape monitoring, and continuous process window monitoring. EUV inline defect monitoring and tool monitoring is important for reducing baseline defectivity in the litho cell for faster ramp, and for early identification of litho excursions in production. A critical part of this monitoring strategy is inline after develop inspection (ADI) monitoring, which is defect inspection on patterned wafers after printing and development of the resist ADI. Inline ADI innovations that find yield-critical defects allow fabs to reduce process issues, prevent at-risk wafers early in the process, and enable rework when excursions are found in production. As with past technology transitions, the implementation of multiple monitoring steps as part of a comprehensive process control strategy will be critical for a fab’s successful ramp of EUV.Debra Vogler, SEMI
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New metrology and inspection technologies and new analysis approaches made possible by improving compute technology offer solutions to finding the increasingly subtle variations in materials and subsystems that meet specifications but still cause defects on the wafer. More collaboration across the supply chain is helping too. SEMICON West programs on materials and subsystems will address these issues. New metrology approaches needed to deal with process margin challenges As device process margins shrink and subtler materials variations cause unwanted deviations, the need for better monitoring of both surface and sub-surface material variations is driving a trend towards “metro-spection” – the convergence of metrology and inspection. “Device process margins have eroded to the point that traditional metrology strategies and techniques are no longer viable for controlling yield and parametric performance,” says Nanometrics Vice President Robert Fiordalice, who will speak in the materials program at SEMICON West. “Limited sampling capability, low throughput, insufficient sensitivity or the destructive nature of the techniques can often become problems. What’s more, deviations in material characteristics are not always determined by the initial quality of the material, but often arise from variations during the integration of the materials.” One new type of inline tool or line monitoring technology is Fourier Transform Infrared (FTIR) spectroscopy, traditionally used in quality control or tool characterization. Better sensitivity and higher throughput now enable rapid analysis and feedback for on-the-fly detection of subtle deviations in film properties that may compromise device performance or yield. More advanced analytics will help extract new information from old metrologyMore expensive metrology may not be required to identify subtle variations in in-spec materials that cause wafer defects. Today’s advanced compute capabilities now enable more sophisticated analysis of existing data and the identification of small but significant variations in raw materials and finished goods. The figure of merit (FoM) values presented in certificate of analysis (CoA) reports miss subtle variations in raw material properties. Of particular note is the reduction of molecular weight distributions to a mean, and standard deviation, whereas variations in the tails are associated with pattern defects. Advanced compute capabilities now allow the industry to step beyond the FoM in favor of more holistic measures, enabling predictive analysis of resist chemical variations associated with specific pattern defects. Source: JSR Micro“We often don’t need to find a new measure, but just a new way of looking at what we measure now,” says Jim Mulready, vice president of global quality assurance at JSR Micro. Mulready will speak in the SEMICON West program on materials defectivity issues. “The certificate of analysis reduces multiple measurements to a single figure of merit. But if we ignore all that raw data, we miss a chance to learn. One of our sayings in quality is ‘Customers don’t feel the average, they feel the variation.’ In many electronic materials, the quality of the raw material can have a big impact on the final performance, but the types of analysis needed to look at the tails of the distribution of these measures (such as molecular weight) in detail used to be really hard to do. Now it’s becoming increasingly straightforward and affordable.” Mulready says tools now available in the data processing sector enable the identification of subtle variations in materials that can cause defects on the wafer. These tools use methods like detailed subtractions of chromatography curves of polymer raw materials or analysis of tails of distributions of molecular weights. “Our job now is to drive these kinds of more sophisticated data analysis back into our chemical supply chain as well,” says Mulready. “We must work more closely with our suppliers to integrate their raw materials into our products. The reason the JSRs of the world exist is as a safety valve to reduce the variation from the chemical industry before it gets to the fab.”Continued collaboration with equipment suppliers required While the industry has been talking about the need for tighter collaboration between materials suppliers and equipment manufacturers for years, it still doesn’t always happen. “The material supplier and the equipment maker are tied together like kids in a three-legged race when we deliver an integrated system for consistent on-wafer performance,” says Cristina Chu, TEL/NEXX director of strategic business development, another speaker in the materials program. “When we introduce changes to the tool hardware, we need to make sure it doesn’t upset the system. Similarly, we need the material supplier to send a bottle over when a new chemistry formulation is under development. If a new chemistry runs into problems in the field, it will take much more time for both of us to fix it at the customer site. The toolmaker can provide a slightly different perspective on applications, while being more objective than a customer on how the formulation performs compared to earlier versions.”Regular and ongoing collaboration between chemistry suppliers and toolmakers enables the highest quality system solution to reach the customer. Chu notes that her team tries to maintain consistent collaborations with material suppliers across changes in organizations as the business environment changes. “For consistent on-wafer capabilities, we need a consistent collaboration process with chemistry suppliers. We need to meet with materials providers at a regular cadence throughout their development process. We need to check back with them as we scale up results from the coupon to the wafer level and to work out the kinks in the integrated solution together. The quality and consistency of our combined performance at the customer depends on ensuring the quality and consistency of our development and evaluation process as well.”Fabs and subsystems suppliers look to pilot data sharing program to improve process margins With ever tighter process margins, subtle variations in parameters that don’t appear in the specifications are also compromising results on the wafer, and neither the fab nor the supplier alone has the full information needed to improve performance. To help, a SEMI standards group is developing a protocol for a pilot program to standardize and automate some data sharing.The fab knows that performance is best with a particular parameter value, and knows when performance fluctuates, but often faces a black box problem with no way of knowing what exactly is wrong. In the rush to get the tool back up, the fab engineers may not get around to emailing the supplier about the issue for some time. The subsystems supplier, on the other hand, may know the cause of the variation, but likely has no way of knowing the critical parameters or ideal target values for the fab’s process. “In order for engineers to have constructive conversations about how to improve performance, we all need to exchange more information,” says Eric Bruce, Samsung Austin diffusion engineer, and co-chair of the SEMI Standards initiative addressing the issue, who will speak in the subsystems program at SEMICON West. A potential solution could be to create a standard and automated process to share particular data, agreed to in the purchasing contract, whereby the subsystems supplier shares more information about their parameters with the fab, and the fab in return gives feedback on what parameters work best to drive improved performance. The best place to start will likely be on parts that do not contain core yield-related IP, but where usage and lifetime information is useful.“We’re looking for people to participate in a pilot program to work together with suppliers to try sharing some information to improve performance,” says Bruce. “There’s a lot of this sharing in the backroom anyway, but this could make it fast and automated, and make everyone’s engineering job a lot easier.”Paula Doe, SEMI
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For medtech applications to flourish, sensors need a supporting infrastructure that translates the data they harvest into actionable insights, says Qualcomm Life director of business development Gene Dantsker, who will speak about the future of digital healthcare in the Medtech program at SEMICON West. “Rarely can one device give a complete diagnosis,” he notes. “What’s missing is the integration of all the sensor data into prescriptive information.” The maturing medtech sector has developed to the point where sensors can now capture massive amounts of data, conveniently collected from people via mobile devices. The sector now has higher compute capacity to process the data, and improving software can produce actionable insight from the information. The next challenge is to seamlessly integrate these components into legacy medical systems without disrupting existing workflow. “Doctors and nurses don’t have time for disruptive technology – a new system has to be invisible and frictionless to use, with one or fewer buttons, no training and truly automatic Bluetooth-like pairing,” he says. “So device makers need to pack all system intelligence into the circuits and software.”Getting actionable healthcare information from sensors requires integration into the existing medical infrastructure. Source: Qualcomm LifeOne interesting example is United Healthcare’s use of the Qualcomm Life infrastructure to collect data from the fitness trackers of 350,000 patients. The insurance company then pays users $4 a day, or ~$1500 a year, for standing, walking six times a day and other behaviors that clinical evidence shows will both improve patient health and reduce healthcare costs. “It’s a perfect storm of motivations for all stakeholders,” he says.Next hot MEMS topics: Piezoelectric devices, environmental sensors, near-zero power standbyWith sensor technology continuing to evolve, look for coming innovations in MEMS in piezoelectric devices, environmental sensors and near zero-power standby devices, says Alissa Fitzgerald, Founder and Managing Member of A.M. Fitzgerald and Associates, who will provide an update on emerging sensor technologies in the MEMS program at SEMICON West.Piezoelectric devices can potentially be more stable and perhaps even easier to ramp to volume than capacitive ones, with AlN devices for microphones and ultrasonic sensors finding quick success. Now the maturing infrastructure for lead zirconate titantate (PZT) is enabling the scaling of production of higher performing piezo material with thin film deposition equipment from suppliers like Ulvac Technologies and Solmates and in foundry processes at Silex and STMicroelectronics, she notes.In academic research, where most new MEMS emerge, market interest is driving development of environmental sensors and zero-power standby devices. With demand for environmental monitoring growing, much work is focusing on technologies that improve the sensitivity, selectivity and time of response of gas and particulate sensors. Research and funding is also focusing on zero or near-zero power standby sensors, using open circuits that draw no power until a physical stimulus such as vibration or heat wakes them up.MEMS, however, likely won’t find as much of a market in autonomous vehicles as once thought. “While the automotive sensor market will need many optical sensors, MEMS players are competing with other optical and mechanical solutions,” says Fitzgerald. “And here the usual MEMS advantage of small size may not matter much, and the devices will have to meet the challenging automotive requirements for extreme ruggedness.”Paula Doe, SEMI
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What’s next for smarter, more connected electronics manufacturing - Part 3 The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco. While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development. “People don’t think of research and development as the first place to automate, but it’s where applying our digitization and simulation has first had impact,” says David Fried, Coventor vice president of Computational Products. He noted that insertion is easier in the lab than in the fab. Technology at 10nm and beyond is now so complex that companies at the leading edge must use process modeling to understand the effect of process variation on their designs. Learning cycles can now be accelerated during development by simulating 10,000 digital wafers instead of running 25 actual wafers during screening, Fried says. Applying structured analysis and machine learning to the data simplifies optimization across the 500 or more interrelated process steps. Coventor has recently introduced a statistical analysis package that aids the design and analysis of process variation experiments by using large volumes of data from its models. Fried says these models are next being used to accelerate the yield ramp in manufacturing. Digital simulation also could speed development of high-mix, lower value products While digital twins are best known for their use in complex, high value products like jet engines, the simulation technology could also enable the electronic manufacturing services (EMS) sector to reduce the time, cost and risk of developing its high mix of products. “The EMS sector’s use of digital twins will be vital for it to smooth the move of CAD/CAM digital design data for so many different products into manufacturing, and to accelerate validation testing of designs and products by doing more of it in the virtual world,” says Dan Gamota, vice president of Engineering and Technical Services at Jabil. Gamota also highlights the push for traceability from the automotive and healthcare markets, where the digital models could be used to quickly assure that the design was built exactly as specified. “In the past year, traceability has evolved from just ‘nice to have’ to ‘how to achieve,’” he adds. “Companies are expecting it, but aren’t willing to accept the cost and risk of doing it alone. We need the community to discuss realistic implementations, identify the most critical elements and bring together the ecosystem partners to build baseline reference architectures for key digital building blocks. The community also needs to assure the reliable flow of data among the electronic manufacturing segments from semiconductor to OSAT to EMS.” Predictive maintenance and virtual metrology applications could mature in next few years While predictive maintenance initially seemed a likely early application of machine learning in factories, it remains a challenge for the electronics sector. “The difficulty is that it’s not clear where to get the most bang for the buck,” says Tom Ho, president of BISTel America, noting that it may make the most sense to track the failure performance of a single expensive part, like an electrostatic chuck, since predicting the failure performance of a whole complex system like an etcher is much harder. “Collecting enough data from all failure types, including especially the rare events, is difficult unless you have a long history of a lot of tools,” adds Doug Suerich, PEER Group product evangelist. “The gain from collecting performance information from many tools across the industry could be big, but many companies still need to overcome concerns around exposing their IP.” Another big opportunity for prediction is virtual metrology – predicting the wafer outcome from the process or sensor data with enough accuracy to replace the physical metrology. “Virtual metrology is improving, and since metrology can be slow and expensive, any reduction could mean a huge potential savings,” says Suerich. “But it is still seen as too scary for many companies. Two to three years from now, companies will expand the practice from lower risk areas into processes that require more confidence in the results.” Moving beyond prediction to automated control needs digital models Once the results are predicted, the model can be used to control or automatically optimize a process and enable the system to learn by itself, usually by reinforcement learning on a digital model. The model can then independently make adjustments to optimize the manufacturing process. “Automated process development is getting close now. Instead of smart guys turning the knobs, deep learning is automating the smart tuning,” says Suerich, suggesting the industry could see widespread adoption in as little as two to three years. This type of machine learning needs a good digital model, and masses of data for learning. One approach uses human experts to build a physics-based model of the clearly understood parts of the process, then turns to deep machine learning to optimize the lesser-understood variables. The alternative, the data-first approach, runs a computer algorithm to suggest the solution purely from data, without human input, and then relies on the human to evaluate the usefulness of the results. Modeling digital twins of wafers could enable automated process control, chamber matching, and fleet matching, says Fried. If every wafer had its own virtual twin with all the upstream metrology and structural information needed to make equipment control decisions, it could feed forward that information to enable the seamless transition from one step in the process to another based on understanding their complex interrelationships. This could potentially improve uniformity across wafers and equipment, and reduce the need for metrology, he argues. Moving metrology sensors into the chamber will also require model-based algorithms to enable dynamic process control in close to real time, says Fried. These algorithms will be needed to acquire, parse, and process the data at high speed, and then to choose how to adjust the controls. “There will be a model behind collecting and interpreting the metrology data,” he notes. “That’s a really rich vein for improvements in process control.” “The end goal is to collect equipment data in real time, analyze it with AI, and send back controls to optimize manufacturing processes,” Jabil’s Gamota says. “This requires a robust architecture for communication between equipment and consistent formats for data collection and analysis. But the cost and complexity of this heavy lifting is too great for any one company to do alone. We need a consensus-based architecture for ingesting, analyzing and acting on the data.” SEMI tests data transfer protocols, benchmarks best practices SEMI is launching a smart data project to identify the various data transfer protocols needed for inter-company communications. The project will feature a proof-of-concept model in a development fab to produce verifiable results so SEMI can better understand how different approaches meet member needs. SEMI’s smart manufacturing technology communities and the Fab Owners Alliance are also benchmarking current smart manufacturing practices in the microelectronics industry to help SEMI members better understand the path forward and potential return on investment. Speakers over all three days at SEMICON West addressing these issues include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org. What’s next for smarter, more connected electronics manufacturing - Part 1 What’s next for smarter, more connected electronics manufacturing - Part 2 Paula Doe, SEMI
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With artificial intelligence (AI) rapidly evolving, look for applications like voice recognition and image recognition to get more efficient, more affordable, and far more common in a variety of products over the next few years. This growth in applications will drive demand for new architectures that deliver the higher performance and lower power consumption required for widespread AI adoption. “The challenge for AI at the edge is to optimize the whole system-on-a-chip architecture and its components, all the way to semiconductor technology IP blocks, to process complex AI workloads quickly and at low power,” says Qualcomm Technologies Senior Director of Engineering Evgeni Gousev, who will provide an update on the progress of AI at the edge in a Data and AI program at SEMICON West, July 10-12 in San Francisco. Qualcomm Snapdragon 845 uses heterogeneous computing across the CPU, GPU, and DSP for power-efficient processing for constantly evolving AI models. Source: QualcommA system approach that optimizes across hardware, software, and algorithms is necessary to deliver the ultra-low power – to a sub 1-milliwatt level, low enough to enable always-on machine vision processing – for the usually energy-intensive AI computing. From the chip architecture perspective, processing AI workloads with the most appropriate engine, such as the CPU, GPU, and DSP with dedicated hardware acceleration, provides the best power efficiency – and flexibility for dealing with rapidly changing AI models and growing diversity of applications.“So far it’s been largely a brute force approach using conventional architectures and cloud-based infrastructure,” says Evgeni. “But we’re going to run out of brute force options, so future opportunities lie in developing innovative architectures, dedicated hardware, new algorithms, and new software. Innovation will be especially important for AI at the edge and applications requiring always-on functionality. Training is mostly in the cloud now, but in the near future it will start migrating to the device as the algorithms and hardware improve. AI at the edge will also remove some privacy concerns, an increasingly important issue for data collection and management.”Practical AI applications at the edge where resources are constrained run the gamut, spanning smartphones, drones, autonomous vehicles, virtual reality, augmented reality and smart home solutions such as connected cameras. “More AI on the edge will create a huge opportunity for the whole ecosystem – chip designers, semiconductor and device manufacturers, applications developers, and data and service providers. And it’s going to make a significant impact on the way we work, live, and interact with the world around us,” Evgeni said.Future generations of chips may need more disruptive systems-level change to handle high data volumes with low power A next-generation solution for handling the massive proliferation of AI data could be a nanotechnology system, such as the collaborative N3XT (Nano-Engineered Computing Systems Technology) project, led by H.S. Philip Wong and Subhasish Mitra at Stanford. “Even with next-generation scaling of transistors and new memory chips, the bottlenecks in moving data in and out of memory for processing will remain,” says Mitra, another speaker in the SEMICON West program. “The true benefits of nanotechnology will only come from new architectures enabled by nanosystems. One thing we are certain of is that massively more capable and more energy-efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.” Major improvement in handling high volumes of data with low high energy use will require system-level improvements, such as monolithic 3D integration of carbon nanotube transistors in the multi-campus N3XT chip research effort. Source: Stanford UniversityThat means carbon nanotube transistors for logic, high density non-volatile MRAM and ReRAM for memory, fine-grained monolithic 3D for integration, new architectures for computation immersed in memory, and new materials for heat removal. “The N3XT approach is key for the 1000X energy efficiency needed,” says Mitra.Researchers have demonstrated improvements in all these areas, including multiple hardware nanosystem prototypes targeting AI applications. The researchers have transferred multiple layers of as-grown carbon nanotubes to the target wafer to significantly improve CNT density and have also developed a low-power TiN/HfOx/Pt ReRAM. The low-temperature CNT and ReRAM processes enable multiple vertical layers to be grown on top of one another for ultra-dense and fine-grained monolithic 3D integration. Other speakers at the Data and AI TechXpot include Fram Akiki, VP Electronics, Siemens; Hariharan Ananthanarayanan, motion planning engineer, Osaro; and David Haynes, Sr. director, strategic marketing, Lam Research. See SEMICONWest.org.Paula Doe, SEMI
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