Business and Markets

Extended Plateau, Not a New Cycle: The Broader Industry PictureThe current recovery in the semiconductor market appears to signal revival, yet is best understood as an extended phase of the existing cycle—a phase defined less by renewed demand than by structural restraint and efficiency-driven realignment.AI-related demand is indeed driving the rebound, yet this recovery differs fundamentally from past expansionary booms. It is unfolding within an efficiency-driven adjustment phase, where capital expenditure has shifted its focus from capacity expansion to process upgrades and optimization. The observed recovery therefore reflects structural realignment rather than a conventional cyclical upswing.This realignment has created an ‘Extended Peak Plateau’—a state not of cyclical acceleration but of structural transformation. The imbalance between resilient equipment and materials spending and stagnant wafer shipments has produced an uneven recovery, concentrated in select high-value segments rather than evenly across the value chain. The apparent plateau seen today stems less from broad-based demand expansion than from price-anchored growth, sustained by firm pricing in premium segments such as AI-related and high bandwidth memory (HBM) products.At the same time, semiconductor manufacturers—particularly in memory—have adopted a supply-controlled operational strategy, emphasizing process optimization and product upgrades over large-scale capacity additions. Together, these three structural forces—supply/demand imbalance, price-anchored resilience, and efficiency-oriented adaptation—have defined the industry’s current phase, where revenue growth remains elevated but plateaued rather than accelerating or decelerating.In this context, the recent rise in DRAM prices and continued hyperscaler investment hold implications beyond short-term variables: They determine whether the industry can sustain equilibrium without widening the amplitude of future cycles between overheating and contraction. If DRAM recovery remains purely supply-driven, the upturn will likely be shallow; conversely, a slowdown in hyperscaler investment could undermine the demand foundation itself.This is why the report characterizes the current phase not as a “new cycle” but as an extended plateau. While AI-driven momentum has already taken hold, the transition toward a stable and balanced industry structure must pass through the filter of efficiency. This efficiency-based rebalancing will, in all likelihood, require a period of adjustment before a truly sustainable equilibrium — the foundation for the next phase of genuine growth — can emerge.Desynchronization Between Investment and Wafer Demand: Evidence of a Structural ShiftThe chart below visually illustrates this structural asymmetry. When normalized to Q1 2019 = 100, as of Q2 2025 equipment investment has rebounded to roughly 244, photoresist revenue to 200, and total semiconductor revenue to 184—yet wafer shipments remain near 110 and wafer revenue around 103.Diverging Trends Across the Semiconductor Value Chain (Q1 2019 = 100) * Note1. Data sources: SEMI (WWSEMS, Silicon Wafer Shipment, Photoresist Market Data), WSTS, and IR disclosures from the top five wafer suppliers.2. Wafer revenue reflects the aggregated sales of the top five suppliers; Shin-Etsu’s quarterly figures are estimated from 2Q 2021 onward.3. Semiconductor fab equipment investments reflect only wafer-processing equipment (WFE) expenditures, based on the Wafer Processing Equipment category defined in SEMI’s WWSEMS dataset. All indices are normalized to Q1 2019 = 100; wafer area shipments are originally reported in million square inches (MSI), while other indicators represent revenues or investments in U.S. dollars (USD). The data clearly indicate that while equipment and materials have rebounded, wafer shipments and related revenue remain subdued. This divergence is not a matter of cyclical timing; rather, it reflects a re-alignment of the industry’s recovery dynamics, driven by process complexity and efficiency-oriented capital deployment. In other words, the widening gap between investment and wafer industry output symbolizes the industry’s transition from expansion-driven growth to efficiency-driven operations.In previous cycles, the linear linkage of “investment expansion → production expansion” prevailed. Today, however, investment is now synonymous with process-efficiency improvement rather than capacity growth. Behind this shift lie longer cycle times, rising process complexity, and the increasing concentration of demand in AI-related nodes. More complex manufacturing now requires process sustainment, advanced process control, and continual upgrades—CapEx allocation now reflects this shift.At the same time, a clear gap has emerged between wafer revenue and shipment growth, underscoring the divergence between financial recovery and physical output. In other words, shipment volumes have improved, but average selling prices remain subdued, signaling that the recovery is not demand-driven. This indicates that the current phase is sustained not by broad-based demand expansion, but by selective growth achieved through efficiency gains and product-mix adjustments. Despite this widening gap, the industry may give the outward impression of a steady growth plateau, since CapEx spending and high-value segments continue to post solid growth. Yet what appears as stable growth in the semiconductor and equipment market could be, in fact, a structural illusion—a state shaped by process complexity, efficiency-driven investment, and deliberate product-mix management. In short, this perceived growth is the by-product of financial and supply discipline, not the result of renewed demand momentum.Realignment of the Wafer Industry: A Gradual 300 mm-Led Shift Anchored in Efficiency and Portfolio StrategyAs the broader semiconductor ecosystem shifts its focus from expansion to efficiency—and from scale to high value and customer reliability—wafer manufacturers are, in turn, redefining their competitive edge around operational efficiency and the stable delivery of high-value products. The 300 mm wafer segment continues to lead the recovery, whereas 200 mm wafer shipments remain significantly below its 2022 peak, constrained by sluggish demand from legacy and non-memory applications. On the profitability front, depreciation burdens and persistent pricing pressure are creating dual headwinds.To navigate this environment, leading wafer suppliers are pursuing a dual-track approach: renegotiating long-term supply agreements (LTAs) while managing short-term contracts and selective and disciplined pricing to sustain utilization. At the same time, they are optimizing product portfolios to balance cash-flow defense with strategic offense. In this context, the critical question is shifting from “How much can be sold?” to “What kind of portfolio—specifically, how consistently can high-value wafers be sold and delivered?”In essence, performance is now measured less by expansion and investment scale, and more by efficiency, sustainability, and reliability. This strategic realignment mirrors the broader efficiency-driven transition underway across the semiconductor value chain, underscoring that the wafer industry is no exception to the global shift toward disciplined, portfolio-centric growth.Conclusion: The Path to True Recovery — When Three Forces AlignIn summary, the current semiconductor market is best understood as having entered an extended plateau following the peak of the present cycle, with its future trajectory hinging on how effectively DRAM price resilience and Big Tech investment continuity can restore balance. In essence, the outcome will depend on the market’s ability to narrow the amplitude between overheating and contraction, moving toward a more sustainable equilibrium. Rather than focusing on the DRAM price rebound driven primarily by supply adjustments or on demand concentrated in specific sectors, what truly matters for the wafer industry is the structural alignment of three key forces: (1) the recovery of broad-based and genuine demand, (2) the stabilization of the semiconductor supply structure, and (3) the improvement of operational efficiency across the value chain. The moment these three forces align will signal the true onset of the next upcycle — not only for the broader semiconductor market, but also for the global silicon wafer industry.Such alignment rarely occurs quickly — it requires time, discipline, and structural patience.This article distills the key insights from the Market Update section of the Q3 2025 Silicon Wafer Market Monitor Report. In this quarter’s analysis, the focus lies on the semiconductor cycle’s transition into an Extended Peak Plateau — a phase characterized not by broad-based expansion, but by efficiency-driven operations and portfolio realignment. Drawing on shipment, revenue, and CapEx data across wafers, materials, and equipment, this section identifies structural asymmetries between investment and shipment dynamics, and explores how efficiency gains, product-mix optimization, and supply discipline are reshaping the industry’s recovery trajectory.Separate from this focused article, the full SEMI Silicon Wafer Market Monitor Report provides a wider array of charts and indicators, offering a multidimensional perspective on how key variables interact to shape the future of the global wafer industry. Rather than serving as background commentary, the full report aims to deliver data-driven, decision-ready insights that support strategic thinking amid persistent market uncertainty.For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on SEMI market data are available at SEMI Market Data. Sungho Yoon is a Principal Analyst on the SEMI Market Intelligence team.

On September 16, 2025, the Inclusive Chips Forum organized by Platform Talent voor Technologie at the High Tech Campus Eindhoven convened changemakers from across Europe’s semiconductor ecosystem to share insights and strategies for building a more inclusive industry.This full-day program was designed to showcase practical strategies, inspiring case studies, and collaborative solutions aimed at strengthening inclusion, innovation, and resilience in the semiconductor industry. With Europe’s role in the global semiconductor landscape under intense focus, the forum highlighted why building a workforce culture rooted in equity and belonging is not just the right thing to do, it’s a strategic imperative.A Thought-Provoking Panel on Inclusive LeadershipA central question resonated throughout the conversation: What if inclusivity were treated as a core component of leadership development, as fundamental as financial management or strategic planning, rather than an optional module or one-off seminar?The discussion surfaced several critical insights for the industry and beyond:Awareness alone is not enough. While raising awareness about bias and stereotypes is important, research and experience show it rarely leads to behavioral change on its own. Lasting change comes from setting clear norms, leaders must define and model what is acceptable, expected, and celebrated in organizational culture. As Sahar Yadegari, Executive Director of Expertisecentrum voor haar technische ontwikkeling, emphasized:“Awareness is a starting point, not the finish line. Real change happens when inclusion is built into systems — not treated as an add-on.” – VHTOLeadership as connection. True leaders don’t just focus on profits or processes. They bring all perspectives into the room, connect diverse groups, and create conditions for others to thrive.Structural support matters. To avoid symbolic gestures, organizations must embed inclusivity into their leadership practices and accountability systems.Competitiveness through inclusion. By embracing diversity and inclusion, Europe can future-proof its semiconductor workforce, strengthening innovation capacity and securing its position in an increasingly competitive global market.Looking AheadThe Inclusive Chips Forum underscored a powerful message: embedding inclusion into leadership is not optional, it is essential for the sustainable success of Europe’s semiconductor industry.As participants engaged in lively discussions and networking throughout the day, one thing became clear: building a resilient, innovative, and inclusive semiconductor ecosystem will require collaborative effort, courageous leadership, and a commitment to turning awareness into action.A heartfelt thank you to all speakers, participants, and partners who made this event possible.For more information, contact Ana Isabel Billingslea at [email protected] or Kartikey Srivastava at [email protected] Isabel Billingslea is Communications Coordinator at SEMI Europe.

The SEMI Semiconductor Manufacturing Cybersecurity Consortium (SMCC) Work Group 3 (Supply Chain Cybersecurity) just released a major work product that will have a significant and lasting positive impact on the industry: the “Standardized Semiconductor Cyber Assessment (SSCA)” questionnaire. Creating a common security assessment process for device makers, equipment suppliers, software suppliers and other members of the global manufacturing value chain has been one of the principal focus areas for the SMCC from its outset. Its aim is to replace the plethora of company-specific questionnaires that are maintained, distributed, filled out, evaluated, and discussed. Given the breadth and importance of this objective, the work group involved expert stakeholders from across the globe, and the quality of their collective efforts reflects the robustness of this approach.This first-of-its-kind resource helps companies:Evaluate cyber readiness and reduce supply chain riskStreamline compliance with one standardized assessmentBuild trust and share results across multiple clientsAlign with NIST CSF 2.0 and industry best practicesHow is the SSCA structured?The questionnaire takes its basic structure from the Capability Maturity Model Integration (CMMI) framework, which is designed to improve and integrate processes across multiple disciplines, such as software development, system engineering, system testing, and even people management. It defines five distinct maturity levels for the relevant parts of an organization or aspects of a major topic (see figure below) with general explanations of what it means to be at a particular level.Source: WikipediaWorkgroup 3 tailored this model to the unique cybersecurity challenges faced by the semiconductor manufacturing supply chain, identifying six activity areas inspired by the NIST Cybersecurity Framework 2.0—Govern, Identify, Protect, Detect, Respond, and Recover. Within each area, there are specific descriptions of the attributes an organization must exhibit to be at a certain level.What does the SSCA include?The SSCA is delivered in multi-tab spreadsheet form with a tab of instructions and a tab of questions. Some of the questions are multiple choice (“Which CMMI maturity level are you, based on the attributes listed?”) and many are Yes/No (“Does the organization use secure technologies to share sensitive data with suppliers?”). In total, there are 165 questions across the six activity areas.The latter is already offered in five languages: English, Korean, Traditional and Simplified Chinese, and Japanese.How can I get the SSCA?Click here and fill out the form to download the SSCA.“Remembrance of Things Past” or has this ever been done before?No… and sort of.Those of you who remember the state of the semiconductor manufacturing industry in the early 90s will recall that one of the biggest problem areas was the poor and inconsistent quality of the embedded equipment control and communication interface software. SEMATECH and its member companies saw this as an ideal pre-competitive domain for the consortium’s focus, so the Manufacturing Systems Division evaluated best practices in the software engineering community of that era and selected the Capability Maturity Model (CMM) of Carnegie-Mellon’s Software Engineering Institute. Sound familiar?While wholly adopting the CMM at that time was beyond the reach of most equipment suppliers, the nugget that emerged was the decision to standardize on a set of “4-Up” charts that conveyed the most basic of software quality metrics. This got everyone using the same vocabulary, definitions, and visualization techniques to compare progress across process areas and timeframes, which was instrumental in identifying and addressing the root causes of the software issues. An example of a typical software quality “4-Up” chart appears below.Source: Techno-pmAnd in related news!Given the WG 1,2 recent (mid-July) release of the SEMI E187 Compliance Guidance document and the formation of the new South Korea Cybersecurity Work Group (WG9), the SMCC is poised to realize its vision of accelerating the adoption of SEMI Cybersecurity standards while creating vital complementary material.For more information or to participate in the cybersecurity working groups at SEMI SMCC, please contact Mayura Padmanabhan at [email protected] Weber is the VP, New Product Innovations at PDF Solutions and a long-time SEMI Standards participant, currently co-leader of the Equipment Data Publication Task Force and Computer and Device Security Task Force.

On October 03, 2025, as part of the European Chips Diversity Alliance, the recent "Why Inclusion Fuels Better Chips" panel discussion, hosted by Kartikey Srivastava, Senior Specialist, Communications at SEMI Europe, brought together three leaders from across the ecosystem to explore how inclusion is not just a social imperative but a strategic advantage.Martina Wolfgruber, Head of Talent Skills Funding at Infineon Technologies Austria: With over 15 years of experience in HR, Wolfgruber is responsible for funded projects aimed at promoting careers and cultivating talent within the microelectronics industry.Catherine Le Lan de Franssu at Synopsys: Le Lan de Franssu brings a wealth of experience in customer success management, training, and team management from her time at companies like LSI-Logic, Synopsys, and Texas Instruments. She now focuses on fostering collaborations for workforce development.Dr. Suzanne Lesecq, Research Director and European Programs Manager at CEA- Leti: A research director and former university professor, Dr. Lesecq focuses on data fusion and advanced control. She currently manages European programs at CEA-Leti/DSYS.The semiconductor industry is the backbone of Europe's digital transformation, but achieving excellence goes beyond technology alone. It's about bringing every perspective and every talent to the table.Inclusion as a Strategic ImperativeThe panelists all agreed that a commitment to diversity, equity, and inclusion (DEI) is essential for Europe to lead in the semiconductor sector. Wolfgruber posed a compelling question: can Europe truly afford to leave half of its talent pool untapped? She pointed to data from a Boston Consulting Group study showing that companies with diverse leadership are nearly 40% more likely to achieve above-average profitability, and diverse teams are almost twice as likely to be innovative. For Infineon, she noted, "inclusion is not just a value... it's a strategic advantage."Echoing this sentiment, Le Lan de Franssu emphasized that innovation depends on collaboration across institutions, disciplines, regions, and cultures. She believes that "breakthrough moments happen when talented people of every background feel valued, supported to their best self at work." Dr. Lesecq added that inclusion is "a matter of society" that goes beyond a single company's benefit.Fostering a Culture of InclusionThe conversation then moved to practical steps for building a truly inclusive environment. Dr. Lesecq, coming from the academic sector, highlighted the significant gender imbalance and the lack of inclusion for people with special needs. She stressed the need for a major effort to attract untapped talent to the emerging semiconductor domain.One effective solution discussed was mentoring. Le Lan de Franssu shared how a mentoring program can help make diverse talent more visible. She noted that companies working together, such as the collaboration between Synopsys and Infineon on a summer school, helps not only with their own hiring needs but for the broader semiconductor industry. Wolfgruber agreed, stating that a wide range of communities already exists to help companies widen their scope and influence culture; it's simply a matter of companies leveraging them.The Future of a Diverse EcosystemThe panel concluded with a shared vision for the future. The moderator, Srivastava, summarized the key takeaways: a need for greater collaboration between industry and academia, the importance of mentoring, and a continued focus on leveraging research that proves diverse teams produce the best results.Dr. Lesecq shared her hope that Europe will continue to keep this mindset and implement it, seeing inclusion as a societal change that everyone must push for to create a "place for everyone."This panel discussion, along with initiatives like the Spark Excellence Award, serves as a powerful reminder that while technology is at the heart of the semiconductor industry, its true strength lies in the diversity of its people.Learn more about the European Chips Diversity Alliance. For more information, contact Ana Isabel Billingslea at [email protected] or Kartikey Srivastava at [email protected] Isabel Billingslea is Communications Coordinator at SEMI Europe.

As the global economy increasingly prioritizes sustainability and climate action, corporate renewable energy procurement has emerged as a critical tool worldwide. To achieve their corporate sustainability goals, businesses have sought to secure renewable energy through Corporate Power Purchase Agreements (CPPA) with renewable energy developers. Overview of System Charges: Their Role and Impact on Corporate Renewable Energy ProcurementCPPAs are one of the common approaches for businesses to procure renewable energy directly from renewable energy developers. Physical CPPAs involve two major cost components – energy costs and system charges. In this blog, we focus on system charges which are fees collected by utilities that include transmission and balancing components. Transmission charges cover the use of grid infrastructure to deliver electricity, while balancing charges cover the cost of maintaining real-time supply-demand stability.Although system charges are a key cost component in physical CPPAs, they are typically not the primary cost drivers. Based on Wood Mackenzie’s cost estimate analysis for a 50-100MW solar CPPA across the various regulated and liberalized APAC markets of Malaysia, Thailand, Australia, Philippines, South Korea, Singapore, Japan and Taiwan, system charges typically make up less than 20% of the total CPPA price. However, this share of system charges in the total CPPA price varies considerably between APAC markets. Australia, the Philippines and South Korea maintain system charges at between 10% - 20% of their solar CPPA prices. Singapore, Japan and Taiwan see the lowest proportion of system charges of solar CPPA prices at 7%, 6% and 5% respectively.Malaysia's Moment: Optimizing SAC for CRESS SuccessAnnounced in July 2024, CRESS allows for physical CPPAs from renewable energy projects of 30 MW and above. While CRESS opens new avenues for businesses to access renewable energy, the implementation of the System Access Charge (SAC), a surcharge imposed on renewable developers for using the Malaysian Grid under CRESS, has raised cost concerns within the industry.Based on Wood Mackenzie’s analysis, Malaysia's SAC account for about 60% of the estimated total CPPA price in Peninsular Malaysia, assuming a solar production cost at USD57/MWh (based on the average of the large scale solar LLS3 LLS4 - bid price range of MYR 0.19-0.28/MWh. The SAC significantly impacts the overall cost structure of renewable energy procurement. Malaysia’s SAC for solar “non-firm supply” under CRESS is currently set at 40sen/kWh or about USD/MWh making them the highest system charges applicable to CPPAs in the region.Another concern relates to cost-transparency and ease of long-term cost forecast for buyers. Most APAC markets demonstrate high transparency in their methodologies for determining system charges. Countries like Australia and Japan provide clear breakdowns of cost components, including grid capital expenditure, operation expenditure, power losses, ancillary services, and market operation costs. Even after analyzing other regulated markets like Thailand (where wheeling and balancing charges are based on UGT 2 tariff rates), Taiwan and South Korea, Malaysia’s SAC lacks transparency in its the system charges determination methodology, compared to three other vertically integrated Single Buyer markets like Peninsular Malaysia. Such cost transparency, including detailed cost components and calculation methodology, is crucial for corporate energy buyers looking to increase predictability of electricity costs by entering long-term CPPAs. The high SAC charge poses a significant barrier to the adoption of renewable energy by industrial end-users like semiconductor manufacturers and makes it challenging for prospective CRESS buyers to understand how these charges may evolve over a 21-year contract period. The SAC under CRESS would be reviewed every 3 years and is subjected to a maximum variation of 15% from the prevailing charge.RecommendationsThe lack of transparency of the SAC could jeopardize Malaysia’s critical development objectives, such as attracting MYR500 billion (USD $110 billion) in semiconductor investments by 2030 under its National Semiconductor Strategy (NSS), or its 40% renewable installed capacity target by 2035 (or about 18 GW by 2035). To address these challenges and create a more favourable environment for both semiconductor investments and renewable energy adoption, SEMI and Wood Mackenzie propose the following recommendations:Benchmarking SAC against transparent and established system charge components: Additional transparency would allow Malaysia to align with practices in both regulated and liberalized markets across the APAC region and allow more players to make long-term investments in Malaysia. Similar cost methodologies to the regulated tariff could be adopted. As an initial step, SAC should reflect Network Charges defined under the regulated tariff, and as a best practice, any differences between the SAC and the Network Charges in the regulated tariff should be clearly explained and justified (e.g. additional balancing costs induced by solar procured under the CRESS may be audited with the Single Buyer).Improving CRESS SAC stability and predictability: Ensuring transparency on the calculation methods behind SAC and its components, and predictable SAC levels, will allow businesses to proactively anticipate and plan for renewable energy procurement expenses, enabling informed decisions and on long-term corporate solar PPAs spanning 20 years’ time horizon under the CRESS framework. In particular, the maximum change in SAC charges can be narrowed down from 15% every three years.4Alignment of national sustainable energy policies: Strengthening policy support and ensuring accessible financing are essential to driving the widespread adoption of renewable energy. CRESS can only succeed if the scheme enables fair, transparent, and competitive access to clean energy. New renewable energy coming online via CRESS should not be put at an economic disadvantage through differentiated system charges from those applicable to other clean energy schemes. For example, no SACs are applied to solar under Large Scale Solar (LSS) projects, despite their system impacts being the same as under CRESS. Sustained efforts to improve affordability within CRESS are crucial for attracting investment, reducing the cost of SAC for buyers, and accelerating Malaysia’s transition to a sustainable, low-carbon future.The Path Forward and ConclusionImproving transparency and stability of SAC is crucial for facilitating Malaysia's development goals in semiconductor investments and renewable energy targets. By implementing these recommendations, Malaysia can enhance its competitiveness in attracting sustainable investments and accelerate its transition to clean energy.As the voice of the global electronics manufacturing and design supply chain, SEMI is committed to working with policymakers, industry leaders, and stakeholders to address these challenges. SEMI and Wood Mackenzie believe that by fostering a more transparent and competitive environment for renewable energy procurement, Malaysia can unlock the full potential of the country’s semiconductor industry while contributing to a more sustainable future.SoYoung Jang manages the SEMI Energy Collaborative programs at SEMI.Antoine Gaudin and Chun Kang Eu are from Wood Mackenzie.

SEMICON West in Phoenix, Arizona, will bring together all of the SEMI Sustainability efforts and programs under one roof over three days. With back-to-back sessions from October 7-9, this year’s Sustainability EHS Program will offer expert insights on the most pressing sustainability topics facing the microelectronics industry. Tuesday will kick off the program and focus on the business aspects of driving to sustainability in the semiconductor sector. On Wednesday, the Pavilion hosts discussions on water risk, water management, circular economy solutions and the needs for innovation from startups. Finally, Thursday will highlight the current emissions landscape, milestones and achievements, and solutions developed by the SEMI Semiconductor Climate Consortium (SCC). The 2025 event also marks the first public discussions of the full scope, findings and status of the SCC’s direction.All three days of the Sustainability EHS Program are sponsored by Edwards, Schneider Electric, TEL, SCREEN, Sundt and the Greater Sacramento Economic Council. Here’s a sneak peek at what the 2025 program has to offer. Registration for SEMICON West is open.The Business of Sustainability – Tuesday, October 7 Sustainability Panel: Path to Success Sustainability hits the keynote stage with Tuesday afternoon with a panel discussion detailing a plan for meaningful sustainability progress. The panel, titled Sustainability Panel: Path to Success—The Semiconductor Industry Leads the Way for a Resilient Future, will take place on the CEO Summit Keynote Stage from 2:35-3:35 p.m. Experts from Applied Materials, BASF, Micron, Google, and Qualcomm will cover strategies on how collaboration, supplier engagement, and clean technology investments are reducing emissions and propelling the industry closer to its sustainability goals. Attendees will discover what’s working, what’s still to come, and how the industry will forge its way toward a more sustainable future.A Musical Performance by Ay YoungIn anticipation of the Path to Success panel discussion, Tuesday will also spotlight an exciting musical guest. AY Young is a singer, songwriter, and the founder of the longest-running clean energy concert series in the U.S. At 2:20 p.m., he’ll take to the CEO Summit Keynote Stage for a memorable performance and give a glimpse into how important sustainability has become to attract a new generation of talent. Through his musical talent and deep commitment to clean energy, Young was appointed as a United Nations (UN) Young World Leader in 2020, helping the organization further its 17 Sustainable Development Goals. His Project17 initiative is a 17-song album, with each song centering on a different goal and backed by a corporate sponsor that aligns with it. Young will also attend the Sustainability Reception from 5-6:30 p.m. at the Sustainability Pavilion Theater.EHS Regulatory OverviewThe wide range of regulatory topics will be showcased in the first session on Tuesday at the Sustainability Pavilion. Expert speakers and advocacy groups will deliver key insights on the threats and challenges, and the research and collaboration opportunities currently at play in the regulatory environment, with special focus on keeping electronics manufacturing strong. Climate Equity Social Impact Workgroup (CESI) Aligning with the theme of the UN Sustainable Development Goals, the SEMI Climate Equity Social Impact (CESI) Working Group will highlight how its members are progressing real-world outcomes for climate, education, and global cooperation. This session will run from 3-4 p.m. at the Sustainability Pavilion Stage, and it’s ideal for anyone in the industry who’s passionate about sustainable partnerships. Innovations Enabling Reduce, Reuse, Repurpose and Recover – Wednesday, October 8Resource Use and Circular EconomyWednesday’s 10:15-11:30 a.m. session, Resource Use and Circular Economy will offer tactical solutions to help fabs reach up to 80-90% circularity. The goal of this session is to lay a foundation for transforming the industry’s circularity concerns into practical opportunities, which will be achieved over two panel discussions. Discussion 1, A Circular Value Chain: Challenges and Leading-Edge Solutions, will highlight solutions for eliminating waste and reducing manufacturing costs through circular technologies. This panel will feature experts from Edwards, Syensqo, and ElectraMet and will be moderated by Subgeni’s Taimur Burki. These subject matter experts will highlight their company solutions, but also other areas they see in need of consideration from a circularity lens, as well as best known practices across fabs. Water is a precious resource, and how the industry manages it is crucial for its long-term success. Discussion 2, Tactical Maturity Scales for Water Management, will unveil two new guides developed by SEMI’s Water Management Working Group. Both products are designed to move manufacturers from both large and small fabs and manufacturing operations to assess their water needs and most efficiently improve water reuse by up to 80%. This panel will be led by speakers from Aquatech, SCREEN, Sundt, Ovivo, and C2MI. Water Resilience Starting at 11:30 a.m. at the Sustainability Pavilion Stage, attendees will hear from the SEMI Environmental Risk Mitigation and Reporting Working Group lead - Senior Sustainable Program Manager – Alua Suleimenova – as she shares her insights and findings from a recently completed study by WaterPlan on industry water risks within the semiconductor value chain. The topic and findings will then be addressed by a panel, where Suleimenova will engage leaders from ASM, Waterplan, ERM, and the Alliance for Water Stewardship, in a conversation about water, nature, and associated corporate risks. Although companies are making strides to protect water access, it’s becoming clear that a focus on internal activities will not move the needle significantly enough for achieving long-term resilience. This panel will offer solutions for adapting water-related risks to the supply chain, with a focus on North America, Asia Pacific, and Europe.Other Wednesday AttractionsSEMI S3 – Startups for Sustainable Semiconductors: SEMI S3, or Startups for Sustainable Semiconductors, is an annual program by the industry’s venture capital divisions designed to boost awareness of semiconductor industry needs by inviting promising startups to be mentored and pitch their solutions to our industry. Earlier this year, 145 candidates submitted applications. Now, it’s down to 15 finalists, who will present at SEMICON West from 2-4:40 p.m. at the Sustainability Pavilion, following a Fireside Chat from experienced innovation experts from 1-2pm.Accelerating Sustainability with Smart Manufacturing – Presentations Poster Session: Technical papers and posters focused on sustainability solutions – from water to energy – will also be presented in the Smart Manufacturing Pavilion from 2-5:15 p.m., providing an opportunity to network with industry leaders and discover the latest best practices for how machine learning and AI can reduce water and waste in fabs.Reducing Emissions – Thursday, October 9SCC – Tackling Emissions Across the IndustryExpect a full-house at Thursday’s all-day session featuring SCC – Tackling Emissions Across the Industry. From 10:15 a.m. to 3:00 p.m., the SEMI SCC leaders and experts will detail its findings and projects addressing the industry’s emissions. SCC has been focusing on ensuring consistent and measurable progress in decarbonizing from 2021 levels. Key topics include: Reporting and aligningBaseline, ambition, and roadmapAbatementLow Global Warming Potential (GWP) gases workLow Carbon Economy (LCE) access and procurementEnergy efficienciesScope 3 upstreamSEMICON West also features SEMI U courses to learn more about sustainability in our industry. For example, on Thursday, SEMI U: PFAS Compounds in Semiconductor Environment, is being offered from 8 a.m. to noon. This course is available for purchase. Support the SEMI Forest community effort to reforest our planet by funding a range of certified carbon avoidance and tree planting projects. Our goal for SEMICON West is to fund planting for 100,000 trees. Scan the QR code below to contribute and help us meet our goal.Learn more about the 2025 SEMICON West Sustainability EHS Program. Follow SEMI Sustainability on LinkedIn for regular updates on sustainability initiatives. Saifi Usmani is Vice President for Sustainability at SEMI.

The SEMI Startups for Sustainable Semiconductors (S3) program announced 15 startups chosen as finalists for pitching to the industry at SEMICON West 2025 in Phoenix, Arizona. The finalists were chosen from a field of 35 semifinalists after a virtual pitch event over 2 days. Startups were evaluated by the organizing committee on five factors: the sustainability impact on our industry, commercial viability of product, company value proposition, the quality of the pitch and the startup team.The committee, made up of experienced Corporate Venture Capitalists (CVCs) from the global semiconductor industry, initially received 145 submissions in all three categories identified for 2025:Sustainable Semiconductor ManufacturingSustainable Data CenterGen AI for Sustainable DesignNow in its 4th year, the program features strong exposure to semiconductor industry CVCs, through the personal mentoring each startup receives. Mentoring topics are tailored to align with the needs and strategic positioning of the startup business plan, and can range from basic introduction to semiconductor manufacturing, to connections to new funding sources. A full analysis of the program over the past 3 years is available here.The SEMI Startups for Sustainability Semiconductor pitch event will take place at the Sustainability Pavilion Stage on Wednesday, October 8 starting at 1:00 p.m. Program lead John Wei of Applied Ventures will open the session and introduce a fireside chat featuring Dr. Om Nalamasu, CTO of Applied Materials and Chair of Applied Ventures and Dr. Melissa Grupen-Shemansky, CTO of SEMI, and moderated by Saifi Usmani, SEMI Vice President of Sustainability. These executives will discuss the role of startups in semiconductor sustainability, along with a variety of related topics. The finalist pitches are scheduled from 2:00 to 4:40 p.m., with each presenter given a 10-minute time slot.Investors are welcome to attend the session at SEMICON West and to register their interest here to learn more about the 2026 program.2025 S3 FinalistsActasys Inc.Brooklyn, NY, USA Actasys has developed a precision cooling solution designed for thermal bottlenecks in semiconductor-driven systems such as networking cards (NICs), DPUs, switches, and optical transceivers. Instead of cooling entire racks or server rooms ActaJet™ targets localized hotspots at the device level, delivering scalable, high-efficiency airflow through a compact, adaptive, and electronically controlled actuator system. AlixLabs ABLund, Sweden AlixLabs AB is developing a disruptive semiconductor manufacturing technology based on Atomic Layer Pitch Splitting (APS). It enables cost-effective and environmentally sustainable scaling of transistor architectures by doubling pattern density without requiring advanced lithography. The core product includes both the APS process and customized etching equipment that integrates into existing semiconductor fab workflows, reducing complexity, cost, and environmental impact.AllonniaBoston, MA, USA Allonnia delivers on-site PFAS treatment with SAFF® (Surface Active Foam Fractionation), a modular system that uses air to naturally separate long- and short-chain PFAS from water. SAFF concentrates PFAS up to 100,000x, minimizing waste and enabling cost-effective, closed-loop management alongside any destruction technology. This plug-and-play solution helps fabs meet strict regulations while advancing sustainability goals with low OPEX and seamless integration into existing operations.AlsemySeoul, South Korea Alsemy is building an AI-powered platform that bridges Manufacturing Execution Systems (MES) and EDA domains enabling fabless engineers to reflect manufacturing data characteristics in their chip designs, while process engineers can make data-driven decisions to optimize manufacturing processes for maximum chip performance. By connecting these traditionally siloed areas, a feedback loop is created to drive efficiency and innovation across the semiconductor value chain.Arieca IncPittsburgh, PA, USA Arieca's adaptable Liquid Metal Embedded Elastomer (LMEE) technology, which blends liquid metal and polymer, delivers both thermal performance and mechanical reliability. LMEEs are a cost-effective, dispensable emulsion that is compatible with existing high volume manufacturing tools and allows for low pressure spreading and excellent wetting. CuspAICambridge, UK CuspAI is building an engine that combines Gen AI models, virtual twins, and active learning pipelines for simulation to develop sustainable materials solutions that address critical environmental challenges, including, environmentally-friendly etching reagents, specialized sorbents for emissions capture, and novel catalysts for manufacturing waste remediation. The engine has already proven successful in designing metal-organic frameworks (MOFs) for carbon capture and PFAS removal from water.FlexiramicsEnshede, The Netherlands Flexiramics® is a breakthrough flexible, 100% ceramic fiber material designed as a drop-in replacement for glass fiber in PCBs. By enhancing thermal conductivity and reducing signal loss, it enables semiconductor manufacturers to build faster, cooler, and more reliable devices. This translates into higher performance, longer lifetimes, and greater efficiency for next-generation chips and advanced electronic systems.icspiKitchener, ON, Canada icspi has developed the microAFM, a scalable atomic force microscope (AFM) on a 1 mm^2 MEMS scan head, 1,000,000x smaller than conventional AFMs. MicroAFM technology enables parallel arrays of thousands of devices for sub-nanometer metrology and inspection with unprecedented throughput, accelerating time-to-yield and reducing scrap.Mixx Technologies, Inc.San Jose, CA, USA Mixx Technologies is a deep-tech startup building next-generation optical interconnect solutions to deliver non-blocking, energy-efficient data movement. The advanced 3DS platform enables petabit level end-to-end connectivity for AI workloads resulting in sustainable, efficient, and cost-effective scaling. The 3DS platform comprised of the engine, package and system, enables seamless deployment of the optical IO chiplet.Point2 TechnologySan Jose, CA, USA Point2 designs and manufactures mixed-signal interconnect SoCs for terabit data transmission, to overcome the barriers of copper and optical cabling to accelerate AI interconnect in GPU cluster scale-up. e-Tube technology uses an RF Transmitter SoC to convert data from the electrical to the RF domain for transmission over plastic waveguides, with the RF Receiver SoC converting the data from the RF domain back to the electrical domain.PROUDLausanne, Switzerland PROUD's patented diamond-layer technology with the highest heat dissipation capacity ( 1000 W/m.K) of any existing material, deposited on chips, allows a direct upgrade in heat extraction, power output and efficiency.SKYRE, Inc.East Hartford, MA, USA SKYRE, Inc. is a pioneer in hydrogen technology, developing innovative solutions to support a clean energy future. From hydrogen recycling, purification and compression, to sustainable energy systems, we deliver environmentally responsible innovations in high-efficiency, zero-waste hydrogen and carbon transformation technologies—cutting costs, boosting industrial productivity, and reducing environmental impact.SyentaSydney, Australia Syenta has developed LEM - Localized Electrochemical Modelling - a process for depositing metal patterns using a local electrochemical process. The pattern is created on a stamp, which then prints the pattern on the substrate in an additive process.Vionano Innovations IncSt. Paul, MN, USA VioNano Innovations is building a patterning platform to enable advanced feature scaling using self-assembling polymer brush materials. The system enables polymers over 193 nm DUV lithography patterns to double feature density without requiring ALD/CVD or etch steps. The result is a low-energy, high-resolution process for sub-20 nm features using existing infrastructure.XLYNX MaterialsVictoria, BC, Canada XLYNX designs and manufactures a revolutionary family of polymer crosslinkers. These reagents are uniquely able to cure virtually ANY aliphatic polymer, by harnessing high-yielding insertions to carbon-hydrogen bonds. Curing can be triggered thermally (at temperatures as low as 80°C) or photochemically (using either UV or blue light). Heidi Hoffman is Senior Director, Marketing Sustainability at SEMI. Saifi Usmani is VP, Global Industry Sustainability Programs at SEMI.

The semiconductor industry faces an unprecedented paradox: AI demand is booming, fab investments are rising, yet wafer shipments remain stubbornly flat. What's driving this disconnect, and when will it break?As of mid-2025, the global silicon wafer market appears calm on the surface, but underlying structural tensions are quietly mounting. The demand for AI semiconductors remains resilient, and certain high-value supply chains continue to operate near capacity. Yet wafer shipments have shown little sign of meaningful recovery—a divergence that raises questions about the conventional supply-demand playbook.SEMI's latest Silicon Wafer Market Monitor Report begins with a structural hypothesis: that the current market dynamics cannot be explained solely by weak demand or delayed orders. Instead, we propose that the demand pattern of fab operations itself has fundamentally changed.The Hidden Constraint: Time ExtensionOne critical metric has emerged as a structural bottleneck—fab cycle time, or the average duration for a wafer to complete its full process flow. Our quantitative analysis reveals that since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained.Why is this happening? Rising process complexity, increased equipment density, and tighter quality control requirements are absorbing more capital per wafer while paradoxically slowing production. Equipment spending per wafer area has surged over 150% since 2020, yet this investment translates into longer processing times rather than higher throughput.The High Bandwidth Memory (HBM) Economic ThresholdSimultaneously, the market is approaching a new inflection point driven by the rapid rise of HBM. HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand. However, HBM currently accounts for just 16% of total memory revenue—still below a critical economic threshold.Our analysis identifies that when HBM reaches 25% of total memory revenue, the trade ratio rises to 1.5. This is the structural breakeven point where CapEx per wafer for HBM-dedicated lines aligns with standard DRAM economics. At this threshold, memory makers gain clear incentives to expand wafer input, and customers become more willing to pay premium prices.The Quantitative FrameworkInstead of relying on conventional forecasts, we model the interaction of four critical variables—HBM penetration, DRAM bit growth, fab utilization, and cycle time—using a quantitative simulation framework. Under current conditions (16% HBM revenue share, 15% annual bit growth, 95% fab utilization, and 14.8% cycle time increase), wafer input would need to increase by 23.9% annually to meet projected demand.Yet no fab is scaling wafer input to that extent today. This suggests the market isn't demand-constrained but operating within a conditionally responsive system—one that won't activate until key thresholds align.Beyond Economics: Technical and Operational ReadinessThe slow pace of HBM expansion isn't solely about investment timing. Technical constraints including low yields, delayed customer qualification, and process stabilization challenges also play critical roles. These preconditions—investment readiness, yield optimization, and qualification completion—haven't yet aligned, keeping the market in strategic latency despite robust underlying demand.Additional factors compound this delay. Backend bottlenecks in Chip-on-Wafer-on-Substrate (CoWoS) packaging are causing semi-finished wafers to accumulate as inventory, constraining upstream wafer input. At the fab level, companies prioritize efficiency gains through process conversions over new construction. Meanwhile, macroeconomic uncertainty, geopolitical tensions, and foreign exchange volatility continue suppressing capital execution.The Three-Tier Response ModelThis structural shift creates a three-tier demand response across the supply chain:Wafer demand: Conditionally responsive, awaiting economic threshold alignmentEquipment investment: Process-transition driven, already responding to complexity increasesMaterials demand: Directly tied to cycle time extensions, with potential for early bottlenecksFor certain process-critical materials like EUV photoresists and TSV chemicals, supply constraints may emerge even before wafer input fully ramps, preceding equipment expansion.Strategic ImplicationsFor industry stakeholders, this analysis suggests three key actions: wafer suppliers should prepare scenario-based capacity plans around the 25% HBM threshold; equipment makers should anticipate process-transition driven demand regardless of current wafer volumes; and materials suppliers should prepare for potential bottlenecks as extended cycle times increase consumption per wafer.Crucially, the current stagnation shouldn't be interpreted as structural decline. Rather, the market exists in a state of strategic readiness, with key conditions not yet aligned. Once they are, wafer demand will likely respond nonlinearly—and momentum is already building in that direction.The structural inflection point (≈25% HBM penetration) and cycle time increase (+14.8%) serve as forward-looking indicators not just for wafer producers, but for the entire upstream supply chain. The question isn't whether this inflection will occur, but when. Companies that understand these structural dynamics and prepare accordingly will be best positioned to capitalize on the nonlinear demand response when it arrives.These key insights are from the market update section of the Q2 2025 Silicon Wafer Market Monitor Report. This quarter's analysis models structural inflection points using scenario-based projections across nine core charts and tables, offering data-driven perspective on the industry's readiness for the next demand shift. Download your free sample report today.For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on the complete SEMI market data portfolio are available at our Market Intelligence website. Sungho Yoon is a Principal Analyst in the Silicon Wafer Market Research at SEMI Market Intelligence.

The semiconductor industry is grappling with a critical talent shortage, both globally and within the United States. At the same time, the workplace landscape for high school and college graduates is changing. These dual pressures present an opportunity: to cultivate early career awareness by introducing K–12 students to dynamic, real-world learning experiences that open their eyes to emerging industries—like semiconductors—and the meaningful roles they could play in them.Investing in this early exposure strengthens the long-term talent pipeline for the semiconductor industry and prepares students to meet the demands of a rapidly evolving workforce. However, realizing this vision requires intentional, cross-sector collaboration among educators, industry leaders, workforce boards, and policymakers.One example of this type of collaboration is the ChipWorks Series in Idaho. Boise State University partnered with Micron, the Idaho Workforce Development Council, and the Idaho Digital Learning Alliance to design, develop, and launch the learning experience for middle and high school students in 2024. The ChipWorks Series consists of three courses: Chip, Chip, Hooray!; Introduction to Electrical and Computer Engineering; and Materials Science and Engineering. With the first course launching in Fall 2024, the program has already reached over 220 learners across Idaho – and it’s just getting started. Camille Platts-McPharlin is the Project Manager at the Microelectronics Education and Research Center helping Boise State prepare to expand their programming to a national audience in 2025.The origin of the ChipWorks Series began through a grant with the Idaho Workforce Development Council. “The Council and Boise State University saw an opportunity to address the growing workforce gap by building a pipeline that begins in middle school and goes through adulthood,” said Platts-McPharlin. Development began in 2023 and was shaped by more than 300 voices from industry, academia, and K–12 education. This cross-sector group of stakeholders worked collaboratively to ensure that the lessons were responsive to real-world industry needs and compatible with classroom delivery best practices. Furthermore, the courses are aligned with State and National learning standards as well as ABET standards. Overcoming logistics challenges around open-source resources and existing structures in formal education led to two of the programs being dual credit, setting high school students up for early success in post-secondary. There has been an enthusiastic response from learners across Idaho, and more learners are expected to engage this year, as the third and final course is launched in the fall. Students enroll at their home school, have the support of local teachers, and receive online instruction synchronously from a dedicated teacher through the Idaho Digital Learning Alliance. This model enables a broader group of learners to access the training, regardless of educator understanding of the content. Students learning ChipWorks Series lessons at Micron Chip Camp.The ChipWorks Series is now expanding its reach beyond Idaho. In collaboration with Micron, Platts-McPharlin and the MERC team are working to bring the courses to students in New York. Educators from Syracuse and surrounding districts participated in a week-long professional development event to learn the curriculum and begin the work of bringing it into their local school districts. Teacher training for educators from Idaho and New York. Platts-McPharlin offered words of wisdom for other educators, training providers, or partners who are trying to create industry awareness opportunities earlier in the learning journey. “The key to success is listening closely to stakeholders and balancing the various perspectives. This will result in a quality product,” she said. Her other suggestion: trust the process. While it was challenging to build entirely new programs, the impact it is having on students, their teachers and their families to make them aware of their potential is immense. Programs like ChipWorks offer a powerful solution to the semiconductor industry’s workforce crisis, but they cannot stand alone. For sustained progress, industry leaders, workforce development councils, and educational institutions must work together to co-design scalable, inclusive solutions. This means sharing expertise, investing in infrastructure, and championing long-term talent development—starting in the earliest years of education. For more information on the ChipWorks Series, or to learn how to bring it to your students, please contact Camille Platts-McPharlin: [email protected]. To learn about what the SEMI Foundation is doing to bring together cross-sectoral groups for similar projects, contact Anissa Hamdon-Morison: [email protected] Hamdon-Morison is Training and Curriculum Manager at SEMI Foundation.

“Critical minerals our world needs for electric vehicles and semiconductors can be found here. Clean energy we need to power artificial intelligence data centers and economic growth can be built here.”[1] This statement was made by former US President Joseph Biden during his visit to Angola in December 2024 to support a US-funded railroad project called the Lobito Corridor. The railroad would connect mining areas in the Democratic Republic of Congo (DRC) and Zambia to a port on the western coast of Africa, an important step towards expanding access to critical minerals needed for growth of the semiconductor and energy industry in the west. According to the Intergovernmental Forum on Mining, Minerals, Metals and Sustainable Development (IGF), “there is no universally agreed upon definition of what ‘criticality’ means…criticality is also very country- and context-specific, particularly with respect to mineral endowment, the relative importance of the minerals to industrial and economic development, and a strategic assessment of supply risks and volatility.”[2] In other words, the term “critical mineral” may vary by location, application, and current events. Many countries have generated their own lists of critical minerals to help guide legislation, budgetary allocations and diplomatic efforts. For example, the United States Geological Survey released a list of “50 mineral commodities critical to the US economy and national security” in 2022 which included 10 minerals that were directly linked to semiconductors and electronics.[3] These included arsenic, dysprosium, gallium, lutetium, rhodium, ruthenium, tantalum, terbium, tin, and tungsten. Other lists might include cobalt, copper, and sometimes uranium. For most countries that make chips and electronics, critical minerals are both essential for supporting their industry and also hard to find within their own borders.While downstream electronics and semiconductor manufacturers are often located in countries with robust labor protections, the extraction of raw minerals too often takes place under less humane circumstances. In April 2024, the UN Secretary General launched the Panel on Critical Energy Transition Minerals to address the challenges associated with responsible extraction of critical minerals. One of the motivations for the formation of the panel was the concern about human rights violations related to mineral extraction. “Mining, at all scales, large and small, has too often been linked with human rights abuses, environmental degradation and conflict.”[4] The term “conflict mineral” has a much narrower definition than critical mineral, and usually only refers to tin, tantalum, tungsten and gold, also known as ‘3TG’. This definition is often used in policy frameworks, such as the US Dodd-Frank 1502 Act[5] and the European Union (EU) Regulation 2017/821[6]. These four minerals were identified as a major source of income for armed groups in the DRC, fueling a decades long war that has claimed more than 6 million lives since the start of the Second Congo War in 1996.[7] For example, in May 2024, armed groups from Rwanda captured a town in the Congo with the largest coltan mine in the country, which is the second largest producer in the world of the ore that is refined to make tantalum - a key component of capacitors. The incursion helped to finance the armed group, collecting at least $800,000 per month in taxes.[8] Over the past 15 years, several frameworks have emerged to address the conflicts and tensions stemming from extraction of critical minerals. A common framework within the semiconductor industry was written by the Organization for Cooperation and Development (OECD), which is an intergovernmental economic organization founded in 1948 (then known as OEEC) to “build better policies for better lives.” The organization publishes several guidelines, including the OECD Due Diligence Guidance for Responsible Business Conduct[9] (see suggested measures in Figure 1) and the OECD Due Diligence Guidance for Responsible Supply Chains of Minerals from Conflict-Affected and High-Risk Areas with focuses specifically on 3TG minerals.[10] These guidelines provide a structure through which companies and organizations might address human rights and environmental issues that may arise from their or their suppliers’ operations. Figure 1: Due Diligence Process and Supporting Measures from the OECD Due Diligence Guidance for Responsible Business Conduct (2018)Several regulations have been implemented by governing bodies to prevent financing of armed groups through procurement of conflict minerals. In the United States, Section 1502 of the Dodd-Frank Wall Street Reform and Consumer Protection Act requires certain companies to “publicly disclose their use of conflict minerals that originated in the Democratic Republic of the Congo or an adjoining country.”[11] Also known as the “Disclosure Rule,” a company must file a report to the Securities and Exchange Commission (SEC) describing the source and chain of custody of its conflict minerals, and must also conform to a nationally or internationally recognized due diligence standard such as the OECD guidelines. Similarly, the EU Regulation 2017/821 refers to the OECD Due Diligence Guidelines and calls on companies within the EU to monitor, audit and disclose procurement of conflict minerals. In 2024, the EU furthered its efforts to address human rights and environmental issues by adopting the EU Corporate Sustainability Due Diligence Directive (EU CSDDD). This directive will require all companies that do business within the EU, regardless of country of origin, to monitor their supply chains for labor and environmental violations or risk penalty.Given the tremendous effort by the industry to address the conflict associated with 3TG minerals, it is unclear whether these efforts have had an effect. The U.S. Government Accountability Office (GAO), which serves as the federal government’s watchdog agency and is tasked with providing Congress with independent, nonpartisan information, has been reporting on issues related to conflict minerals in the DRC since 2010. Kimberly Gianopoulos, Managing Director of GAO’s International Affairs and Trade Team, has led this body of work over time, including GAO’s most recent report, which was published in October 2024. Gianopoulos stated that, “although it has been over a decade since the SEC issued its conflict minerals disclosure rule in 2012, GAO’s most recent report found that there is no empirical evidence that the rule has decreased violence in the eastern DRC, where many mines and armed groups are located, and that a majority of companies that conduct due diligence on their mineral supply chains continue to report being unable to determine the origins of minerals used in their products.” The 2024 Conflict Minerals report can be found here: https://www.gao.gov/products/gao-25-107018.Regulatory approaches are only one way in which the semiconductor industry interacts with conflict mineral issues. Many companies and industry associations have implemented their own initiatives and formed associations to share resources to trace materials and collect supplier information. One such industry association is the Responsible Business Alliance’s Responsible Minerals Initiative (RMI). Jennifer Peyser, the executive director of the RMI, stated that the initiative “supports over 500 downstream, midstream, and upstream member companies with a suite of due diligence standards and tools, data, guidance, training, and other resources for global responsible sourcing and regulatory compliance. Our facility and supply chain due diligence standards are rooted in longstanding international norms while reflecting emerging corporate and stakeholder priorities for regulatory compliance, managing sustainability risks and impacts, and fostering responsible mineral supply chains.” More information about the RMI can be found here: www.responsiblemineralsinitiative.org.Recently, SEMI has formed a new Responsible Supply Chain (RSC) working group under its Supply Chain Management initiative to provide a platform for enabling traceability and provenance across the supply chain to meet government regulations on conflict minerals and unfair labor practices. This new working group aims to bring together SEMI member companies to raise awareness of key issues, share resources, and advocate effective regulations and standards. The working group is comprised of SEMI member company employees from a wide range of backgrounds, including sustainability managers, supply chain experts and process engineers. If you are interested in joining our discussions, please visit our website for more information: https://www.semi.org/en/industry-groups/supply-chain-management. On July 9 at 8am Pacific/11am Eastern, the SEMI Responsible Supply Chain working group will host a webinar featuring a roundtable discussion with Jennifer Peyser, Executive Director of the Responsible Business Alliance’s Responsible Minerals Initiative, and Kimberly Gianopoulos, Managing Director of the International Affairs and Trade Team at the US Government Accountability Office, including Q A for attendees to join the discussion. Visit https://www.semi.org/en/event/critical-minerals-due-diligence-and-semiconductor-supply-chain to register.Other upcoming events include a panel discussion at SEMICON West, October 7-9, 2025 in Phoenix, Arizona!Author Bio:Dr. Kimberly Harrison Ph.D is a Senior MEMS Designer with AMFitzgerald Associates, a design firm located in the Bay Area California. She has a doctoral degree in mechanical engineering from Stanford University, and has worked as a designer and process engineer in the semiconductor industry for 10 years. She was nominated as a 2022 MEMS Sensors Industry Group Emerging Leader. As a founding member and leader of the SEMI Responsible Supply Chain Working Group, she hopes to bring SEMI members together to discuss solutions to human rights issues in the semiconductor supply chain.References:[1] Remarks by President Biden Participating in the Lobito Corridor Trans-Africa Summit in Benguela, Angola (December 4, 2024). https://bidenwhitehouse.archives.gov/briefing-room/speeches-remarks/2024/12/04/remarks-by-president-biden-participating-in-the-lobito-corridor-trans-africa-summit-benguela-angola/[2] Critical Minerals: A Primer (November 1, 2022). https://www.igfmining.org/resource/critical-minerals-primer/[3] https://www.usgs.gov/news/national-news-release/us-geological-survey-releases-2022-list-critical-minerals[4] Resourcing the Energy Transition: Principles to Guide Critical Energy Transition Minerals Towards Equity and Justice (April 11, 2024). https://www.un.org/en/climatechange/critical-minerals[5] https://www.sec.gov/resources-small-businesses/small-business-compliance-guides/conflict-minerals-disclosure[6] https://eur-lex.europa.eu/eli/reg/2017/821/oj/eng[7] Conflict in the Democratic Republic of Congo (March 20, 2025). https://www.cfr.org/global-conflict-tracker/conflict/violence-democratic-republic-congo[8] The Evidence that Shows Rwanda is Backing Rebels in DR Congo (January 29, 2025) https://www.bbc.com/news/articles/ckgyzl1mlkvo[9] OECD Due Diligence Guidance for Responsible Business Conduct (February 1, 2018). https://www.oecd.org/en/publications/oecd-due-diligence-guidance-for-responsible-business-conduct_15f5f4b3-en.html[10] OECD Due Diligence Guidance for Responsible Supply Chains of Minerals from Conflict-Affected and High-Risk Areas, 3rd edition (April 6, 2016). https://www.oecd.org/en/publications/oecd-due-diligence-guidance-for-responsible-supply-chains-of-minerals-from-conflict-affected-and-high-risk-areas_9789264252479-en.html[11] https://www.sec.gov/resources-small-businesses/small-business-compliance-guides/conflict-minerals-disclosure