Yield Engineering Systems, Inc. (YES), a leading manufacturer of process equipment for semiconductor advanced packaging, life sciences, and “More-than-Moore” applications, today announced that it has promoted Dan O’Connell to Vice President of Strategic Accounts.

Mr. O’Connell joined YES in November of 2021 as Senior Director of Key Account Management. In his newly expanded role, he will work closely with the company’s Sales, Marketing and Technology teams to nurture strategic customer relationships and ensure YES’s alignment with current and future customer technology requirements.

“Dan’s extensive strategic account experience in the semiconductor industry has contributed to our rapid growth,” said Rezwan Lateef, President of YES. “His proven ability to develop strong industry relationships aimed at enabling technology roadmaps, coupled with his intimate knowledge of Advanced Packaging processes, make Dan a valued addition to our senior leadership team.”

Prior to joining YES, Mr. O’Connell held senior key account management positions of increasing responsibility at ASM Pacific Technology Ltd., Tokyo Electron (TEL), LAM/Novellus, and Ebara. He holds a bachelor’s degree in Chemical Engineering from Worcester Polytechnic Institute.

About YES
Yield Engineering Systems, Inc. (YES) is a preferred provider of high-tech, cost-effective equipment for enhancing surfaces and materials. The company’s product lines include thermal processing systems, chemical vapor deposition (CVD) systems, and wet process equipment used for the precise surface modification of semiconductor substrates, semiconductor and MEMS devices, LED displays, and biodevices. Customers ranging from startups to Fortune 100 companies rely on YES systems to create and volume-produce innovative products in a wide range of markets. YES is headquartered in Fremont, California, with a growing global presence. For more information, please visit yieldengineering.com.

• Read more about YES Names Dan O’Connell as Vice President of Strategic Accounts

Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the “TrekApps” family, today joined RISC-V International (RVI) as a strategic member.

Breker will offer its expertise in SoC verification solutions to the RVI working groups.

“As the complexity of RISC-V processors for state-of-the-art systems continues to increase, rigorous commercial verification has become paramount,” remarks Calista Redmond, CEO of RISC-V International, the non-profit organization that maintains RISC-V as a free and open processor instruction set architecture (ISA). “Breker’s proven expertise and insights in this area are invaluable to enable the industry to address these challenges.”

Breker is known for its leadership in test content synthesis that leverages C++ and the Accellera Portable Stimulus Standard (PSS) specification models for UVM and SoC applications. It provides a portfolio of TrekApps that generates high-coverage, optimized tests to address common verification scenarios, including Cache Coherency, Security, Power Domain Management, Packet Generation, and the integration of ARM and RISC-V processors. Breker’s portfolio, in use at many leading semiconductor companies, is directly applicable to RISC-V SoCs, and invaluable to both processor developers driving quality and end-users looking to increase confidence in integrated devices.

“RISC-V International has revolutionized the semiconductor industry, and we are now seeing the result of this in widespread industry activity and at many of our semiconductor customers,” notes David Kelf, Breker’s CEO. “Rigorous, commercial verification is now critical for the ongoing success of RISC-V and Breker is committed to work with the organization to provide such solutions.”
Breker became a member to influence the development of a cache coherency and integration test content platform for RISC-V processor development and end-use verification. With the RISC-V ISA leveraged in greater numbers of advanced, application processors, this type of platform offers critical test functionality for many RISC-V stakeholders.

Breker at Design Automation Conference
Breker will demonstrate its System Coherency Synthesis TrekApp and other solutions at Design Automation Conference (DAC) in Booth #2528 (Second floor) Monday, July 11, through Wednesday, July 13, from 10 a.m. until 6 p.m. at the Moscone West in San Francisco.
Send email to [email protected] to arrange a meeting or demonstration.

About Breker Verification Systems
Breker Verification Systems is a leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from intent-based, abstract scenario models based on AI planning algorithms. Breker’s Test Suite Synthesis and TrekApp library allows the automated generation of high-coverage, powerful test cases for deployment into a variety of UVM, SoC and Post-Silicon verification environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM, Huawei and other companies leveraging Breker’s solutions are available on the Breker website. Breker is privately held and works with leading semiconductor companies worldwide.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
Facebook: https://www.facebook.com/BrekerSystems/

• Read more about Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies

Primarius Technologies will unveil its flexible and scalable design environment for custom memory and analog/mixed-signal IC design and new circuit simulation and design enablement solutions during the Design Automation Conference (DAC) July 11-13 at Moscone Center in San Francisco.

Demonstrations will feature Primarius’ NanoDesigner™, a full custom design platform; SDEP™, an innovative spec-driven modeling automation platform; PCellLab™, a PDK parameterized cell library development platform; NanoCell™, a standard cell library characterization solution; and 9812AC, the first commercial AC dynamic noise measurement system.

Other demonstrations will highlight products such as an all-in-one semiconductor parameter analyzer FS-Pro™, and a portfolio of solutions for SPICE model, process design kit (PDK) and standard cell library verification including ME-Pro™, PQLab™ and LibWiz™.

New Additions to Primarius Product Portfolio
Primarius is committed to delivering innovative data-driven design technology co-optimization (DTCO) EDA solutions powered by leading-edge SPICE/FastSPICE simulation technologies, shortening time to market and improving yield, power, performance and area of circuit designs at advanced process nodes.

Its DTCO solutions such as SDEP, PCellLab, NanoCell and FS-Pro reduce the iteration cycle from process technology development to IC design for models, PDKs and standard cell development products available from Primarius.

NanoDesigner provides an extendable and flexible design environment with schematic entry, layout editing and in-design physical verification that supports full-custom memory and analog/mixed-signal designs. It integrates with NanoSpice, Primarius’ circuit simulator series that offer the full spectrum of circuit simulation capabilities including high-performance parallel SPICE to an adaptive dual-simulation engine FastSPICE. Both offer more accurate and faster results than traditional SPICE and FastSPICE. NanoDesigner’s expanded capabilities cover mixed-signal verification, aging, EM/IR, random telegraph noise (RTN) and high Sigma yield analysis.
PCellLab, a user-friendly automated standard Pcell library development tool, pairs with PQLab, a PDK-quality verification platform, to form a complete solution for PCell generation and verification.

Primarius’ new NanoCell, a solution used for standard cell library characterization, and LibWiz, a user-friendly GUI to qualify libraries, combine for a standard cell library characterization and qualification solution.

And finally, 9812AC is the first commercial low-frequency dynamic noise measurement system. It has superior capabilities and versatility for measuring low-frequency noise characteristics of semiconductor devices over a wide range of bias voltage and excitation frequencies.

More Products in the Primarius Portfolio
SDEP, an innovative model development platform designed to tackle advanced SPICE modeling challenges, provides a system to retain and receive device modeling expertise and build automated flows for different process platforms and applications with intelligent target-oriented algorithms. It has a built-in parallel SPICE simulation engine for fast performance and includes rich data analysis and validation utilities, powerful parameter control and optimization functions and flow automation features.

FS-Pro is an all-in-one parametric analyzer used with semiconductor device DC/AC, reliability and statistical measurement solutions.

At 2022 Design Automation Conference
Primarius Technologies will exhibit at DAC Booth #1419 (First floor) Monday, July 11, through Wednesday, July 13, from 10 a.m. until 6 p.m. at the Moscone Center in San Francisco.

To arrange a meeting or demonstration of the Primarius Technologies product portfolio, send email to: [email protected].

About Primarius
Primarius Technologies (688206.SH) is a global electronic design automation (EDA) company. It delivers the semiconductor industry’s leading design enablement technologies for advanced SPICE modeling, PDK generation and standard cell library characterizations, and a complete design technology co-optimization (DTCO)-enabled custom design flow for complex memory, analog and mixed-signal designs. Powered by leading-edge SPICE/FastSPICE simulation technologies, Primarius is committed to delivering innovative DTCO solutions. Its mission is to shorten time to market and improve yield, power, performance and area of circuit designs at advanced process nodes. Primarius’ unique data-driven EDA solutions are supported by a full range of semiconductor parametric testing systems and the industry’s golden low-frequency noise testing systems. Visit Primarius Technologies for more information.

• Read more about Primarius Unveils Custom Design Environment, Circuit Simulation and Design Enablement Solutions at DAC

The global demand for computer chips is so high that existing product capacities can’t keep up. Therefore, unscheduled production downtime in Semiconductor fabs, must be avoided at any cost. Busch Vacuum Solutions developed a new service concept that ensures the availability of the vacuum supply, which plays an essential role in the semiconductor production process. This new service helps avoid unpredictable downtime and even makes it possible to reduce the overall operational costs by up to 35%.

The top priority given to all suppliers in the semiconductor and flat-panel market is the reduction of unscheduled downtime. In response, Busch Vacuum Solutions developed the unique vacuum pump remanufacturing service ARPQP (Advanced Remanufacture Product Quality Planning). The new service follows the four core principles of the world-class automotive standards of APQP in remanufacturing vacuum pumps. Following these principles is considered the highest standard for safe, efficient, reliable, and optimized manufacturing. ARPQP represents a new level of reliability for customers and focuses on advanced thinking and preemptive action for prevention. Busch is the first company in the field of vacuum technology to have embraced this standard. Vacuum pumps are remanufactured to automotive quality standards.

ARPQP has already proven to be successful among many Busch customers. The reasons why customers decide to use ARPQP vary. Yet, they all have the same objectives: avoid unscheduled downtime and improve performance. Their experiences after a few months are convincing. In all fabs, the failure rate for all types of vacuum pumps has decreased. One of the biggest Semiconductor manufacturers in the world experienced a 35% reduction in vacuum pump exchanges per year after implementing ARPQP for the entire installed base of vacuum pumps. This improvement led to a 7% increased production equipment availability, which is key when the loading of the Fab is already 100%.

About Busch Vacuum Solutions
Busch Vacuum Solutions USA sales and manufacturing headquarters is in Virginia Beach, VA where a team of 500 dedicated employees takes care of all their customer’s industrial vacuum needs. Busch USA is part of the global Busch Vacuum Solutions family owned company with over 3500 employees in more than 40 countries.

For more information about Busch: www.buschusa.com

• Read more about Avoid Unscheduled Downtime in Semicon Fabs with Preventive Vacuum Service

Deventer, June 21, 2022 – RoodMicrotec N.V., a leading independent company for semiconductors supply and quality services, and EnSilica plc, a leading chip maker of mixed signal ASICs (Application Specific Integrated Circuits), today announce that they have successfully brought a mixed signal automotive ASIC to commercial production following the official launch of a new flagship vehicle by a premium automotive company. The ASIC provides key differentiating features in the chassis control of the vehicle.

As announced in 2018, RoodMicrotec was selected by EnSilica to support it in the qualification and testing of this mixed signal automotive ASIC. RoodMicrotec will undertake final testing and shipment of the ASICs for EnSilica.

EnSilica is pleased to confirm that the main production run has now commenced with the official launch of the vehicle. The production schedule for more than 2.5 million ASICs over the next 12 months has been received. The ASIC has an anticipated seven-year production life and depending on the model, there are up to 24 ASICs per vehicle.

“It has been exciting to support EnSilica in bringing this project to production over the last few years. We are now looking forward to supporting production of this device in our Nördlingen facility”, says Martin Sallenhag, CEO of RoodMicrotec. “It again shows the demand for our unique combined capabilities, in depth experience and excellent track record in bringing automotive products to the market for our valued customers.”

“We are delighted to be entering the full production volume of this exciting project, having successfully collaborated with RoodMicrotec over a number of years. Our joint effort across this highly technical automotive project has now resulted in successful launch of the vehicle”, says Ian Lankshear, CEO of EnSilica.

About EnSilica
EnSilica is a leading fabless design house focused on custom ASIC design and supply for OEMs and system houses, as well as IC design services for companies with their own design teams. The company has world-class expertise in supplying custom RF, mmWave, mixed signal and digital ICs to its international customers in the automotive, industrial, healthcare and communications markets. The company also offers a broad portfolio of core IP covering cryptography, radar and communications systems. EnSilica has a track record in delivering high quality solutions to demanding industry standards. The company is headquartered near Oxford, UK and has a design centres across the UK and in Bangalore, India and Porto Alegre, Brazil.
Further information on EnSilica at www.ensilica.com

About RoodMicrotec
RoodMicrotec is a leading independent company for semiconductor supply and quality services. With more than 50 years of experience in the semiconductor and electronics industry, RoodMicrotec is well-established as a highly valued partner for many companies worldwide. The Company provides full-turnkey ASIC services for complex microchips that are customized to handle specific applications for individual customers. In cooperation with strong partners, RoodMicrotec manages the entire development and production flow of ASICs in the target volume, ranging from low quantities up to multiple millions per year. The turnkey solution includes project management, wafer test, assembly, final test, qualification, failure analysis and logistics. All services comply with the industrial and quality requirements of the high reliability, aerospace, automotive, healthcare and industrial sectors. RoodMicrotec’s headquarter is located in Deventer, Netherlands, with operational units in Nördlingen and Stuttgart, Germany.
Further information on RoodMicrotec at www.roodmicrotec.com

Further information
Martin Sallenhag - CEO, Arvid Ladega - CFO
Telephone: +31 570 745623 Email: [email protected] Web: www.roodmicrotec.com

This press release is published in English and German. In case of conflict between these versions the English version shall prevail.

• Read more about Premium Automotive Vehicle Launched with EnSilica’s Key Mixed Signal ASIC

Brewer Science presents EUV lithography innovation at largest tech conference in Asia
Roles of underlayers in EUV lithography is the keynote speech at CSTIC 2022
 

Rolla, Mo. June 20, 2022 - Brewer Science, Inc., a global leader in developing and manufacturing next-generation materials and processes for the microelectronics and optoelectronics industries, will present the keynote address, Roles of Underlayers in Novel Patterning for EUV Lithography, at the China Semiconductor Technology International Conference (CSTIC), one of the largest and the most comprehensive annual semiconductor technology conferences in Asia.

Semiconductor Innovation Requires Materials for Extreme Ultraviolet Lithography (EUV)
EUV lithography is used to pattern the smallest features in advanced semiconductor devices. The demand for smaller devices with more capabilities requires industry innovation in EUV processes and materials. Additionally, EUV plays a critical role in the evolution of technology and enables the continuous advancement of the semiconductor roadmap, as it provides the capabilities of higher processing power, while using less energy, and providing higher performance. However, one of the biggest challenges facing EUV lithography is material requirements, recognizing the critical role underlayers play in the patterning of EUV lithography. Unlike bottom anti-reflective coatings (BARC), thickness is not limited by wavelength, but rather related to resist and process requirements.

 
Roles of Underlayers in Novel Patterning for EUV Lithography
Dr. Douglas Guerrero, Senior Technologist at Brewer Science, has published over 60 papers in the areas of conducting polymers, BARCs, DSA, and underlayers for EUV lithography, and is an inventor on over 20 US patents. In his keynote address, Roles of Underlayers in Novel Patterning for EUV Lithography, during the Symposium II: Lithography and Patterning at CSTIC, he will provide information on the device and materials roadmap, as well as answer questions to the most critical questions in the industry:

• How does overall EUV patterning require thinner layers?
• What challenges do chemically amplified resists (CARs) and underlayers face?
• What role will underlayer play in future patterning?
• What are the options for patterning without a CAR?

Additionally, Zhimin Zhu, Senior Scientist at Brewer Science, will be co-chairing the Session II panel, Lithography Materials, within the Symposium II: Lithography and Patterning.

CSTIC will have nine symposiums covering all aspects of semiconductor technology with focus on manufacturing and advanced technology, including detailed manufacturing processes, device design, integration, materials, and equipment, as well as emerging semiconductor technologies, circuit design, and silicon material applications. CSTIC is organized by SEMI and IEEE-EDS, co-organized by IMECAS. The conference will be held June 14th, 2022 through July 12, 2022 accessed online through the SEMI Cloud.

If you are unable to attend, but wish to learn more about Brewer Science’s innovative EUV lithography materials, you can visit our website to view datasheets and schedule a call with an EUV expert.

 
About Brewer Science
Brewer Science is a global leader in developing and manufacturing next-generation materials and processes that foster the technology needed for tomorrow. Since 1981, we’ve expanded our technology portfolio within advanced lithography, advanced packaging, smart devices, and printed electronics to enable cutting-edge microdevices and unique monitoring systems for industrial, environmental, and air applications. Our relationship-focused approach provides outcomes that facilitate and deliver critical information. Our headquarters are in Rolla, Missouri, with customer support throughout the world. We invite you to learn more about Brewer Science at www.brewerscience.com.

• Read more about Brewer Science presents EUV lithography innovation at largest tech conference in Asia

Breker Verification Systems, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, appointed FirstEDA as its exclusive European distributor.

Twenty-year-old FirstEDA, a value-added distributor of design automation tools and training in Europe, now sells and supports Breker's TrekSoC™ and TrekUVM™ tools that automatically generate self-verifying test cases for multi-threaded, multiprocessor SoC devices and UVM block-based verification. Breker selected FirstEDA for its experienced and highly skilled engineering staff and understanding of the needs of the verification community.

“Breker stands out in the field of verification tools and solutions,” says Julian Lonsdale, Sales Director of FirstEDA, based in the U.K. “It consistently delivers high-quality, innovative and versatile tools to solve the challenges facing verification engineers.”

“FirstEDA is recognized as a trusted and well-connected European partner,” remarks Dave Kelf, Breker’s CEO. “Choosing to partner was an easy decision because we value the skillset and expertise it provides and know our relationship will flourish.”

About Breker Verification Systems
Breker Verification Systems is a leading provider of verification synthesis solutions that leverage SystemUVM, C++ and Portable Stimulus, a standard means to specify reusable verification intent. It is the first company to introduce graph-based verification and the synthesis of high-coverage test sets based on AI planning algorithms. Breker’s Test Suite Synthesis and TrekApp library allows the automated generation of high-coverage, powerful test cases for deployment into a variety of UVM, SoC and Post-Silicon verification environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM, Huawei and other companies leveraging Breker’s solutions are available on the Breker website. Breker is privately held and works with leading semiconductor companies worldwide.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
Facebook: https://www.facebook.com/BrekerSystems/

TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.

• Read more about Breker Verification Systems Appoints FirstEDA as Exclusive European Distributor

Breker Verification Systems, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, named NeXtream of Yokohama, Japan, as its exclusive distributor in Japan.

NeXtream, supplier of software, hardware and intellectual property (IP) created outside of Japan, now sells and supports Breker's TrekSoC™ and TrekUVM™ tools that automatically generate self-verifying test cases for multi-threaded, multiprocessor SoC devices and UVM block-based verification. Breker selected NeXtream for its marketing and sales professionalism and understanding of verification and validation, electronic design automation (EDA) and intellectual property (IP) markets.

“The verification engineering community here and elsewhere needs a solution to automatically generate thousands of tests for every semiconductor design project,” comments Tsunemori Kawahara, president and CEO of NeXtream. “Breker’s TrekSoC is such a solution and is embraced throughout the global chip design verification community.”

“NeXtream has deep ties into the chip design and verification community in Japan and a reputation for exceptional support,” remarks Dave Kelf, Breker’s CEO. “We look forward to a developing a close working relationship.”

About Breker Verification Systems
Breker Verification Systems is a leading provider of verification synthesis solutions that leverage SystemUVM, C++ and Portable Stimulus, a standard means to specify reusable verification intent. It is the first company to introduce graph-based verification and the synthesis of high-coverage test sets based on AI planning algorithms. Breker’s Test Suite Synthesis and TrekApp library allows the automated generation of high-coverage, powerful test cases for deployment into a variety of UVM, SoC and Post-Silicon verification environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM, Huawei and other companies leveraging Breker’s solutions are available on the Breker website. Breker is privately held and works with leading semiconductor companies worldwide.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
Facebook: https://www.facebook.com/BrekerSystems/

TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.

• Read more about Breker Verification Systems Names NeXtream Exclusive Distributor in Japan

Zurich, Switzerland / Heidelberg, Germany – Heidelberg Instruments Nano AG in Zurich, a subsidiary office of Heidelberg Instruments Mikrotechnik GmbH celebrated the 10-year anniversary of the commercialization of the NanoFrazor system series. The NanoFrazor is based on the Thermal Scanning Probe (t-SPL) technology and can be used for nanopatterning of quantum devices on 1D/2D materials, grayscale photonics devices, nanofluidic structures or biomimetic substrates for cell growth.

Originally the Thermal Scanning Probe technology was developed at IBM, where a group of researchers showed that the sharp tips of atomic force microscopes can be heated and used as a tool to “drill” nanoscale holes and later to write arbitrary nanostructures by using special, evaporating materials.

After exploring the technology at IBM, Felix Holzner and Philip Paul incorporated SwissLitho AG as a spin-off from ETH Zurich (Heidelberg Instruments Nano AG since 2021) as CEO and CTO with the idea of selling nanolithography equipment for t-SPL. The technical term “Thermal Scanning Probe Lithography” was then replaced by the product name “NanoFrazor”.

After starting operations of then SwissLitho in early 2013, the first commercial NanoFrazor machine named “Titlis”, a NanoFrazor Explore, was installed in 2014 at McGill University in Canada. “Titlis” is still running and just recently received an upgrade with the integration of the laser writer module jointly developed in Heidelberg and Zurich. Today, more than 50 NanoFrazor systems have been installed at renowned facilities all over the world, with new customers lined up for future systems.

“The NanoFrazor team in Zurich works on various promising developments on the instrument as well as on the materials to continuously expand the applications range of the technology. There are still manifold open opportunities for the NanoFrazor, as it can still be considered novel, even 10 years after the start of its commercialization. Everyone at Heidelberg Instruments is excited to see how the NanoFrazor will have developed in another 10 years from now”, Konrad Roessler, CEO of Heidelberg Instruments Mikrotechnik says.

The anniversary was celebrated in the newly opened office of Heidelberg Instruments Nano in Zurich together with family, friends, and numerous partners, who supported the successful journey of the NanoFrazor.

About Heidelberg Instruments Mikrotechnik GmbH
With over 35 years of experience and more than 1,200 installed systems, Heidelberg Instruments is one of the leading international players in developing and producing high-precision photolithography systems and nanofabrication tools. Heidelberg Instruments systems are installed in industrial and scientific facilities around the world. They are used for efficient direct writing and photomask fabrication for various industries, including semiconductors, quantum computing, photonics, 2D materials, IoT, and many related fields.

• Read more about Heidelberg Instruments celebrates 10 years of NanoFrazor

Primarius Technologies today announced its SDEP™ intelligent spec-driven model extraction platform has been adopted by Samsung Foundry.

SDEP helps Samsung Foundry and its customers significantly shorten turnaround time for SPICE model development, accelerating development competitiveness at legacy nodes, and enabling fast Design Technology Co-Optimization (DTCO) iterations at advanced process nodes. By continuously embedding know-how in the customized flow, engineers can run automated flows with more than 50% efficiency improvement for curve fitting. That solves resource shortage problems for multiple projects and ensures high-delivery quality of SPICE models independent of engineer’s experience level.

“Samsung and Primarius achieved another success with SDEP’s adoption after intensive testing and qualification of the technology on our advanced process platforms,” remarks Jongwook Kye, Executive Vice President of Foundry Design Enablement Team at Samsung Electronics. “Our mutual customers will benefit from having faster time to market with reduced model development and delivery time. With a SDEP setup, we can provide high-quality SPICE model and meet increasing customer demands with our available engineering resources.”

“Samsung has been a long-time Primarius customer and a strategic partner,” comments Dr. Zhihong Liu, Primarius’ Chairman and CEO. “SDEP is a revolutionary technology to enable an efficient DTCO and meet the toughest needs from advanced process development. We’re glad that SDEP is being adopted by Samsung Foundry, which enables fast iterations with design groups and further increases Primarius’ value as a Samsung SAFE ecosystem partner.”

SPICE modeling is more challenging and takes more effort at smaller technology nodes where device characteristics are more complicated. It now takes several months to develop a full SPICE model library for IC design after process technology development is completed.

In the post-Moore’s Law era, challenges include continuous shrinking of transistors and new process platforms for different applications using older technology nodes. Each variety of a process platform requires a dedicated effort on SPICE model development and foundries see more model development requests than previous generations. As a result, delivery of fast and accurate SPICE models with limited engineering resources is a challenge when faster time to market and quick iterations between process development and circuit designs are expected.

About SDEP
An innovative model development platform designed to tackle advanced SPICE modeling challenges, SDEP provides a system to retain and receive device modeling expertise and build automated flows for different process platforms and applications with intelligent target-oriented algorithms. Modeling experts can establish fully customized model auto-extraction flows for different applications using powerful and flexible modules available. With a built-in parallel SPICE as the core simulation engine for fast performance, it has integrated data analysis and validation utilities, rich parameter control and optimization functions as well as flow automation features.

At 2022 Design Automation Conference
Primarius Technologies will exhibit at the 2022 Design Automation Conference (DAC) in Booth #1419 (First floor) Monday, July 11, through Wednesday, July 13, from 10 a.m. until 6 p.m. at the Moscone Center in San Francisco.

To arrange a meeting or demonstration of the Primarius Technologies product line, send email to: [email protected].

About Primarius
Primarius Technologies (688206.SH) is a global EDA company delivering industry-leading design enablement technologies for advanced SPICE modeling, PDK generation and standard cell library characterizations, and a complete DTCO-enabled custom design EDA flow for complex memory, analog and mixed-signal designs. Powered by leading edge SPICE/FastSPICE simulation technologies, Primarius is committed to deliver innovative DTCO EDA solutions, with the mission to shorten time-to-market and improve YPPA of circuit designs at advanced process nodes, and unique data-driven EDA solutions, supported by full range of semiconductor parametric testing systems and industry’s golden low frequency noise testing systems. Visit Primarius Technologies for more information.

• Read more about Samsung Foundry Adopts Primarius’ SDEP to Shorten SPICE Model Development Turnaround Time