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Brewer Science Earns Intel’s 2023 EPIC Distinguished Supplier Award

Brewer Science is one of only 22 Distinguished Award recipients across Intel’s global supply chain

Rolla, MO, June 21, 2023 – Brewer Science is proud to announce that it has earned Intel’s EPIC Distinguished Supplier Award. Through its dedication to Excellence, Partnership, Inclusion, and Continuous (EPIC) quality improvement, Brewer Science has achieved a level of performance that consistently exceeds Intel’s expectations.

“As one of only 22 Distinguished Supplier Award recipients across the Intel global supply chain, Brewer Science stands out among suppliers in the semiconductor industry,” said Keyvan Esfarjani, chief global operations officer at Intel. “Their customer orientation and commitment to excellence is a testament to their dedication and serves as a global benchmark for others to follow.”

The Intel EPIC Distinguished Supplier Award recognizes a consistent level of strong performance across all performance criteria. Of the thousands of Intel suppliers around the world, only a few hundred qualify to participate in the EPIC Supplier Program. The EPIC Distinguished Award is the second-highest honor a supplier can achieve. In 2023, only 22 suppliers in the Intel supply chain network earned this award.

To qualify for an Intel EPIC Distinguished Supplier Award, suppliers must exceed expectations, meet aggressive performance goals, and score 80 percent or higher in performance assessments throughout the year. Suppliers must also meet 80 percent or more of their improvement plan deliverables and demonstrate formidable quality and business systems.

Get more information about the Intel EPIC Supplier Awards

Find the latest at the Intel Newsroom

Visit the Intel EPIC Supplier Awards page

About Brewer Science
Brewer Science is a global leader in developing and manufacturing next-generation materials and processes that foster the technology needed for tomorrow. Since 1981, we’ve expanded our technology portfolio within advanced lithography, advanced packaging, smart devices, and printed electronics to enable cutting-edge microdevices and unique quality monitoring systems for water and air applications. We are Certified Employee-Owned and a Certified B Corporation™, using our business as a force for good. Our headquarters are in Rolla, Missouri, with customer support throughout the world. Learn more at www.brewerscience.com.

Dresden, 21 June 2023. On 19 June, Masao Hodai, Chief Operating Officer of EBARA Precision Machinery Company Tokyo, visited EBARA’s German site in Dresden-Weixdorf. After a welcome by Dr Reinhart Richter, Managing Director of EBARA Precision Machinery Europe, an informative tour followed, during which Masao Hodai inspected the Overhaul Centre for vacuum pumps, built in 2021, the warehouse, the training facilities currently being built, and representatives from the most important product divisions. A joint lunch with members of Dresden’s staff rounded off his visit.

Strong signal for the Dresden location
“The visit of COO Masao Hodai reinforces our location within the Silicon Saxony region and shows the significant status of the semiconductor industry in Dresden for EBARA’s headquarters in Japan. Our progress in terms of safety, quality, CO2 reduction and market acquisition has made a deep impression. All EBARA employees in Dresden feel very honoured by this visit from Japan”, said Dr Reinhart Richter, happily. In the afternoon, in-depth client meetings were on the agenda at the Dresden site before Masao Hodai returned home to Tokyo.

About EBARA
EBARA Precision Machinery Europe (EPME) GmbH, headquartered in Sauerlach near Munich, is the European sales and service company of EBARA Corporation Tokyo. EBARA is a leading global manufacturer of vacuum and semiconductor systems used to produce wafers, liquid crystals, solar cells and other high-tech products. EBARA Corporation was founded in 1912 by Issey Hatakeyama and employs over 19,000 people worldwide. With an annual turnover of 4.7 billion euros, EBARA is one of the largest companies in the industry. EBARA supplies 16 of the top 20 manufacturers in the chip industry.

About EBARA Precision Machinery Europe
The EPME portfolio includes dry and turbomolecular vacuum pumps as well as modern gas abatement systems for the chemical industry, for example. In addition, EPME distributes state-of-the-art CMP tools, wafer bevel polishing and substrate coating systems for chip manufacturing. In 2021 EBARA opened its second modern overhaul centre for vacuum pumps in Dresden. EPME has been operating a vacuum pump overhaul centre in Livingston (UK) since 1993. EPME employs over 250 people in Europe and Israel.
Photo: EBARA / Tommy Halfter

Brewer Science’s High-Temperature-Stable, Gapfilling Planarizing Material Revolutionizes Advanced ArF and EUV Processes

OptiStack® SOC450 material provides zero shrinkage up to 550°C when baking in N2

June 15, 2023 – Rolla, MO – Brewer Science, Inc., a global leader in developing and manufacturing next-generation materials for the microelectronics and optoelectronics industries, is thrilled to announce the latest breakthrough in high-temperature gapfilling materials – OptiStack® SOC450 material, enabling advanced node processes by providing unparalleled performance at extreme temperatures.

A basic overview of a spin-on carbon and the need for a high-temperature stable material.
Overcoming the Industry Compromise: Thermal Stability for Planarization and Gapfilling

One of the greatest challenges in the advanced ArF and EUV industries has been finding a material that can withstand high temperatures without sacrificing its planarization and gapfilling capabilities.

Shrinkage in spin-on glass (SOG) coatings, or annealing processes, can result in incomplete coverage, pattern distortion, delamination, or cracking. Insufficient thermal stability properties can affect subsequent process steps, compromising the overall performance and reliability of the device. To prevent significant yield loss caused by unstable materials during high-temperature annealing, such as those necessary in self-aligned double patterning (SADP) applications, it’s important to ensure gapfilling materials are stable over 400°C.

A typical low-temperature SOC has 50% weight loss when baked to 400°C which makes planarization suffer due to the film shrink.

OptiStack® SOC450 Material Enables SADP Processing with High Thermal Stability

With OptiStack® SOC450 material EUV processes will no longer have to sacrifice temperature stability for superior gapfilling and planarization.

OptiStack® SOC450 material is a carbon-based high-aspect-ratio spin-on-carbon material designed to withstand high temperatures and provide low shrinkage, offering significant benefits to ArF, EUV, SADP, SAQP, 3D NAND, and advanced memory processes.

The following simplified example illustrates one potential application of OptiStack® SOC450 material to improve a SADP process by utilizing high-temperature CVD deposition of the spacer.

The following simplified example illustrates one potential application of OptiStack® SOC450 material to improve a SADP process by utilizing high-temperature CVD deposition of the spacer.

Key Features and Benefits of OptiStack® SOC450 Material

Zero Shrinkage: Unlike traditional SOC materials, OptiStack® SOC450 material boasts a remarkable 0% shrinkage when subjected to high-temperature baking, up to 550°C when baking in N2 after a 170°C soft bake step. This means precise planarization and gapfilling are possible without worrying about dimensional changes, maintaining the integrity of valuable components.

High Thermal Stability: OptiStack® SOC450 material can withstand high-temperature vacuum-deposited SiXn films over 200 nm. The high thermal stability enables integration schemes utilizing chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) processes.

OptiStack® SOC450 material offers narrow trench and high-aspect ratio gapfilling, including a complete fill, without void or delamination.

CMP Compatibility: When a strict global-level planarization is needed, OptiStack® SOC450 material can be further planarized by chemical mechanical planarization (CMP) for use in high topography, and/or highly variable pattern density devices. With many spin-on carbons facing challenges with long-range planarization, the ability to OptiStack® SOC450 material enables superior planarization by controlling the rate of removal, based on the slurry and pad type.

CVD Processing: Chemical vapor deposition (CVD) can pose many problems if the spin-on carbon material vaporizes or sublimates, including contamination that leads to defects. Ineffective CVD can cause film thickness variation or that challenge the integrity of the device. Off-gassing, delamination, and cracking are also seen with traditional SOC thermal decompositions. OptiStack® SOC450 material does not sublimate or vaporize in conditions up to 400°C, and demonstrates superior stability in conditions up to 550°C.

Increase Efficiency: High carbon content of OptiStack® SOC450 material enables CF4 plasma etch rates better than SiOx. Ultralow metal ions less than 1,000 part-per-trillion ensure decreased post-etch defects. Additionally, the solubility in fab-friendly solvents and compatibility with other spin-on materials eliminates potential drain clogging issues.

OptiStack® SOC450 material will redefine what you expect from high-temperature-stable, gapfilling planarizing materials. Its unique combination of thermal stability, zero shrinkage, and exceptional performance will enable new possibilities for your products, helping you achieve unprecedented levels of quality and reliability. Don’t settle for compromises between thermal stability and superior gapfilling when you can have it all with OptiStack® SOC450 material. Connect with a product expert or learn more by visiting our website.

About Brewer Science
Brewer Science is a global leader in developing and manufacturing next-generation materials and processes that foster the technology needed for tomorrow. Since 1981, we’ve expanded our technology portfolio within advanced lithography, advanced packaging, smart devices, and printed electronics to enable cutting-edge microdevices and unique monitoring systems for industrial, environmental, and air applications. Our relationship-focused approach provides outcomes that facilitate and deliver critical information. Our headquarters are in Rolla, Missouri, with customer support throughout the world. We invite you to learn more about Brewer Science at www.brewerscience.com.

United States

Online via Web Conference
United States

Standards

TRACEABILITY NORTH AMERICA TC CHAPTER

Date: Wednesday, July 19, 2023

Time: 4:00-6:00 PM Pacific 

Online via Web Conference

 

AGENDA (TBD)

(subject to change) 

Last updated: March 10, 2022

 

NOTE: 

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend. 

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! 

Questions? Contact your local staff coordinator: Click here 

4:00 pm - 6:00 pm Off Add to Calendar Disabled

Registration

Member: $49
Non-Member: $99

Registrants will receive the presentation recording and PDFs of Webinar #4.

Taylor Zhao
Manager, Programs & Committees
[email protected]

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United States Register Now Business Technical

SiC—Silicon Carbide Webinar #4: Understanding Sic Chip Cost, the Impact of Defects, and the Case of Price Parity With Si at the System Level

Silicon devices are dominating power electronics due to their excellent starting material quality, streamlined fabrication, low-cost volume production, proven reliability and ruggedness, and design/circuit legacy. Although Si power devices continue to make progress, they are approaching their operational limits primarily due to their relatively low bandgap and critical electric field that result in high conduction and switching losses, and poor high temperature performance.

SiC power chips are gaining significant market share and are projected to capture over 30% of the power chip market by 2029. Their cost, however, remains above that of similarly rated silicon chips and increases disproportionately with area. In this presentation, various elements of SiC chip cost will be qualitatively analyzed including contributions of substrate, epitaxy, and chip manufacturing. Material defects will be discussed in terms of their impact on chip area scalability and yields, and wafer test maps will be presented to elucidate their correlation. Finally, the case of system-level price parity between Si and SiC will be made, achieved primarily through reduced mass and volume of magnetic components, and simplified thermal management

 

View other webinars in the SiC Series

  • Webinar #1—Silicon Carbide Material Properties, Key Applications, and Fabrication Basics: Making the Transition from Silicon
  • Webinar #2—Non-CMOS Compatible SiC Power Device Fabrication in Volume Si Fabs
  • Webinar #3—Bidirectional SiC and GaN Switch Technology 
  • Webinar #4—Understanding SiC Chip Cost, the Impact of Defects, and the Case of Price Parity With Si at the System Level 
  • Webinar #5—SiC Edge Termination Technology

 

Meet the Speaker

Biography

United States

Victor Veliadis, PowerAmerica
Victor Veliadis, PhD
Executive Director and Chief Technology Officer,
PowerAmerica

Now Available On-Demand!

Join us online for the fourth webinar in the Silicon Carbide Series—Understanding SiC chip cost, the impact of defects, and the case of price parity with Si at the system level.

Off Add to Calendar Disabled America/Los_Angeles 1
Event format

Xpeedic of Cupertino, Calif., unveiled RF EDA Solution 2023 edition today at the IEEE MTT International Microwave Symposium (IMS) here, showcasing its ability to accelerate the design of highly integrated RF modules and systems using its differentiating chip-package-system EDA tools and mass-production proven Integrated Passive Devices (IPD) IP.

The RF Electronic Design Automation (EDA) Solution includes XDS, Xpeedic’s RF system-level design and simulation platform, IRIS, its on-chip passive modeling and simulation tool, and iModeler, a passive model generation tool.

XDS provides schematic design and simulation, post-layout electromagnetic simulation with both method-of-moments (MoM)- and finite-element-method (FEM)-based solver technologies, electro-magnetic (EM) circuit co-simulation and tuning/optimization. In the new 2023 edition, XDS features a new filter synthesis algorithm and supports parametric padstack and permittivity, SNP-based LC matching in Smith Chart, bondwire simulation and hierarchy design for schematic and layout.

IRIS has been widely adopted for RFIC designs and certified for advanced process nodes. In the new 2023 edition, IRIS upgrades its accelerated 3D EM solver engine with improved run time and peak memory usage.

iModeler now includes built-in MoM cap, MiM cap, inductor and transformer templates, enables parameterized result exploration using built-in templates.

Xpeedic at IMS
Xpeedic will be in Booth #1121 at the IEEE MTT International Microwave Symposium (IMS) in the San Diego Convention Center in San Diego. Hours are today from 9:30 a.m. until 5 p.m., Wednesday, June 14, from 9:30 p.m. until 6 p.m. and Thursday, June 15, from 9:30 a.m. until 3 p.m. Attendees can stop by the booth to schedule demos or meetings by sending email to [email protected].

“Overview of Integrated Passive Devices (IPD) for RF Front-end Applications” will be presented by Xpeedic Wednesday at 3 p.m. at the MicroApps Theater in Booth #2447.

About Xpeedic
Xpeedic is a leading EDA provider to accelerate designs and simulations of next generation high-frequency, high-speed intelligent electronic products. Powered by its proprietary electromagnetic, circuit, and multi-physics solver technologies, Xpeedic is addressing challenges in designing IC in advanced nodes, 3D-IC with advanced packaging, high-speed digital, and RF systems for the markets including data center, automotive, communication, mobile, and IoT. Founded in 2010, Xpeedic has offices in both U.S. and China. For more information, please www.xpeedic.com.

Engage with Xpeedic
www.xpeedic.com
Twitter: @xpeedic
LinkedIn

Xpeedic of Cupertino, Calif., today announced its Integrated Passive Devices (IPD) shipments surpassed an unprecedented two-billion units accomplished through its mass production-proven IPD development platform that enables proliferation of IPDs to RF front-end modules.

Xpeedic’s IPDs and IPD development platform will be showcased today through Thursday at the IEEE MTT International Microwave Symposium (IMS) in San Diego.

“This is a momentous milestone for Xpeedic,” remarks its CEO Feng Ling. “Our commitment to continue addressing RF and other significant design challenges remains unchanged.”

Adoption of Xpeedic’s IPDs is driven by the need for smaller, high-performance, cost-effective, and reliable electronic systems across various industries. Advantages of the solution include:
• A rich set of IPD libraries on various IPD processes, such as high-resistivity silicon and glass for common, ready-for-mass production building blocks used in RF front-end modules.
• Trusted foundry and packaging ecosystem partners supporting both quick prototype and mass production.
• Home-grown electronic design automation (EDA) design flow tailored to meet specific needs for greater efficiency and productivity. Developing an in-house EDA design flow also fosters innovation and differentiation by incorporating internal design methodology that results in unique designs with competitive advantages.
• A dedicated and experienced design team enabling quick turnaround for customized IPDs.

Xpeedic at IMS
Xpeedic will be in Booth #1121 at the IEEE MTT International Microwave Symposium (IMS) in the San Diego Convention Center in San Diego. Hours are today from 9:30 a.m. until 5 p.m., Wednesday, June 14, from 9:30 a.m. until 6 p.m. and Thursday, June 15, from 9:30 a.m. until 3 p.m. Attendees can stop by the booth to schedule demos or meetings by sending email to [email protected].

“Overview of Integrated Passive Devices (IPD) for RF Front-end Applications” will be presented by Xpeedic Wednesday at 3 p.m. at the MicroApps Theater in Booth #2447.

About Xpeedic
Xpeedic is a leading EDA provider to accelerate designs and simulations of next generation high-frequency, high-speed intelligent electronic products. Powered by its proprietary electromagnetic, circuit, and multi-physics solver technologies, Xpeedic is addressing challenges in designing IC in advanced nodes, 3D-IC with advanced packaging, high-speed digital, and RF systems for the markets including data center, automotive, communication, mobile, and IoT. Founded in 2010, Xpeedic has offices in both U.S. and China. For more information, please www.xpeedic.com.

Engage with Xpeedic
www.xpeedic.com
Twitter: @xpeedic
LinkedIn

Kitchener, Ontario – PEER Group®, the largest supplier of innovative factory automation software products for the semiconductor industry, is sharing its SEMI® Standards expertise and insight during the industry-led Global Cybersecurity Forum, happening at SEMICON West 2023.

Featuring talks by executives from leading chip makers, OEMs, and suppliers, the forum, Securing the Future for Semiconductor Manufacturing, will highlight the current state of industry-wide cybersecurity status, risks, and effects and detail the collaboration plans to protect the entire semiconductor supply chain.

“Amid recent high-profile cyberattacks on fabs, the semiconductor industry is banding together in defense of our highly complex and valuable global supply chain,” says Doug Suerich, PEER Group’s Director of Marketing, “the Global Cybersecurity Forum provides a prominent platform for industry leaders to discuss this topic. The caliber of speakers reflects the critical importance cybersecurity is to semiconductor manufacturing and we look forward to advancing our defensive strategy together as an industry.”

Suerich will be moderating the four-hour forum, which is scheduled to begin at 1:00 p.m. PDT on Wednesday, July 12.

The forum will kick-off with keynote addresses by Brent Conran, CVP, Chief Information Security Officer, Intel Corporation, and James Tu, PhD, Head of Corporate Information Security, TSMC. Additional presenters include executives from Applied Materials, ASML, Lam Research, and the National Institute of Standards and Technology (NIST).

Mike Kropp, PEER Group’s Co-Founder, CEO, and President, will also speak during the forum, sharing insight into the potential vulnerabilities associated with software that is used on semiconductor tools and in factories and the best practices companies follow to mitigate these issues. Kropp will provide an overview of SEMI® E187 and E188, the new Cybersecurity Standards published by the SEMI Fab & Equipment Information Security and the SEMI Fab & Equipment Computer Device Security Task Forces.

PEER Group has extensive experience helping OEMs and factories comply with the various SEMI Smart Manufacturing Standards, which include Cybersecurity Standards E187 and E188. In addition to participating in the Global Cybersecurity Forum, PEER Group will also be exhibiting during the show. To learn more about PEER Group products and services, stop by booth 451 during SEMICON West or visit: https://www.peergroup.com/news-events/events/semicon-west-2023

About PEER Group
PEER Group® is the largest supplier of innovative factory automation software products for the semiconductor industry. Since 1992, our solutions have helped the world’s most advanced OEMs and factories reduce time to market and lower costs by solving their equipment automation, data management, and process control problems. A multi-award winning company, PEER Group has been named a Best Workplace by Great Place to Work Canada 11 times, and most recently was one of six recipients of Intel’s 2022 EPIC Outstanding Supplier Award, which recognizes the absolute top performers in the Intel supply chain. Follow PEER Group on LinkedIn and Twitter at @PEERgroup_Inc..

Axiomise, the leading provider of cutting-edge formal verification solutions that include training, consulting, services and custom apps, today launched its next-generation formalISA® app with open-source, formally verified RISC-V processors such as cv32e40p and WARP-V.

Also announced today is a new RISC-V Studio Portal with real-world formalISA applications and product demonstrations to help the RISC-V ecosystem understand the necessity of exhaustive formal and the kind of bugs that can be caught with formal methods.

“We are excited to share the app launch in conjunction with a new studio portal with real-world applications of formalISA and product demos,” remarks Dr. Darbari. “The app will enable the wider ecosystem of RISC-V to see why exhaustive formal verification is a necessity and what kind of bugs can be caught with formal methods. formalISA app is a powerful offering in realizing our vision of making formal normal. Axiomise has the tools and the skills to become the ‘go to’ RISC-V Verification expert.”

Dr. Darbari and his team will be at the RISC-V Summit Europe to demonstrate formalISA in Bay 7 from Tuesday, June 6, to Thursday, June 8, at Hotel Barcelo Sants in Barcelona, Spain.

About formalISA
Axiomise’s formalISA is a push-button formal verification solution used for architectural and micro-architectural verification of RISC-V processor cores. Initially launched four years ago, it has been used to formally verify numerous open-source and commercial RISC-V processors by identifying deep corner-case bugs and mathematically proving the absence of bugs on complex out-of-order and in-order cores.

A state-of-the-art proof status dashboard captures reporting and coverage information and provides full automation, saving time and cost. formalISA is powered by i-RADAR®, and a reporting and coverage solution called SURF.

formalISA is available now. Pricing is available upon request.

About Axiomise
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, FIETE, DPhil (Oxford), who has been a formal verification practitioner for more than two decades with 60 patents in formal verification and over 70 publications.

Engage with Axiomise at:
Website: www.axiomise.com
Twitter: @axiomise
LinkedIn: https://www.linkedin.com/company/axiomise/
Facebook: https://www.facebook.com/axiomise
Axiomise, formalISA and the Axiomise logo are trademarks of Axiomise Limited, UK.
Making formal normal is a registered trademark of Axiomise Limited, UK.