Technology and Trends

Sapphire is a precious gemstone, consisting of aluminum oxide (α-Al2O3) with occasional traces of other elements such as iron, titanium, chromium, vanadium or magnesium. While sapphire stones found in nature mostly go to jewelry applications, the lab-grown sapphire – produced in a scale of up to several hundred tons per year – is widely used by the electronic industry. Now one can hardly find a branch of technology where this crystal is not used.Sapphires are mainly applied in infrared optical components, high-durability windows, wristwatch crystals, and the very thin electronic wafers used as the insulating substrates of solid-state electronics. High thermal conductivity, low reactivity, and appropriate unit cell size make sapphire an ideal material for a wide range of such electronic substrates for manufacturing of components such as LEDs and CMOS chips.SEMI spoke with Ivan Orlov, CEO of Scientific Visual, after his presentation at SEMI Strategic Materials Conference at SEMICON Europa, 12-15 November, 2019 in Munich, Germany, to learn more about the future of sapphire.SEMI: Why is sapphire an ideal material for a wide range of electronic substrates? Orlov: Sapphire undoubted advantages are its chemical inertness and ability to withstand high temperature, radiation and mechanical loads. In addition, it exhibits low dielectric loss and very good electrical insulation that makes sapphire a good candidate for substrates for LEDs and laser diodes or wafers for epitaxial growth. However, the most important advantage is that sapphire crystal lattice does very well matching semiconductor materials deposited to its surface, in particular nitrides of group III elements. To plainly benefit from these features, the grown sapphire must have as few macro- and micro-defects as possible, as substrate defects are inherited by semiconductors layers grown on the substrate surface. Hence the importance to detect defects in the raw sapphire material. This is the area where our team at Scientific Visual contributes. SEMI: Flaws are usually identified only after costly wafering and polishing steps, because rough surface of raw crystals prevents detection of the defects. What can be done to prevent defects?Orlov: Today, major players are investing in growing larger crystals without mastering in depth the growth process. Let’s face it, the semiconductor substrate industry, which is primarily based in Asia, is using empirical research methods. The raw sapphire boules are still inspected manually, and this qualitative assessment is exploited in two folds. The first step is to further process the boule. Furnace operators then adjust the growing parameters depending on the results of the manual inspection.Due to the lack of visibility into internal crystal defects, the crystal growth and its downstream processing remain an art rather than a science. The primary reasons are the difficulty to measure, locate and quantify precisely the defects in the full crystal volume. Scientific Visual equipment enables defects in raw boules to be fully quantified and categorized. With such objective measurements and knowing the full set of growth parameters, the Process Engineering (PE) team can, with the assistance of deep learning algorithms, considerably improve the growing process. Our quality control tools give Process Engineering team the “eyes” to see complete defect distribution in raw crystals, enabling it to make minor modifications in the growth process to improve yields, reduce costs and shorten the time to market for products.SEMI: What lead to those advancements and what problems did your team set out to solve? Orlov: Breakthroughs in immersion tomography, machine vision and parallel computing drove advancements in automated quality control technology. Previously crystal inspection accuracy was limited by the acuity of the operator’s eye and subjective bias. Light distortion and the diffusion of crystals made it impossible to accurately identify internal defects.Scientific Visual equipment give operators an undistorted 3D view of all defects in a crystal boule or ingot. However, only deep learning technology can correlate a hundred thousand growth data points to identify a final defect pattern.Defect pattern in non-processed item cored from EFG sapphire plate. Well visible is a typical wavy pattern of surface layers and sandwich structure in the volume. Color code marks sapphire defect density: from deep blue (non-defective material) to deep red (highest defectiveness.) SEMI: What challenges are addressed by your approach? Orlov: Increasing the yield of semiconductor substrates like Sapphire, Gallium Nitride and Silicon Carbide is paramount to reducing the price of wafers while increasing their quality. The upstream growth and downstream wafering processes are not deterministic. So far, most of the producers can only determine the quality during the late stages of the process. This condition creates huge constraints for teams in charge of production and processing. Automated Quality Control (QC) at the early stage of the production chain relieves all the unknowns, ultimately reduce the cost of material.SEMI: And what are the main opportunities?Orlov: There are massive opportunities to increase the yield and to ease the full processing chain from growth to the wafering process. Objective Quality Control (OQC) paves the way to industry-wide standards that categorize crystal quality at each step of growth to enable full certification of the defectiveness of the material and facilitate its trade and exchange.SEMI: What’s one of your predictions for the future of new materials?Orlov: The explosion of e-mobility and electric vehicles and the development of other green technologies will drive rising demand for low-defect sapphire, silicon carbide and gallium nitride substrates thanks to the streamlining of the full processing chain. Manual quality control will soon give way to full automation as quality control in sapphire and other raw crystals production is the only missing link in a fully automated semiconductor production chain. I believe that in five years, automated raw crystal inspection will become standard in the industry. Our mission is to empower every crystal grower to achieve this important milestone.Dr. Ivan Orlov obtained a Ph.D. in Crystallography from the Federal University of Technology in Switzerland EPFL and an MSc in Solid-State Physics in Moscow, Russia. Ivan co-founded Scientific Visual in 2010 to answer the challenge of the synthetic crystals industry struggling with high defect yield. Prior to this he worked in a company specialized in diamond optics. He has more than 10 years of experience in R D with focus on optical materials, industrial crystals and non-destructive quality control technologies. Dr. Orlov was a SEMI Task Force member for sapphire standard development in China and collaborates with ISO committee in Switzerland to establish industry-wide sapphire quality standards.Serena Brischetto is senior marketing and communications manager at SEMI Europe.

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

In a shining hour for Prof. Mike Czerniak, environmental manager for Edwards Ltd., a SEMI member company, and Chemistry Prof. Simon O’ Doherty of the University of Bristol, the educators presented a case study on efforts by the semiconductor and aluminum industries to mitigate greenhouse gas emissions – part of an online Bristol Futures course that won the National Award in the Next Generation Learning and Skills category of the prestigious Green Gown Awards.The online students hailed the semiconductor industry as an exemplar of applying abatement systems to the reduction of greenhouse gas emissions as well as an excellent example of an engaged industry and true dedication to sustainable development. The course – Unleash Your Potential: Sustainable Futures – encourages students to learn about the sustainability challenges of the modern world and make a positive contribution to society.This four-week online course takes learners on a journey to explore their personal views and understanding of sustainable development, then addresses challenges faced by the city of Bristol and globally before bringing them back to the personal. The case study features academics and industrial partners discussing the challenges of greenhouse gas emissions and the benefits of cutting-edge collaborations aimed at driving long-term solutions.Hosted on the FutureLearn platform and offered three times a year, the free online course is structured around the United Nations Sustainable Development Goals (SDGs) to provide fascinating, solution-based narratives in the era of the Anthropocene.The University of Bristol launched Bristol Futures in 2018 and the initiative centers on three themes: Global Citizenship, Sustainable Futures and Innovation, and Enterprise. The interdisciplinary team that developed the Sustainable Futures theme consisted of myself (Ph.D. candidate, Chemistry/Geography), Chris Preist (Professor, Computer Science and Sustainability) and Aisling Tierney (Ph.D. Archeology); this interdisciplinary approach was introduced by sustainable development pioneers Chris Willmore (Professor of Law and Sustainability) and Martin Wiles (Head of Sustainability)The case studies have one particular strength – a sweeping diversity of contributors to reflect the endless possibilities of sustainable development. The 10-minute videos engage learners with academics, researchers, industrial experts, students, government and non-government organizations and communities. The Head of Unesco for Maritime Affairs, goat herders in Croatia, authors, the Intergovernmental Panel on Climate Change (IPCC), first-year university students – they all add their special flavor to sustainable development.Established in 2004, the Green Gown Awards recognize the exceptional sustainability initiatives being undertaken by universities and colleges. We are extremely proud that this online course has been recognized as sector leading by the Green Gown Awards and thrilled that the Sustainable Futures online course has been taken by more than 5,700 people, including over 2,000 students at the University of Bristol.We hope that the Sustainable Futures family will continue to grow and invite you to join us in this exploration of sustainable development, global challenges and yourself in our next run starting in February 2020!Eleni Michalopoulou is a Ph.D. candidate, Atmospheric Chemistry Research Group, School of Chemistry, at the University of Bristol.

The industry continues rewarding luminaries of the SOI ecosystem. Recently recognized are Jean-Pierre Raskin for RF-SOI, Lattice Semi and NXP for FD-SOI products, and Bich-Yen Nguyen for her work in SOI. The SOI Consortium extends hearty congratulations to all the winners and their teams. Professor Jean-Pierre Raskin was awarded by the prestigious Médaille Ampère 2019 for the originality of his scientific work in the field of RF-SOI technologies for wireless communication. The international award was delivered by Mr. François Gérin, president of the SEE - Société de l'électricité, de l'électronique et des technologies de l'information et de la communication, on December 3rd, 2019, in Paris, France. We’ve long covered the work of Professor Raskin and his UCLouvain team – which is largely responsible for why SOI is in every smartphone on the planet. It’s a great story (read it here) and it goes on! In his Ampère acceptance speech, Professor Raskin said, “...significant industrial research and development is being performed toward fully integrated SOI front-end-modules. Notably, the 45nm PD-SOI [RF-SOI] and 28nm and 22nm FD-SOI nodes are being extensively designed with to develop 5G mm-wave low-noise amplifiers (LNA), power amplifiers (PA) and switches, in particular at 28 GHz. […] Overall, SOI is expected to be a big contender as a technological platform to enable mass production of millimeter wave 5G and ultra-low power RF IoT devices and products in the near future.” [caption id="attachment_27119" align="alignleft" width="294"] Lattice CEO Jim Anderson (left) and Mark Lipacis (right), Managing Director of Jefferies (Courtesy: GSA Lattice Semi)[/caption] Lattice Semiconductor was the recipient of the Global Semiconductor Alliance’s (GSA) 2019 Analyst Favorite Semiconductor Company award based on technology and financial performance. The GSA awards recognize the achievements of top performing semiconductor companies and the 2019 winners were announced at the annual GSA Awards Ceremony held on December 5, 2019. In thanking his team, Lattice CEO Jim Anderson, added, "We are even more excited about the solid execution of our product roadmap, specifically, the accelerated product rollouts of both CrosslinkPlus and our next generation FPGA platform based on FDSOI technology, which will be key catalysts to our achieving sustained long-term revenue and profitability growth.” [caption id="attachment_27120" align="alignright" width="71"] (Courtesy: NXP)[/caption] NXP was a recipient of a Best-in-Show Award at the 2019 Arm TechCon this fall. As was noted by Brandon Lewis, Editor-in-Chief of Embedded Computing Design, “The i.MX RT1170 crossover MCU marks a technology breakthrough in MCUs, running up to 1GHz while maintaining low-power efficiency. It is architected to deliver a record-setting performance, with a 6468 CoreMark score and 2974 DMIPS while executing from on-chip memory. The solution uses advanced 28nm FD-SOI [note: fabbed by Samsung Foundry] technology, making NXP the first company to build MCUs in this advanced technology node. This new MCU family is redefining the "edge" and MCU landscape, bringing unprecedented performance and high levels of integration to propel industrial, IoT, and automotive applications.” And finally, Soitec Senior Fellow Bich-Yen Nguyen was elevated to the status of IEEE Fellow in the Class of 2020 “for contributions to silicon on insulator technology”. As previously noted in her IEEE bio, “Her honors and awards include the Dan Noble Fellow, the highest technical award at Motorola; the Master of Innovation Award; and the first national Women in Technology Lifetime Achievement Award. She holds over 200 worldwide patents and has authored more than 180 technical papers on integrated circuit technologies.”

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

“A hundred years from now, someone’s going to look back and say, ‘Can you believe they waited until you got a disease, and then they did something?’” This observation from Dr. William Hait, the leader of Johnson Johnson’s External Innovation program, crisply sums up the SEMI Smart MedTech Summit, a two-day program at SEMICON Europa 2019, sponsored by GE Research and imecBenjamin Wiegand, PhD of Johnson Johnson, cited the quote in his opening presentation and added another pertinent question: “What if we could predict who was going to get a disease and then preempt it from happening?” Weigand’s conclusion is the first of six key takeaways from the summit.1. Accomplishing this vision could lead to a world without disease. Developing a disease-free world by exploring how the integration of advanced electronics and medical technology (MedTech) can enable new healthcare solutions is the very mission of the SEMI Smart MedTech Initiative. Various experts speaking at the MedTech Summit delved into a range of topics, from pan-European medical initiatives and artificial organs to new sensors and systems and start-ups’ need for funding and partners.2. All of us will have a digital twin (avatar), bringing together all relevant data that can impact our health and well-being.Several speakers illustrated the advantages of a digital human avatar that would start with an individual’s unique physical data and then be continuously updated with new data tracked by body-worn devices and from ongoing research findings. This would enable healthcare providers to extract insights and predict future physical performance or health issues.While, technologically, the avatar can already be constructed, the ability to make real changes to future human behavior is a significant outstanding question. Multiple speakers highlighted the various benefits of digital avatars at the MedTech Summit. 3. The MedTech sector’s need for cybersecurity looms large, as it does in every other digitally-driven, IOT-based framework.Further exploring the human-to-digital interface, Anthony Mathur of Bart’s Heart Center in the UK pointed to the importance of strict laws for safeguarding patient privacy, a cornerstone of healthcare digital policies, and the critical need for cybersecurity. He warned against an all-digital action network, citing the virus attack that shut down the UK’s National Health Service, rendering all patient records inaccessible for more than two weeks.4. MedTech devices, systems and other tools will radically change healthcare in the not-too-distant future.Almost every speaker touched on this point, including Franz Laermer of Bosch in his presentation The Future of Personalized Treatment. Laermer explored devices that will drive more patient-centric healthcare in areas including asthma therapy and molecular diagnostic testing and highlighted innovations in monitoring oncology therapies more effectively, less invasively and more accurately. Other presenters showcased their work in areas including silicon-based microfluidics, next-generation DNA sequencing and synthesis, lab-on-chip and cell arrays. 5. Startups and well-established companies will help advance digital tools and data to keep us healthier, happier and safer. Among the MedTech Summit highlights, several start-ups presented their business, financial and go-to-market plans. Notably, continuous glucose monitoring (CGM) is an especially active area of investment and innovation, as diabetes is among the world’s most widespread chronic diseases. The industry’s goal is to develop a non-invasive platform as a replacement for today’s prick-and-test approach to measuring blood sugar levels.6. Pan-European organizations are working to coordinate efforts and investments in digital healthcare. The European healthcare sector is large and diverse, as shown in the following slide provided by the organization MedTech Europe. Every country has its own legal framework, infrastructure, and health service structure medical technology companies must navigate. More than 27,000 medtech companies are located in Europe – 95% of them small to medium size businesses. Michael Stubin and Patrick Boisseau from MedTech Europe said concerted efforts to coordinate research and structural changes across the EU are underway to help spur medtech innovation and, with healthcare accounting for 10% of Europe's GDP, drive more market opportunity. This table shared by MedTech Europe points to the wide range of medical systems by country across the continent. Next StepsIs your company applying microelectronics innovations to change the way we approach medical care? If so, you’re invited to share your mission, roadmap and collaboration needs at a future MedTech Initiative Forum. For regular updates, join the MedTech interest list. In addition to the SEMI MedTech Initiative, our Nano-Bio Materials Consortium (NBMC) brings together scientists, engineers and business development professionals from industry, government and universities to collaboratively initiate research and development of electronic technologies to improve human performance monitoring and performance augmentation. Find out more at www.semi.org/collaborate/communities/NBMC.Michael Ciesinski is the Vice President of Technology Communities at SEMI.

It’s official.The first autonomous vehicle has been verified for operation on the open road in Asia with no traffic restrictions. And this is no corner case, flash-in-the-pan technology. The white 4-door minivan’s modular software can be integrated into all manner of vehicles including cars, trucks and buses. More promising still, the minivan – proven roadworthy after more than 1,300 miles of testing – will lead not only to an upgrade of Taiwan’s automobile electronics industry but to groundbreaking smart transportation service models.Imagine, for example, hopping a driverless shuttle to the hottest attractions in Hsinchu City, Taiwan such as Big City, Hsinchu Cheng Huang Temple, 19 Hectares Grassland, 17KM Coastline Scenic Area and Siangshan Wetland. The autonomous ride could become another transportation option sooner than you think.“We have every intent to make available self-driving sightseeing shuttle services soon,” said Chih-Chien Lin, mayor of Hsinchu City. “The services will be our first step to substantially improving the traffic flow, highlighting the unlimited applications associated with autonomous vehicles.”Bearing the license plate number Taiwan No.0001 – the first issued for an autonomous vehicle in Taiwan – the minivan is an early but important advance in the region’s autonomous-driving technologies under a new initiative led by the Industrial Technology Research Institute (ITRI), which developed the test vehicle’s software, and the Hsinchu City government. SEMI president and CEO Ajit Manocha joined Hsinchu City mayor Chih-Chien Lin and ITRI vice president Pei-Zen Chang to promote the initiative at SEMICON Taiwan 2019 in the run-up to its launch during an October 22nd press conference in Hsinchu City. Taiwan luminaries attending the press conference were (L-R in photo below) Terry Tsao, SEMI Chief Marketing Officer and SEMI Taiwan President; Jwu-Sheng Hu, Vice President and General Director, ITRI Mechanical and Mechatronics Systems Research Laboratories; Der-Sheng Lin, Deputy Director General, MOEA Department of Industrial Technology; Chih-Chien Lin, Mayor of Hsinchu City; Pei-Zen Chang, Vice President, ITRI. ITRI and Hsinchu City government officials kick off the next phase of Taiwan’s smart transportation initiative in an October press conference near Nanliao Fishing Harbor, Hsinchu City. “This milestone in self-driving technology is a shining example of public-private partnerships in action to advance smart mobility and dovetails with SEMI's work building communities consisting of the automotive and microelectronics industries, government, and academia for collaborative innovation,” said Terry Tsao, SEMI chief marketing officer and SEMI Taiwan President. “We are thrilled to have joined ITRI and the Taiwan government in promoting the extraordinary power of technology to make automobiles and cities smarter.”Emmy Yi is a marketing specialist at SEMI Taiwan.

Sandia National Laboratories just finished updating equipment in its microelectronics fab, marking the completion of the first phase of a 3-year fab upgrade program. The transition from 6-inch to 8-inch wafer sizes will align the Department of Energy national lab with industry standards to ensure easier access to tools, spare parts and raw materials.Sandia is a prestigious member of the SEMI Fab Owners Alliance (SEMI FOA), an international group of semiconductor and MEMS fab managers and industry suppliers that meet regularly to solve common non-competitive manufacturing issues and improve their business results. SEMI spoke with Michael Holmes, senior manager of microfabrication at Sandia, about its approach to revitalizing the fab while developing new production processes and technologies.SEMI: What were the main challenges in moving into production with 8-inch wafers?Holmes: The goal of the conversion is to reestablish our 6-inch production processes on 8-inch wafers including our radiation hardened 350nm CMOS and MEMS technologies. This requires tuning hundreds of interrelated parameters to get the same end result as before but with different equipment and at a larger scale. In addition, during the conversion we are developing a new 180nm radiation hardened CMOS production process and re-establishing research work on 8” in our silicon photonics and ion trap technologies. Modifications to the facility have also been required including raising the ceiling to install the new implanter and relocating our gowning area to facilitate installation of new CMP tools. In addition to converting our Silicon fabrication facility, we are also converting select equipment in our compound semiconductor facility. We are one large team working toward these goals.SEMI: Were there any roadblocks in sustaining production of the 6-inch wafers while planning and implementing processes for the upgrade to 8-inch?Holmes: Six years of planning ensured the conversion would not affect production of components needed for national defense. This planning window was required to ensure production commitments were completed in advance of conversion start in August of 2018 and return to production for commitments starting in July 2021. This period provides time to complete the hardware conversion and steps review and requalify the production line to ensure products made using the new equipment are identical to ones produced by the old equipment. The hardware conversion phase completed on schedule and the fabrication of prototype and research components on 8-inch started in November of 2018.SEMI: Can you shed some light on the development of gold antennas that promise to improve the thermal infrared radiation capabilities in systems?Holmes: Sandia developed a new infrared detector design that breaks away from relying on thick layers of detector material and instead uses a subwavelength nanoantenna – a patterned array of gold square or cross shapes – to concentrate light on a thinner layer of material. This design uses just a fraction of a micron of detector material, whereas traditional thermal infrared detectors have a thickness of 5 to 10 microns. The nanoantenna-enhanced design increases the amount of an infrared radiation a detector can see while also reducing image distortion caused by background noise. It also allows for the invention of new detector concepts.SEMI: Sandia is known for producing high-reliability components. Several SEMI FOA members have customers in the automotive domain, where reliability is critical. Do you have any advice for them on their path to high-reliability, zero-defect systems?Holmes: High-reliability microdevices at Sandia’s MESA facility are paramount. A structured quality program is rigorously realized in each facet of the production process. Our processes and design rules are constructed around reliability, and we extensively leverage in-line metrology and electrical test to validate devices throughout production. SEMI: Are there any examples of how the FOA peer-to-peer dialogue and knowledge sharing helped in your upgrade from 6-inch to 8-inch?Holmes: Sandia is new to the FOA. Our initial interactions have been very valuable, and members have shared insights into metrics and process improvements that will benefit MESA moving forward. Relative to the 6-inch to 8-inch conversion, as part of our planning process, we did engage other foundries within the FOA to solicit feedback and lessons learned.The mission of the Fab Owners Alliance is to provide value to the fab management and operations community through collaborative platforms for device makers and solution providers.Nishita Rao is marketing manager for technology communities at SEMI.

As 2019 draws to a close, the SOI Consortium would like to recognize members that have joined over the course of this year: Applied Materials, Analog Bits, Antaios, Silicon Catalyst and SmarterMicro. And as we start off 2020, the Consortium is pleased to welcome Thalia Design Automation. Here’s a bit of SOI-ecosystem background for each of them: Applied Materials: AMAT has a long history in the heart of SOI ecosystem – in fact they’ve been working with SOI wafer-leader Soitec for over 25 years. AMAT is leading supplier of SOI-related process equipment, with systems for ion implantation, epitaxial deposition and chemical mechanical polishing (CMP). In fact their ion implanters are a key enabler to what became and is Soitec’s industry-leading Smart CutTM SOI wafer manufacturing process. And of course AMAT equipment is used to make virtually every chip in the world, so their breadth of vision as a Consortium member is clearly a wonderful addition. Analog Bits: SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. Analog Bits has been revolutionizing SERDES IP by drastically cutting the power it pulls. In fact in porting the IP to the FD-SOI processes of leading foundries, Analog Bits has laid claim to the industry’s lowest-power SERDES IP. They have been an active and generous sponsor of SOI Consortium events for several years now. Antaios: Antaios is a start-up in advanced memory technology. They are developing Spin Orbit Torque (SOT) non-volatile (NV) memory IP that is ultra-fast, durable, and reliable. The SOT-MRAM was proposed by SPINTEC and is now being developed by Antaios for nodes below 28nm where an STT-MRAM process is available. It is writable/readable in the nanosecond time scale making it particularly promising for cache memory applications (such as SRAM) for IoT, edge computing, AI and high-performance computing. SOT is an MRAM flavor that Antaios explains solves the STT-MRAM tug-of-war between endurance, speed and retention, thereby addressing both eFLASH and eSRAM replacement. Silicon Catalyst: Silicon Catalyst is the world’s only incubator focused exclusively on accelerating solutions in silicon. They address the challenges faced by startups while guiding them from concept to product, providing a path to funding, free access to tools, testing and shuttle runs, along with advice on proper corporate governance and strategic execution. The 21 startups admitted since 2015 to the incubator are developing innovative solutions in a variety of areas including energy harvesting, wearables, silicon photonics, memory technology, loT, high performance computing, artificial intelligence, machine learning, wireless communications, and biomedical devices. SmarterMicro: SmarterMicro is a fabless RF chip company. Their portfolio includes switches, power amplifiers and front-end modules FEMs. SOI technology provides the ideal platform for the software-defined RF front end module. They presented at several SOI Consortium events in Shanghai in recent years. Their 2018 presentation, RF-SOI in 5G Era and their 2017 presentation Reconfigurable RF PA and FEM with RF‐SOI, are available from our website. Dr. Li Yang of SmarterMicro received an SOI Consortium Industry Achievement Award in 2018 for outstanding contributions to RF-SOI, particularly citing the reconfigurable FEM, which debuted at Mobile World Congress in 2019. Thalia Design Automation: Thalia’s Re-use Platform-as-a-Service (RePaaS) solution combines an innovative methodology, advanced design automation technology and experienced analog engineering resources. It helps analog IP providers to maximize re-use of their existing product portfolio, to create new product variants quickly and easily, and to adapt their designs for manufacture using any semiconductor foundry service. Thalia’s AMALIA™ EDA design tools comprise an intelligent analog design optimisation automation toolset. The company has worked on multiple FD-SOI projects with body biasing, some of which are described in a recent company blog (read it here). Interested in joining this dynamic organization? For information on how your company can become part of the SOI Consortium, visit our About Us page, then use the Contact page to make your request.

The SOI Consortium’s China 2019 event ran for two days, and it’s taken four (!) posts to cover all the presentations. In this final post we cover the afternoon RF-SOI sessions, which were dedicated to the China RF-SOI ecosystem and the RF value chain. In case you missed them, our previous posts recapped: 1. major keynotes from both the FD-SOI and RF-SOI days; 2. the FD-SOI presentations; 3. the morning sessions of the RF-SOI day; and 4. (this post) the RF-SOI day afternoon sessions. As we noted in Part 1 of our RF-SOI coverage, there were over 500 attendees for the RF-SOI day. And impressively, the room was still packed right through to the very end of the afternoon. Read on! SESSION 2: CHINA RF-SOI ECOSYSTEMSuzhou HunterSun Electronics: Super Opportunity for Integrated RFFE (“Jacky” Yujun Ding, COO)This talk had two parts. First, how is 5G changing the world, and second, what are the RFFE opportunities? He cited IHS data indicating that 5G will create tens of millions of jobs. New products include NB IoT, cellular V2X, as well as traditional PC/tablets and smart phones. But you still need to cover 2/3/4G with 5G. Major growth will happen in 2025-27. In terms of opportunities for RFFE, you've currently got 550mm2 going for $8; in 5G, you'll need 600mm2, but it will cost $16. You need RFSOI for filters and antenna switches, which are in high demand. Parts of the supply chain have no China players. Revenue for BAW is higher than SAW, but there's more SAW. He sees the industry moving heavily into integrated FEM (versus chip-on-board). He finished by itemizing different parts of the RFFE, indicating where the opportunities are (citing some data from Yole), with a special emphasis on integrated products for Chinese companies, with continued investor confidence. SmarterMicro: RF-SOI: Key Technology of Smart Connection (Yangyang Pen, Director) RF-SOI is an enabler of smart connections. However he sees GaAs as better for power, so SmarterMicro has a solution combining RF-SOI and GaAs. They've developed the world's first mMTC RFFE for high-performance upgrades on a single die and software reconfigurable. He notes that for IoT, lifetimes will be longer than 10 years, and that terminals are becoming more powerful. CanaanTek: Critical SOI CMOS Blocks in the 5G NR Sub-6GHz RF Front-End Architectures (Wayne Ni, CTO Board Chairman) CanaanTek is a fabless company working in consumer markets, with switches, tuners and LNAs in SOI-CMOS. He wants to capture 10% of the market with a focus on sub-6. The antenna/tuner is a must, and they've developed solutions for switches here. The figure of merit is RonCoff. He showed a product roadmap on SOI-CMOS. Xpeedic: Innovative EDA Solutions to Enable Differentiated RF-SOI Designs (Feng Ling, CEO)RF-SOI is growing, but there are still design challenges in process, models, filters and packaging. To design a good front end, you need better models and filters. People think passives are easy, but you need accurate models here. Xpeedic has developed design flows that include the effects of packaging early in design. Their products include IRIS, iModeler and Metis (for packaging). They've also introduced substrate modeling in partnership with CWS in France. The product is called SiPEX: it can address linearity in switch or PA designs. You need accurate substrate models to do this. Customers indicate they're seeing big improvements as well as reductions of 25% in chip area. IDP filters is another place they're working, to provide RF filters to fabless IC or module companies. No single filter technology can fit all the needs – IDP is one of them, so they have a broad portfolio of IDP filter technologies. He closed by saying that especially in China, the SOI ecosystem is really growing. SESSION 3: RF VALUE CHAINTowerJazz: Specialized RFSOI Foundry Technology to Support Rapid New Product Development (Paul Hurwitz, Director of RF Technology Development)This presentation gave a full overview of what TowerJazz offers in terms of RF-SOI foundry services with its fabs in Isreal, the US and Japan. What's new in 2019 is a diversifying of 200mm and 300mm. 200mm is best for power handling (for infrastructure/basestation antenna tuners and switch power handling, for example). 300mm is best for SW and LNA integration and higher digital densities. They've got new SOI models for the latest technology generations, and physics-based modeling of RF breakdown for accuracy. With more die being flipped, they needed new substrate modeling. For LNA and switch integration in 300mm, they invested in RF modeling. They also have an in-house MPW (multi-project wafer) program. He noted that customers in China are moving quickly in response to their customer requirements. Okmetic: Tailored Silicon Substrates for RF Applications (Atte Haapalinna, CTO)Okmetic Oy is a niche player in the substrate materials market, with specialties in sensors and MEMS, where they are the market leader. Now part of China’s NSIG group, they are expanding their manufacturing facility in Finland. In this presentation, their CTO talked about their current offerings as well as what they have under development. They do 150-200mm wafers, with a special emphasis on thick SOI. In terms of silicon substrates for RF, ultra-high resistivity is key. Their wafers are also used in IDP – integrated passive devices – for RF and acoustic filters. They are continually improving their high resistivity Magnetic Czochralski (MCz) silicon wafers, and are developing substrates for RF passives for automotive V2X. For RF beyond 6 GHz, they are looking at customized high resistivity silicon wafers for mmWave with researchers and customers. For sensors, they do SOI wafers with built-in cavities. Incize: RF SOI Ecosystem – History Challenges (Mostafa Emam, CEO)The world is exceeding expectations in terms of data usage. While the CAGR for devices is 27%, for data it’s 46%. Therefore each device needs to be faster and more power efficient. Incize recognizes RF as an art, with each piece hand crafted. But artists need to see the whole picture: at Incize, they help 17 companies – including wafer suppliers, foundries and fabless – see that big picture, especially in measurement, characterization and modeling for RF. For wafer suppliers, they do very high-power and very precise on-wafer testing to determine things like intermodulation distortion and substrate interference. For foundries, their specialty is in RF switches, for whom they do harmonics testing and thermal noise management. With those insights, Incize foundry customers have drastically increased the performance of the RF chips they’re manufacturing on trap-rich, high-resistivity SOI wafers. Meanwhile, Incize is also preparing PDKs for future potential substrate generations including GaN-on-Silicon, silicon-on-porous, and new contactless testing techniques for piezoelectric-on-insulator (POI – used in filters in 4/5G). “There’s a really big business opportunity for RF-SOI,” concluded Emam, “and room for everyone.” Cadence: SOI Technology in Intelligent and IoT/Vision/AI Systems (Jonathan Smith, Senior Director)Cadence does SOI enablement at advanced nodes. Smith shared three recent success stories. First, there’s the Musca-S1 test chip they did with Arm, Samsung and Sondrel this past spring. Second, there’s the Tensilica DSP for automotive vision on GlobalFoundries’ 22FDX, which uses 1/10th of the power of existing solutions and was demonstrated at CES. And finally there’s the i.MX line from NXP. In recent news, there’s a new version (18.1) of Virtuoso RF. Though it’s been on the market for 30 years, they’ve added advanced methodologies so that system design and analysis are on the same platform. They’ve also announced National Instruments’ analysis solver, the Clarity 3D solver for next-gen 3D solutions, the integration of multiple electromagnetic (EM) solvers, and advance SiP options. Silvaco: Xena-IP Management Infrastructure for the SOI Ecosystem (Babak Taheri, CEO)Every multi-core SoC today has as many as 200 IPs, if not more. How do you manage that? Tracking and traceability of IP is complicated but important. For IP providers, how do they track where its being used? And for IP consumers, they need to know what they’ve used and where. What’s required is an IP management system to keep track of the different functions and different concerns. Today’s tracking systems don’t talk to each other. Silvaco’s Xena IP management solution organizes all IP data, accounts, products, contracts, devices, support, compliance and reporting. For compliance in particular, they do IP “fingerprinting” and “DNA analysis”, which they’ve patented. The fingerprint is a digital representation of the IP: it’s not just software. It is secure, and can’t be reverse engineered. It’s not a tag: a tag is inserted into the IP, whereas fingerprints are extracted. DNA analysis flags discrepancies and quickly identifies where they are and which files to look in. Xena works in the cloud, enterprise systems or hybrids. The SOI ecosystem will be hearing a lot more about this. ~~ Please note that the China event presentations are all available on our website to anyone whose company or organization is a member of the SOI Consortium.