Technology and Trends

When COVID-19 hit the semiconductor industry, SEMI members were confronted with new hurdles to keeping their employees safe and their operations running uninterrupted. We quickly assisted our global membership around the globe by providing a forum for collecting member insights on best practices for operating and safety procedures, supply chain issues and sentiments on business impact and recovery. That forum took the form of surveys we launched in March 2020. We shared the results with the larger SEMI member community to help them cope with the evolving impacts of the pandemic on their businesses. Following is a summary of our 4th survey, issued last month. Regional and Sector Representation Nearly 40% of our respondents represented companies headquartered in North America. Of the respondents, 10% each were from companies headquartered in Taiwan and China; 5% from Korea, 13% from Japan and 20% from European and Middle Eastern members. The largest share of respondents – 40% – develop equipment for semiconductor fabrication, assembly, and test; 21% supply materials to the microelectronics industry; 14% are device makers; 6% supply software and design services; and 3% are OSATs, EMS suppliers or ODMs. Measures Member Are Taking to Continue Operations The May survey found that almost no companies ceased production for any significant length of time. In order to continue operations, companies instituted social distancing and masking requirements, temperature checks, schedule changes, and some contact tracing, all to varying degrees, as shown in Figure 1. In addition, several companies implemented some combination of mandatory testing, bump sensors, air purification and site capacity limits and sequestered foreign workers in separate housing for required quarantines after travelling. Figure 1 All of these measures are routinely discussed during the regular SEMI EHSS COVID-19 Working Group calls. That group consists of facilities, HR managers and others tasked with ensuring safety monitoring and compliance at member companies. Company Vaccination Policies With the pace of vaccine rollouts varying widely around the world, only 5% of respondents are requiring all workers to be vaccinated before returning to the office, and 12% have not yet considered a vaccine policy. The majority of companies are encouraging but not requiring employee vaccinations, and 26% leave the decision to the individual employees. Figure 2 North American companies constituted the majority of the required and encouraged vaccination categories. In Europe, companies fall into the employee decision or encouraged categories but none require vaccinations. Japanese companies primarily leave the vaccination decision to employees, while Chinese companies are split among the required, encouraged and employee decision categories. Clearly, these guidelines are not required by law in each region, but instead fall to employers and local policymakers. Member Readiness for Digital Transformation A solid majority of members reported they have invested in the adoption of digital transformation technologies and practices, though only about 14% expect to continue their digital investments in the coming year. Many respondents have deployed virtual meeting software and have implemented or plan to put in place virtual reality tools for remote diagnostics and predictive modeling for semiconductor manufacturing. Figure 3 Location by Functional Group in Returning Employees to Sites Not surprisingly, manufacturing and distribution staff that could work from home during the pandemic are back on site, and respondents signaled that R D and engineering groups will soon end their remote work, following by finance and procurement. Sales and marketing show the highest percentage of staff working remotely, with sales having the highest number remaining remote for some time to come. Figure 4 Resilience to Further Economic Uncertainty Of the 274 companies responding, 229, or 84%, feel more resilient in the face of further economic uncertainty after their response to COVID-19, though continuing supply chain issues and raw materials shortages ranked among their top concerns, as did rising customer demands, their ability to increase capacity utilization rates, and the increasing demands on employees and facilities overall. Figure 5 Many thanks to all survey respondents over the past year! We’ll keep you up to date on results of future surveys. For more details on the SEMI EHSS COVID-19 Working Group calls, visit the SEMI COVID Response Site. To watch the recording of our most recent CEO Webinar – Surging Chip Demand, Digital Transformation, and the Pandemic – What’s Next? – click here. More than 750 people attended the June 2nd webinar sponsored by SEMI members Brooks Automation, Hitachi, JCET, KLA and TEL. Heidi Hoffman is senior director of Technology Communities marketing at SEMI.

Traditionally, defect classification is done manually by operators or using Automated Optical Inspection (AOI) machines, often leading to classification inconsistencies. Also, rules-based AOIs may at times be unable to fully satisfy project requirements due to the rigidity of inspection recipes. SixSense – Breaking the Status Quo with Artificial Intelligence Enter SixSense, an AI-powered defect classification software platform that has been making breakthroughs in defect detection and classification for semiconductors to make manufacturing smarter and more efficient. Founded in 2018, SixSense has already amassed a wealth of experience and chalked up a number of successes such as automating the manual image classification process, reducing manufacturing false rejects, and capturing escapees. Infineon Technologies and GlobalFoundries were amongst the early adopters of SixSense’s platform: classifAI. With Infineon, classifAI has allowed over-rejection rates to be precisely quantified. classifAI – Simple UI, Easy Usage, Powerful Models As a UI-based assistive software platform, classifAI, SixSense’s automated defect classification platform is built with the defect and yield engineer in mind. SixSense takes care of all the back-end complexities – such as coding, algorithm modelling and deployment – to enable end users to get started and use the platform with a simple GUI. The simplified end-to-end AI pipeline offered on the platform includes data labelling to make data AI-ready, model training, and model testing. Ultimately, models are deployed on the production floor for 24/7 inferencing of hundreds of millions of images every year, at scale, across processes, tools and sites. Machine learning models built by the SixSense team have seen strong results, with model accuracy of up to 98% in certain use cases. Track Record of delighting IDMs, Foundries and OSAT Customers SixSense has consistently solved visual inspection problems and enabled the success of IDMs, foundries and OSATs since its inception. The AI technology has helped a range of customers across 100mm-300mm wafer standards, both pure silicon and compound wafers, and caters to specific end-use market requirements such as RF and automotive. Partnerships between startups and established manufacturers are key to actualizing the value of AI in manufacturing. “Our collaboration with AI startup SixSense has enabled us to explore opportunities in yield gain, improving cycle time, and real-time monitoring of process shifts,” said Dato’ Tan Soo Hee, Executive Vice President, Global Backend Operations at Infineon Technologies Asia Pacific. “SixSense has been very attentive to the needs of our engineering team, addressing project requirements using a customer-first approach evident in the design of the intuitive software platform,” said Melvyn Peh, Principal Engineer, Automation-Scan-Pack, Infineon Technologies Asia Pacific. The intelligent annotation module is one of many offered by SixSense, which uses AI to train AI and accelerate the data annotation process by focusing on the semiconductor-specific requirements. Another valuable module in classifAI is advanced analytics that capture the heatmap for defect distribution on the images. Images are stacked on top of each other, with the location of defects aggregated to provide the defect heatmap. Through this, systematic failure patterns were identified that allowed defect engineers to zero in on key sources of failure and assist in root-cause analysis. Infrastructure – Scale Fast, Adapt Quickly, Accelerate Value Creation In the dynamic world of technology, machine learning and AI projects must meet changing infrastructure demands. A cloud-first approach is often favored for the plethora of benefits it offers. “We’re looking forward to a great partnership with SixSense, treading together hand in hand exploring fresh ideas and possibilities,” said Manju Jalali, Vice President of digital manufacturing at GlobalFoundries, who oversees the company-wide roll out of classifAI. For use cases where on-premise deployments are preferred, SixSense offers such options for infrastructure integration, satisfying all possible infrastructure requirements in the market. Contributing to a vibrant innovation ecosystem SixSense was mentioned by Singapore’s Deputy Prime Minister Heng Swee Keat during an event that marked Infineon’s 50th anniversary in Singapore: “I am heartened that Infineon will be investing more than $27 million over three years on an AI initiative in Singapore. Under this initiative, Infineon Singapore will be partnering academia, industry, and local startup SixSense AI to develop new AI solutions and courses.” Explosive Growth of AI in Chip Manufacturing According to a McKinsey Company report, AI contribution to semiconductor company earnings is projected to rise to between $85 billion and $95 billion per year in the coming years. SixSense has been taking great strides in creating value for their semiconductor customers. “SixSense offers tremendous value in a high-growth vertical in the semiconductor industry, marrying the latest deep learning algorithm with the compute power of the cloud,” said Rajan Rajgopal, CEO of DenseLight Semiconductor. “This leads to faster root-cause analysis that helps reduce the cost of non-conformance and improve quality.” Dominic Teo is Enterprise Business Development Representative at SixSense. He can be reached at [email protected].

What does it mean to identify as LGBTQIA+ in the semiconductor industry? It’s an interesting question to ask, but a difficult one to answer. Because we live in a world in which cisgender heteronormity is assumed, it’s possible to self-identify as LGBTQIA+ without sharing that information publicly. Coworkers and managers might not even realize that their colleague or employee is gay, lesbian, transgender, non-binary or other. Unlike other minorities, notably people of color, LGBTQIA+ people may choose to keep their identities invisible.As I began outreach for this article, I recognized that some people might not want to expose a potential vulnerability to both their co-workers and a broader global audience of SEMI members, so I tried to make them feel more comfortable. I told them I’m a lesbian. I said that I’d send content for their review before publishing. But I quickly discovered that wasn’t enough, despite sweeping cultural and legal advances around LGBTQIA+ attitudes and identity. According to a 2020 Gallup Poll, 5.6% of U.S. adults now identify as LGBTQIA+, up from 4.5% just three years ago. In 2004, Massachusetts became the first U.S. state to legalize same-sex marriage, and in 2015, the U.S. Supreme Court made same-sex marriage legal in all 50 states. The semiconductor industry has been historically conservative. The times, however, are changing. Large chip companies such as AMD, Intel and Lam Research actively support diversity and inclusion efforts across minority groups, including LGBTQIA+, and that’s a good thing, but is it enough? And if not, what actions can SEMI members take to help LGBTQIA+ people in semiconductors feel safe enough to choose visibility?According to Antoinette Hamilton, global head of Inclusion and Diversity at Lam Research, more than 46% of LGBTQIA+ employees in the industry aren’t out in the workplace. That tells us there’s still work to be done, a challenge that Lam is embracing. With its Pride employee resource group (ERG) leading the way, partnerships with organizations such as PFLAG and Out Equal, and recruitment efforts made through organizations such as Out in Science, Technology, Engineering, and Mathematics (oSTEM), Lam has earned a score of 100 on the Human Rights Campaign Foundation’s Corporate Equality Index and was named one of the Best Places to Work for LGBTQ Equality.“At Lam, we understand the importance of empowering employees to bring their authentic self to work,” says Hamilton. “We believe when employees feel valued and included, each person can reach their full potential.”Back in 1992 when Intel paid to relocate Judi Goldstein, her partner and their son from New Jersey to Oregon, mainstream cultural attitudes toward gays and lesbians were very different. According to a June 1992 Gallup poll, only 48% of Americans thought that “gay or lesbian relations between consenting adults should be legal,” with 44% saying they should be illegal. A May 2020 Gallup poll recorded a dramatic shift in attitudes, with 72% affirming the legality of same-sex relations and only 24% opposed.By the late 1990s, Intel had extended domestic partner benefits to same-sex couples. “I registered my partner – now my wife – and our son, and realized that from then on, my whole family would have health insurance through Intel,” says Goldstein, who identifies as a gay woman and uses she/her pronouns. “Both relocating my family and providing family health coverage solidified my attachment to Intel, which was way ahead of other companies at the time.”By 1995, Goldstein became one of the first members of IGLOBE, Intel’s ERG for LGBTQ+ employees. Since that time, she’s observed further progress at Intel, first with the addition of gender identity and expression to Intel’s anti-harassment policy, and later with the inclusion of gender-neutral bathrooms at all major US sites. And advancement didn’t stop there.“We now have international IGLOBE chapters, a celebration of Pride Month in June, company support for the Equality Act and other legislation, a provision for transgender health benefits, and the launch of Self-ID efforts in 2017,” she says.From her start as software engineer more than 32 years ago to her current positions as director of the Open Source Audio and Security Engineering teams, Goldstein has played an instrumental role pioneering new technologies and mentoring other engineers at Intel – in addition to serving as a role model for LGBTQIA+ employees coming through the ranks. Now a grandmother with a five-year-old granddaughter, Goldstein lives in Oregon with her wife of more than 30 and two dogs. Location, Location, LocationAs social animals, we tend to value safe and welcoming places to live. When you’re LGBTQIA+, this may mean moving to an urban area that is more likely to embrace diverse orientations and cultures.After getting his master’s in astrophysics, Chuck Chung had a decision to make. Remain in the same field, which would limit his options on where to live, or get a doctorate in engineering, which would expand them.“In the ‘90s when I was making this choice, things were very different, and I knew that where I worked and lived would have a huge impact on how open I could be,” said Chung. “While I would have loved a career in astrophysics, I realized that engineering would be a more practical choice because I was more likely to find work in a city.”Both personally and professionally, engineering has proved a good choice for Chung. He’s lived in San Francisco and Silicon Valley for the past 18 years, where being out in the workplace is rarely an issue. “I compartmentalize my personal and professional lives when necessary, such as when business colleagues who are overseas talk about their families in casual conversation. Most of the time, though, my identity as a gay man is a non-issue, and I work for a company that really cares.”From his pioneering work in MEMS and genetic sequencing to his current focus on the next generation of microarchitectures at IBM, Chung has long thrived. Now, with a new book on MEMS Product Development – co-authored with two other Ph.D.’s, Alissa Fitzgerald and Carolyn White of A.M. Fitzgerald Associates – the best days of Chung’s career may still be ahead of him. He lives in the Bay area with his husband and their two children.Kunal Garg’s identity didn’t influence his career choices because when he started in semiconductors, he wasn’t out to himself or others. A few years into his engineering career at his former company, Garg realized his identity as a gay man at a time when the national discussion about same-sex marriage was at its apex – leading to some uncomfortable situations at work. “As some of my colleagues and managers openly debated same-sex marriage, they seemed oblivious to the fact that there were LGBTQIA+ people at work,” says Garg. “I knew then that I wanted to steer such conversations in a way that would feel safe and inviting for people like me, who work in this industry while being true to their identities.”Once he’d come out to his family and friends, particularly after he married his husband, Garg wasn’t willing to stay silent at work. “Although it took courage and internal struggle to come out to colleagues, my identity as a gay man wasn’t something I wanted to hide or deny anymore,” he says. “Some people laughed when I mentioned my ‘husband.’ The idea that their colleague, an engineer, an Indian immigrant, a man, could be gay and married to another guy was so foreign, it was almost laughable. Luckily, this didn’t stop me from being myself at work, and over time, these types of conversations became very rare.”Nonetheless, Garg looked around for ways to be part of the LGBTQIA+ engineering community. When he moved to AMD in Austin, he wanted to start with a clean slate. “When my manager called to invite me to join his team at AMD, I casually brought up the fact that my husband was going to need to start looking for a new job in Austin. And, very casually, he asked me what my husband did for a living, and we went on to discuss how Austin would be a great city for us to live in,” says Garg. “The fact that this was such a normal conversation was a big factor in my decision to join AMD.”Soon after starting as a design engineer at AMD, Garg found that LGBTQIA+ engineering community for which he’d been searching. He joined AMD’s Pride ERG, a group that he now chairs. “Being a part of this ERG has been transformational for me on a personal level and has allowed me to connect with my fellow engineers and people in my industry, beyond our mutual love for science and technology.”Become a change agentWhile some chip companies actively promote inclusion and diversity of LGBTQIA+ employees, others still have a long way to go. SEMI and the SEMI Foundation are uniquely positioned to help advance LGBTQIA+ equity issues in the microelectronics industry. "The SEMI Foundation is committed to promoting Diversity, Equity, and Inclusion (DEI) in our industry for the benefit of our workers and our member companies,” says Shari Liss, executive director of the SEMI Foundation. “We are designing programs for human resources departments, company leaders, and DEI allies to make the case for stronger DEI practices that will attract, retain, and promote LGBTQIA+ individuals and other underrepresented groups in our industry. We will soon publish SEMI's Roadmap to Diversity, Equity, and Inclusion and DEI Toolkit, which will contain tools to help companies strengthen their workplace cultures so everyone – including those that identify as LGBTQIA+ – will feel welcome, and will be able to do their best work."“If we want to truly see the semiconductor industry flourish on a global level, we need to push for equitable treatment of LGBTQIA+ and other minority employees,” says Garg. “SEMI can help by educating industry leaders, especially in countries outside North America and Europe, on how diversity and inclusion through policy are vital to their sustained productivity. These workshops and trainings should be data-driven to encourage companies to hire more LGBTQIA+ employees and to create policies that promote the well-being of all employees.”It’s not just at the company level or the industry association level that matters. Just as individuals are necessary change agents in proliferating greater equity among women and people of color, they’re also needed as allies of LGBTQIA+ people.“Like so many of us, I’d love to wave a magic wand to end discrimination based on gender identity or sexual orientation, but like any cultural shift, most change comes in small steps, not in giant leaps,” said Karen Lightman, executive director, Metro21: Smart Cities Institute – Carnegie Mellon University. “Fortunately, it’s easy to help make those small steps by becoming an ally to LGBTQIA+-identified people. When you see an injustice, don’t stay silent. Use your voice. There’s transformative power in that act alone. As one step, I’ve started using my pronouns when I introduce myself and now include them in my digital signature. It’s an easy way for me to express that I am an ally to LGBTQIA+-identified people.”Help us make the change. Use your voice. Get involved. Encourage your company to advocate for LGBTQIA+ inclusion and diversity.Maria Vetrano, principal of Vetrano Communications, is a PR consultant at SEMI Foundation.

Adnan Hamid, CEO, founder and visionary of Breker Verification Systems, an ESD Alliance member based in San Jose, Calif., once described his job in chip design verification at AMD as “breaking things.” When it came to naming his startup, Breaker was a natural choice. After some consideration, the “a” was dropped and the company became Breker. Now Hamid is breaking the most complex semiconductor designs and Breker, moving from a startup to a scale-up company, is a noted part of the functional verification space. Smith: Why does verification continue to take the most amount of time in a project cycle? Hamid: The project cycle for semiconductor design has changed. Design abstraction has been raised to a much higher level than the days when developers were connecting logic gates. Today’s developers are typing functions that don’t include lower-level implementation details. Designs incorporate more blocks of reusable IP. Both reduce design time. Meanwhile, designs are getting bigger with more blocks of IP stitched together, all in need of testing. As design complexity grows, the amount of testing and verification increases as a square of design effort. One block requires one functional verification effort. Four blocks of IP mean up to 16 functional interactions require verification. While design is moving up the abstraction level, that’s not the case for verification, where plenty of detail must be reimplemented. Verification has certainly evolved, but engineers still think at the level of independent stimulus, response and coverage, driving the need to allocate so much time for verification. Smith: Are chips targeting artificial intelligence and machine learning applications more difficult to verify? If so, why? Hamid: Yes, absolutely and it’s an interesting challenge, especially given that machine learning is based on massively connected processing element arrays. Attempting to verify the individual processing elements and the critical interconnects is complex. AI device arrays and, interestingly, verification test content operation may both be thought of as a mathematical graph of processing elements and interconnect. Their operation involves walking through the graph form to generate a result. Finding the optimum path through these arrays is key. To understand how these systems may be effectively verified, it is worth investigating planning algorithms. Originally proposed by IBM, these hold the key to this type of verification process. The AI- style algorithm starts backward at the end of the processing element array and tracks down the most optimal and likely paths through it. At Breker, we have used these planning algorithms extensively to drive our graph-based test content synthesis process. Smith: Does system integration require verification? Hamid: Yes, it does. In the past, most functional verification has been performed at the block level. However, with the increase in more specialized SoCs, functionality is spread across multiple blocks, as well as the software running on the processors, driving full system-on-chip (SoC) functional verification. In addition, new requirements such as security and safety must be validated. A system-level infrastructure such as cache coherency and power domain execution has become more complex and these must also be tested. The new frontier in verification is ensuring a fully operational SoC. Of course, given the size of these SoCs, hardware-assisted verification such as emulation is essential, and porting tests from block simulations to SoC emulations has become a requirement. This porting process is problematic and this in turn has driven portable tests, giving rise to the idea behind Accellera’s Portable Stimulus Standard (PSS), of which Breker was a major participant. Indeed, some companies are taking this to the next level by composing their system-level testbench at the same time as they commence SoC architectural design, and then developing the hardware design, software design and test content all in parallel, in the so-called “shift-left” manner. Smith: Is “shift-left” a growing trend that are you seeing in verification? Hamid: Yes. Shift-left is taking hold in hardware and software design, giving way to an increase in early test content composition. Then as individual blocks are finished and connected, their verification is driven from this same test content, saving a significant amount of time and effort. This is a huge verification and test generation change that was inevitable given the increased time-to-market constraints and SoC complexity. Figure 1: Shift-left is ushering in the next generation of SoC verification. Source: Breker Smith: As an entrepreneur, what advice would you give someone founding a startup or thinking about starting one? Hamid: Do not take the attitude “Build it and they will come.” My best advice for an entrepreneur or fledgling entrepreneur is to solve a specific customer problem, however narrow it might seem. Including services as part of a product offering and developing partnerships with other vendors helps with this and turns your company into a solution provider not a product developer. This is essential for getting the right products to market on time and within budget, and then ultimately scaling them across the market. The ESD Alliance and Accellera are hosting a two-part webcast series on the work-from-home experience titled Remote Work, Remote Chip Design: Building Chips During a Pandemic. The first panel, Wednesday, June 9, at 9:00am PDT, will feature a discussion led by Tom Fitzpatrick, strategic verification architect from Siemens EDA verification engineers through their experiences converting their home offices into verification test labs. The second panel in July will explore how executives managed a remote workforce and explain how they plan to bring employees back to physical offices. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

As we move through Q2 of 2021, it seems that the world is finally approaching normalcy. But I don’t believe our lives and businesses will ever be the same. Travel is unlikely to return to the same level as pre-COVID-19 for many years. I’m sure many companies will establish tighter travel policies and budgets as virtual conferencing has proven to be beneficial and cost-effective. Patients and doctors who were skeptical of telemedicine are embracing it, and although it’s not perfect, it has filled a needed gap. Online learning essentially happened over a weekend and will now be part of many curriculums and programs. All of these elements have spurred our semiconductor industry into a super cycle. Demand for chips is leading to an increased demand for semiconductor equipment. Semiconductor capital equipment expenditures in 2020 surpassed $63 billion and are forecast to top $70 billion in 2021. The secondary equipment market typically makes up about 5% to 10% of that. Our inquiries have definitely increased this year. With this in mind, I’d like to share some thoughts for the remainder of the year. Storage of Chipmaking Equipment Not New The semiconductor industry has been experiencing an equipment shortage for some time. It is difficult for original equipment manufacturers (OEMs) to support such a large variety of products and technologies. Some companies use equipment for manufacturing 150mm, 200mm and 300mm wafers. Fabs still run 30-year-old technology on 150mm wafers while the latest technology is manufactured on 300mm wafers. We’ve also seen new technologies like silicon carbide (SiC) being developed on these smaller wafer sizes. Unfortunately, some OEMs stopped making 150mm and 200mm some time ago and have only recently jumped back into the market. These OEMs have had to balance technological advances, pricing, and manufacturing capacity to meet this demand since their primary focus is on 300mm equipment. Third-party refurbished equipment suppliers have also experienced an increase in demand over the last several years. We see it increasing at all technology levels over the next three to five years. This translates to increased equipment pricing for both new and used equipment, as well as increased lead times. Growing Demand for Legacy Tools Many electronic products we use and are familiar with don't require state-of-the-art technology. For instance, cellphones, electric vehicles, wearables, monitors and industrial products still contain many chips manufactured on 200mm wafers using 200mm equipment. There are still approximately 200 200mm fabs worldwide and this makes up about 25% of all wafer capacity regardless of wafer size. These fabs manufacture analog devices, MEMS products, power management ICs, RF devices, discrete devices and sensors. We have also seen an increase in lead times for 200mm equipment. Typical lead times of three to six months have increased in some cases to one year or more. This situation has created a dramatic increase in chip making equipment prices and we do not expect much relief there. Many OEMs transitioned to 300mm equipment prior to 2010. Revenue and profit margins are much higher for them on 300mm equipment. 200mm manufacturing was supported by many third parties for a while. However, in 2016 we saw a resurgence in 200mm equipment, and at that time many OEMs began jump-starting their supply chains. It took some time for them to develop new supply chains, upgrade technology and in some cases hire newly trained engineers to support these new tool sets. All this costs money, which is why we will continue to see an increase in new legacy equipment pricing. Because manufacturers and products may not be able to support these prices, we expect the robust third-party ecosystem to continue. SurplusGLOBAL's Response to this Demand One of the advantages we bring to the secondary equipment market is our ability to recycle technology. We continuously search for opportunities to purchase large packages of tools from companies that are transitioning technology nodes, moving from 200mm to 300mm wafer size or changing product lines. We spend approximately $65 million to $100 million each year on purchasing equipment and in some cases storing it for the right customer. For instance, a memory company may be changing technology nodes and no longer needs its equipment. This use to happen on a predictable schedule. Instead of scrapping that equipment, SurplusGLOBAL purchases and stores it. Sometimes we only need to store it for one month before relocating it. However, in many cases, we store it for one year or more. We may power it on at a later date if it is in good condition. In some cases, we work with an OEM or third party to have it refurbished and ready for a new customer. In response to the need for more secondary market equipment, we have opened up additional offices in Japan and Singapore to stay close to and better support our customers in those regions. Finally, our biggest and most recent endeavor is building our Semiconductor Equipment Cluster, which opens in July 2021. Learn more about the SurplusGLOBAL Semiconductor Equipment Cluster. Emerald Greig is executive vice president Americas at SurplusGLOBAL.

Over the past 50 years, the field of engineering simulation has developed numerical methods that enable engineers to solve 3D physics problems faster, easier, with greater accuracy and more robust results. Finite element analysis (FEA), finite volume methods (FVM) and finite different time domain (FDTD) have increased solver efficiency while dynamic visualization techniques improve what is often called user-friendliness. Despite these improvements, certain challenges still remain. Specifically, simulation requires the simultaneous trade-off of: Accuracy of results Speed of results Ease of use of the workflow Robustness of the workflow Take, for example, mesh generation, the building block of multiphysics solutions. It is well known that using coarser meshes increases simulation speed but will result in loss of accuracy. Similarly, easy-to-use workflows with simpler meshes also reduce accuracy, and can introduce other issues: The simulation may not converge and the robustness fails. Ansys is exploring the use of AI/ML to solve all of these problems. Simultaneous Improvements Commercialization of AI began in the 1970s, but the field actually got its start a decade earlier with the development of rules-based expert systems. The simplest form of AI, these systems rely on curated human expertise to solve problems that would normally require human intelligence. We’d expect that AI/ML applications would be actively used in science and medicine, from streamlining drug discovery and advancing robot-assisted surgery to automating medical records that can be instantaneously accessed by providers anywhere in the world. But AI/ML is rapidly being successfully adopted by an increasingly broad range of industries and users. It’s helping consumer brands mine their social media to find out customers’ feel about their products (sentiment analysis), giving investors a leg up on stock trade opportunities (financial algorithmic trading) and enabling e-commerce owners to personalize offerings to online shoppers (recommendation engines). At Ansys, we can use AI/ML methods to automatically find the parameters of simulation to simultaneously improve speed and accuracy. We believe applying AI/ML will enable us to: Further improve customer productivity Augment simulation, including accelerating chip thermal solutions and developing a fluids solver that combines high-fidelity solutions in local regions with ML methods in coarse regions Optimize design space exploration Drive business-intelligence decisions such as resource-prediction needs for our solvers Combine data analytics-based and simulation-based digital twins to create accurate and fast digital twin hybrids In other words, we believe that AI/ML will help us narrow the gap between the ideal world, where time, effort, efficiency and results are perfectly balanced, and what happens in real life – and make productivity, ease of use, and accuracy a little less of a trade-off. To learn more about applying AI/ML to autonomy, click here. Prith Banerjee is Chief Technical Officer at Ansys, Inc.

Introduction Automated production in electronics manufacturing can produce high-quality products, but it might lead to a particular failure without human interventions. With the rapid technology development, such as the Industrial Internet of Things (IIoT), big data analysis, cloud computing, artificial intelligence (AI), many manufacturing processes can be more intelligent, and Industry 4.0 can then be realized in the near future[1]. Smart manufacturing adopts real-time decision-making based on operational and inspectional data and integrates the entire manufacturing process as a unified framework. Then, the future manufacturing process transforms cyber-physical systems digitally and responds to any uncertain situations proactively while ensuring higher efficiency. In Surface Mount Assembly (SMA) lines, equipment status and quality data can be collected via IIoT technology. Data-driven solutions, such as AI and machine learning algorithms, can be applied to diagnose abnormal defects and adjust optimal machine parameters in response to unexpected changes/situations during production. Collaborating with various SMT industry partners, the research team at the State University of New York at Binghamton (aka Binghamton University) developed a novel framework based on AI-based closed-loop feedback control and parameter optimization to implement a smart manufacturing solution in the PCB assembly for yield and throughput improvement. This AI-based framework could provide a potential road map for data-driven process control in SMA. Machine Intelligence in SMA Each SMA process has a critical effect on the final PCB product quality and throughput. Notably, the solder printing process is a critical operation because over 60% of the PCB assembly soldering defects can be traced back to this stage. An inadequate volume of solder paste transferred to any PCB pad is a printing fault, which leads to board failure and substantial reworking and repair costs. The pick and place (P P) process is the highest cost procedure, including expensive machine investment and extended production time. In the soldering reflow process (SRP), the reflow oven temperature and other related settings determine the solder joints' quality and reliability. Hence, multiple inspection machines in the SMA processes have been introduced, including solder paste inspection (SPI) and automated optical inspection (AOI) machines. Particularly, two independent AOIs could be employed to detect the components' defects before and after SRP. Because many electronics components become small-scale (e.g., ), more assembly-related failures are often observed in recent SMA processes. The Smart Electronics Manufacturing Laboratory (SEML) at Binghamton University is fully equipped with two solder paste printers, two chip-mounters, and a reflow oven along with SPI and AOI machines. The research team tested more than 8,000 PCB at SEML. The results show that numerical methods based only on physical properties might have practical limitations in explaining small-scale components' behavioral patterns. It might be caused by unknown environmental factors (e.g., temperature and humidity), machine calibration, measurement accuracies, vibrations, etc., which could have influenced the quality of the SMA outcomes. However, recent research shows that AI-based methods can increase product quality up to 35%, reduce scrap rates, and optimize fab operations in semiconductor manufacturing, compared to traditional approaches[2]. It implies that a data-driven intelligent SMA process control has the potential to advance SMA processes. The goal of the smart SMA is to maintain optimized settings in both offline and online scenarios. The AI and data analytics solution can optimize all SMA process parameters before production (i.e., offline control) and during production (i.e., online control). The overall schematic of the AI-based closed-loop feedback control framework is illustrated in Figure 2. Intelligent SMA Modules In the solder printing process, four machine intelligence modules are considered: Printing advising module (PAM) Printing optimization module (POM) Printing diagnosis module (PDM) Dynamic stencil cleaning process control (CPC) Figure 2. A schematic diagram of the AI-based closed-loop feedback platform Figure 3. PAM effectiveness over customer’s best-known printing parameter setting PAM aims to recommend the ideal initial setting of the printer critical parameters, such as printing speed, printing pressure, and separation speed, using hybrid machine learning and heuristics optimization techniques[3]. As a case study, the research team validated the PAM's performance with an automotive PCB testbed and compared the printing results to the best-known printing parameters. The experimental results show that PAM can achieve over 50% higher Cpk (i.e., process capability index, as shown in Figure 3). POM optimizes printing parameters in real-time by monitoring printing quality and fine-tuning offset and process parameters for adapting to dynamic conditions[4]. The experimental results show that POM achieves more than 30% production quality improvement in terms of the Cpk by adjusting printing parameters compared to the offline control. PDM provides anomaly detection and diagnosis of the potential printing failure cases to improve process quality and reduce downtime[5]. The experimental results show that the PDM can achieve more than 87% accuracy in predicting different types of defects, improper printer hardware issues in the board support, squeegee, paste conditions, etc. The CPC uses the SPI information to estimate residue buildup level on the stencil undersurface and assess the stencil cleaning profile and cycle control, as illustrated in Figure 4[6]. Upon the implementation of CPC, it is expected that the robustness of the printing quality and the Cpk can be improved by 34% and 10%, respectively, compared to the best-known cleaning parameters using in the production line. Figure 4. Smart residue buildup prediction for stencil cleaning operation control During the P P procedure, the mounter optimization module (MOM) and the mounter diagnosis module (MDM) can be applied as a machine's automation process while optimizing the P P machine's parameters. By utilizing self-alignment effects appropriately, MOM identifies the optimal placement position by predicting the component's post-reflow positions based on the data collected by SPI, Pre-AOI, and Post-AOI machines, as shown in Figure 2. MOM also offers the placement positions adaptively during active production. In the MOM framework, multiple dynamic placement options are first generated based on the solder paste offset information. The components' final offsets in both x and y directions are predicted by a hybrid AI model that stacks on the k-nearest neighbor regression and the gradient boosting regression models. The optimal placement, which has the minimum predicted post-reflow misalignment, can be identified by MOM. The experimental results show that MOM can decrease 18% of the final misalignments compared to a conventional P P placement method (i.e., placing a component on the pad center). MDM is a prescriptive and predictive maintenance method that uses P P machine operational and AOI inspection data to trace back the root causes of P P defects and prevent future failure. MDM can achieve an accuracy of 84.50% in identifying the known root causes of certain defects, such as improper nozzle size, parts' contamination, and feeder problem. It shows that different mounting defects can be detected and classified automatically when the abnormality is detected through AI-based diagnosis algorithms. Figure 5. The illustration of the optimal placement position in the MOM One of the reflow oven issues to be addressed is to find the optimal reflow oven temperature settings, which would affect the final quality of the PCB products. Solder paste manufacturers usually provide a target profile based on the solder paste composition's physical properties, and solder joint temperature is required to meet the given profile. Hence, reflow engineers should fine-tune reflow oven temperature manually to ensure a thermal profile outcome from the reflow oven to correctly meet a target profile, requiring substantial cost and effort. The research team proposes an automated reflow recipe optimization model based on the PCB thermal profile and its recipe. Figure 6. Optimized thermal recipe and thermal profile First, the initial recipe collects the data for the prediction model and identifies the relationship between the thermal profile and the corresponding recipe. Then, an AI-based model is developed to predict the thermal profile based on the input recipe. Compared to traditional methods, the AI-based method generates an optimal reflow oven recipe to minimize the gap between the predicted temperature and the given profile. As a result, the AI-based prediction model allows us to achieve promising results, such as 97% of fitness in the given profile temperature curve within one hour of processing time. The proposed model has other significant advantages, such as saving time, labor, and materials. It enhances the degree of automation of the PCB reflow process. In the future, data from multiple inspection machines will be integrated so that the reflow optimization process is fully automated and generates more reliable results. Summary and Conclusion The small-scale electronics products make the SMA processes much more complicated to maintain high-quality PCB products, and theoretical interpretations of the SMA processes can be challenging due to many uncertain factors. With the help of AI and big data collected from various inspectional operations, SMA processes can be intelligent and flexible in response to dynamic environmental situations. While retaining the optimal control parameters throughout the SMA processes, the final PCB product quality can be enhanced while maintaining the designed throughput. Automated and smart systems bring about the opportunity to next level of electronics manufacturing, which utilizes the data and information from the end-users through edge/cloud computing and fastens the customized product manufacturing with increasing efficiency for high-mix/low-volume manufacturing. Also, it can increase verities of design and fasten the delivery time. About the Author Prof. Sang Won Yoon is a recipient of the SUNY Chancellor’s Award for Excellence in Scholarship and Creative Activities in 2019 and a highly successful researcher who leads many productive long-term industry collaborations. Prof. Yoon received his doctoral degree in School of Industrial Engineering at Purdue University, and he joined the faculty of the Watson School in the Department of Systems Science and Industrial Engineering at State University of New York at Binghamton in 2010. Prof. Yoon has been studying how to extract useful insights from expanding data sets to support intelligent decision-making processes. His research not only resides in better understanding large-scale data set by using statistical learning methodologies, but also leverages optimization, soft computing, simulation, and complex theories with conventional machine learning algorithms. As a result, Prof. Yoon has published in over 130 internationally renowned journals and conference proceedings. He was also a member of the Data Science Transdisciplinary Area of Excellence (TAE) initiative and is an active member of the Health Sciences TAE at his institution. The author recognizes the following for their assistance with this article: Daehan Won, [email protected], Assistant professor Jingxi He, [email protected], Ph.D. candidate Shrouq M. Alelaumi, [email protected], Ph.D. candidate Yuanyuan Li, [email protected], Ph.D. candidate Yuqiao Cen, [email protected], Ph.D. candidate References ​​​​​​​[1] Qi, Q., and Tao, F., 2018. Digital twin and big data towards smart manufacturing and industry 4.0: 360 degree comparison. IEEE Access, 6, pp.3585-3593. [2] 10 Ways machine learning is revolutionizing manufacturing in 2019. https://www.forbes.com/sites/louiscolumbus/2019/08/11/10-ways-machine-learning-is-revolutionizing-manufacturing-in-2019/?sh=7cd2e9e22b40. [3] Khader, N. and Yoon, S.W., 2018. Stencil printing process optimization to control solder paste volume transfer efficiency. IEEE Transactions on Components, Packaging and Manufacturing Technology, 8(9), pp.1686-1694. [4] Lu, H., Wang, H., Yoon, S.W. and Won, D., 2019. Real-Time stencil printing optimization using a hybrid multi-layer online sequential extreme learning and evolutionary search approach. IEEE Transactions on Components, Packaging and Manufacturing Technology, 9(12), pp.2490-2498. [5] Alelaumi, S., Wang, H., Lu, H. and Yoon, S.W., 2020. A Predictive Abnormality Detection Model Using Ensemble Learning in Stencil Printing Process. IEEE Transactions on Components, Packaging and Manufacturing Technology, 10(9), pp.1560-1568. [6] Alelaumi, S., Khader, N., He, J., Lam, S. and Yoon, S.W., 2021. Residue buildup predictive modeling for stencil cleaning profile decision-making using recurrent neural network. Robotics and Computer-Integrated Manufacturing, 68, p.102041.

Now, more than ever, semiconductor companies are relying on their human resources departments to ensure employee safety, support facility access and hygiene measures, cope with staffing demands and incorporate the rapidly evolving guidelines from Centers for Disease Control and Prevention (CDC) and the local state and city mandates. SEMI spoke with Crystal Reich, HR manager at X-FAB Texas, about her participation in the Fab Owners Alliance (FOA) human resources group and the value of collaborating with industry peers on a broad spectrum of topics: from focusing on specific areas such as ensuring employee safety and managing the workforce during a pandemic, to addressing broader organizational challenges such as benchmarking activities and identifying compensation and staffing best practices. SEMI: How did you learn about the FOA human resources group? Reich: I have been part of the FOA HR group since its inception in 2012. Lloyd Whetzel, the CEO at X-FAB Texas, has been very involved with the FOA for several years. When this group was being formed, he let me know about it. I came to the first meeting and have been a part of it ever since. SEMI: What does your participation in the FOA human resources group allow you and your company to do differently? Reich: I am also involved with the Society for Human Resource Management (SHRM), but the FOA HR group provides an excellent opportunity for semiconductor industry HR professionals to collaborate. The group not only covers topics that are specific to the semiconductor industry but also discusses broader topics related to preserving employee well-being during unprecedented challenging times, managing negative emotions, establishing appropriate political expression policies, and creating safe spaces for dialogue. Also, the benchmarking has been fantastic, especially from a compensation and staffing standpoint. It allows us to identify best-in-class recruitment strategies, determine any shortfalls and use this information to improve employee onboarding and development. In addition to discussing these types of issues and trends, we compare and benchmark other HR issues such as policy deployment and legislative trends with colleagues in the industry. SEMI: What are some of the key topics and activities that the FOA HR group has helped you focus on? Reich: X-FAB has been involved in a variety of activities at SEMI. Through the SEMI High Tech U program, we have been able to help college-bound high school students in our community access STEM curriculum and explore careers in technology. We have devised more robust military outreach strategies with the help of the Veterans Program at SEMI, allowing us to recruit and retain excellent technicians from the military. Additionally, benchmarking activities within the FOA HR group have helped us improve our talent acquisition process - especially for positions which are challenging to fill. SEMI: The pandemic brought many significant and unprecedented challenges that affected business continuity. How did your company's participation in the FOA help you navigate these changes? Reich: The FOA has been a great help in addressing the challenges of the global pandemic across several operational collaborative teams. In the early days of the pandemic, as employees moved to remote work, FOA organized a forum that allowed members to share how they dealt with this transition. Constantly changing guidelines and protocols meant that FOA members leaned on each other more than ever to share best practices and lessons from new safety process implementations. FOA offered survey and area-specific team activities, cross-functional operational sessions, and round table discussions at its 2020 Q4 meeting, where members exchanged ideas on how business processes changed during this period and shared what they were doing to ensure business continuity. This provided another excellent opportunity for FOA members to benchmark best practices within the semiconductor industry. SEMI: Would you recommend your peers to join the FOA HR group? Reich: I would highly recommend HR colleagues in the semiconductor industry join this collaborative group. It is a great platform to share ideas, learn from each other, and benchmark with other colleagues in the same industry. The FOA HR Metrics survey is a comprehensive survey covering several different areas within the HR discipline such as compensation, learning and development, tool training, corporate social responsibility, and many others. True to the nature of the FOA, the survey is a result of the collaboration between several HR professionals from Device Maker member companies. Please contact Shilpa Talwalkar at [email protected] if you would like to participate. X-FAB is a member of the SEMI Fab Owners Alliance, an international group of semiconductor and MEMS fab managers and industry suppliers that meet regularly to solve common non-competitive manufacturing issues and improve their business results. Nishita Rao is senior product marketing manager at SEMI.

As we pass the work-from-home one-year mark, most of us still work remotely and will do so for the foreseeable future. As live trade shows and technical conferences were cancelled one after the other, virtual events became the norm. And, teleconferencing became a way of life. While possibly overstating our role, we have the semiconductor industry – from system design through manufacturing and system integration – to thank for a long history of achievement that made the transition to working remotely relatively seamless and straightforward. The shift, in some cases, took some time to sort out as we set up a workable home office, moved to video conferencing with intermittent connections and settled into a routine. Nonetheless, many of us became more productive and, in some cases, even too productive. Each spoke in the global electronic products hub contributed through creativity and innovation with a pinch of ingenuity and grit. Of course, we could have worked remotely 10 years ago, but not nearly as efficiently. Over the last 10 years, the economy moved to the cloud, producing new opportunities across the global market. Many of these opportunities were made possible by the electronic system supply chain and combination of semiconductor technology, electronic product innovation and people who figured how to leverage it with software platforms to tie it together. Zoom, one of our teleconferencing lifelines, is a good example, as are Netflix, our ongoing source of entertainment, and Roblox, a platform to build games. Facebook, Twitter, LinkedIn and the like sourced the news for us and kept us in touch. Amazon delivered our online purchases and GrubHub brought us our takeout dinners. All rely on cloud computing with thanks to the semiconductor industry. Another great example are data centers powered by semiconductors and the amount of data they processed last year. According to International Data Corporation (IDC), 64.2 zettabyte (ZB) of data was created or replicated due to the dramatic increase in the number of people working, learning and entertaining themselves from home. (Its revised model for global data creation and replication predicts the CAGR will grow to 23% over the 2020-2025 forecast period, a sure bet that the semiconductor industry will address ways to manage the growth, possibly through new AI chips.) Our connectivity is driven by smartphones optimized for low power and the performance of more complex chips. Over the last 10 years, design tools have been enhanced and new methodologies have been introduced to respond to the needs of the increasing complex chips for applications that demand high bandwidth, low latency and reduced power consumption and area. Manufacturing is retooling for higher automation under smart manufacturing initiatives and packaging is even more sophisticated with increasing integration and the 2.5D and 3D packaging rollouts. Let’s take stock of our success. The semiconductor industry has a storied tradition of breakthrough technology since its inception. The consumer electronic product craze started when the first PCs were rolled out in 1971, notes the Computer History Museum. Primitive laptops that followed in 1986 gave way to notebooks in 2007 and the ubiquitous smartphone in 2002 – and the rocket fuel for much of this was the buildout of computer networks, hyperscale datacenters and the cloud. Nothing’s been the same since. The next time we turn on our laptop, click on the link for the latest teleconference from our remote home office in comfortable sweats sitting in our ergonomic chair, let’s take a minute to acknowledge our industry’s grand achievement. And, thank one and all for their contribution and consider what’s coming next. About the Author Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Strategic Association Partner. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.