Technology and Trends

Kate Wilson, president of the semiconductor division at Edwards Vacuum, has already made progress in tackling critical issues like reducing Edwards’ carbon footprint, building an inclusive workplace, and contributing to overcoming the global chip shortage.

From the need for more tech talent to fuel digital transformation across all industries to the great resignation and great retirement of workers en masse, the demand for tech talent continues unabated.

During their session Creating a Data Ecosystem to Enable End-to-End Advanced Predictive Manufacturing, Laura Matz of EMD & Raj Narasimhan of Micron provided a case study of their uncommon partnership in creating a shared data ecosystem to prove the advantages of advanced predictive manufacturing.

“Virtual platform environments that combine the verification capabilities of emulation with the pre-silicon functionality insights available through verification intellectual property (VIP) are an increasingly popular way to get designs verified ahead of the curve of new standards,” Browy says.

Semiconductor device manufacturers are focusing on new sensing technologies that can increase wafer throughput, reduce downtime, boost yields and drive other production efficiencies by collecting data that provides insights not previously identified.

As part of bi-weekly meetings of the SEMI Environment, Health, Safety and Sustainability (EHSS) community to share information on the impacts of the pandemic, the EHSS COVID-19 Working Group recently revealed that companies are offering PTO to employees to get vaccinated.

Dr. Lanza, Managing Partner of Lanza techVentures and 2014 winner of the Phil Kaufman Award for Distinguished Contributions to Electronic System Design, addresses why he believes semiconductors in MedTech is about to become the next big thing.

What is analog computing and what do engineers need to know about it so they can make sound decisions during product development to differentiate their battery-operated always-on devices?

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at the technological forefront in incorporating ML techniques in its chip design products. I spoke with Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital Signoff Group, about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. Teng also offers advice on how engineering students can calibrate their education to prepare to work with this transformative technology and urges them to have fun in the process. Smith: How is ML changing the EDA industry? Teng: ML is changing EDA for the better in many ways. It’s more difficult than ever to design chips, and ML is helping by overcoming the complexity, size and technology interdependencies. At the same time, ML is helping our own engineers solve certain classes of EDA algorithm, tool, and flow/solution challenges so that we can deliver even better EDA tools to our user base. The benefits can include reducing runtime, increasing quality of results, and being better equipped to manage vast complexity and data. Also, and maybe even more significant, is the potential boost to user and team productivity, where engineers have more time to focus on high-value problems because they no longer need to spend time on managing overwhelming volumes of data and details that can be easily automated. Smith: What is the potential impact ML can have on semiconductor design? Teng: ML technology can be leveraged in several ways to improve EDA tool performance and engineering team productivity. For example, we initially applied ML to applications such as formal verification, simulation regressions, analog circuit design, and PCB design. We targeted ML toward specific algorithms that processed lots of data to sharpen and speed decision-making. Then we started to look at digital implementation flows that combine multiple steps with multiple decisions in a recipe, especially for chip implementation where the more efficient use of engineering knowledge can make a substantial difference in the chip’s resulting power, performance and area (PPA). These flows present more challenges and require different ML and optimization techniques since the data points are expensive to create and the volume of data is huge. But flow optimization offers the largest rewards for companies investing in data collection and analysis to improve their operations and product quality. By using ML to improve the implementation flow, our users are seeing up to 20% better PPA and 10x improved productivity in developing data center CPUs and AI engines, automotive sensor processing SoCs, and mobile devices. Smith: What is the cloud’s role in the evolution of ML in EDA? Teng: More ML usage means there will be an inevitable surge in compute demand resources, and engineers need the ability to scale in parallel. The cloud provides engineers with the best opportunity to scale computing resources without facing procurement limitations. The cloud also allows engineers to use task-specific compute and ML accelerators and capitalize on distributed computing innovations that leverage the cloud for greater design flexibility and availability. Smith: You have written that you see Moore’s Law accelerating. How does ML fit into this? Teng: We see the rapid adoption of new process technologies as the biggest trend surrounding Moore’s Law right now. ML technology in EDA will help speed tool certification processes, process design kit (PDK) development and other deliverables aimed at creating and improving customer support through all stages of the process lifecycle. This is a virtuous circle, and it’s expanding beyond hardware design and optimization to also include software. Today’s ML functionality works on the abstraction of register transfer level (RTL), optimizing the implementation and verification flows. ML will soon enable use of a higher abstraction of describing the target systems, exploring architectural options and optimizing across hardware and software partitioning. Smith: What advice would you give engineering students who are studying ML with the goal of becoming an electrical engineer? Teng: With the rapid pace of technology development, things are changing constantly. I’d absolutely encourage students to look at ML because ML isn’t going away — its growth is only going to accelerate from here. I’d also suggest that students look more broadly at computational mathematics because that’s foundational for ML. There are many, many opportunities to apply ML to real-world applications that will make a significant impact when it comes to optimizing computational software. Most important, students should explore and have fun while doing it. About Chin-Chi Teng Chin-Chi Teng has served as Senior Vice President and General Manager of the Digital and Signoff Group (DSG) since 2018. Prior to this role, Teng held senior leadership positions in research and development in digital implementation. Teng joined Cadence in 2002 via the acquisition of Silicon Perspective Corporation and subsequently led various research and development groups. He brought deep technical knowledge and more than 20 years of industry and academic experience to his role as leader of the IC Digital group. Teng holds a BS in electrical engineering from the National Taiwan University and an MS and Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He holds seven patents and has written many EDA papers, several deep learning papers, and the book Electrothermal Analysis of VLSI Systems. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Three-dimensional integrated circuits (3D-ICs) are revolutionizing the semiconductor industry. Manufactured by stacking and interconnecting dies so they perform as a single device, 3D-ICs deliver more capabilities by offering higher performance and bandwidth — while also reducing power consumption, package size and costs. However, 3D-ICs present tough design challenges to engineers. Significantly larger than a single-chip system on a chip (SoC), these assemblies have more components, more integration points and longer interconnects, that translate to new risks for high-frequency signal failure, reliability, and other performance issues such as thermal buildup. As the lines between silicon and system continue to blur, engineers must conduct concurrent, multivariate analysis to assess every possible failure mode ― not only at the component level, but also across the entire 3D-IC assembly ― a technical obstacle for many development teams accustomed to applying a series of single-physics engineering simulation tools in a sequential approach. 3D-ICs are assembled in a complex package using a serial analysis approach that doesn’t take into account system-level interactions, as well as the many thousands of bump connection points where something can go wrong. By contrast, concurrent, multivariate simulation and analysis takes into account all physics simultaneously from the earliest prototyping stages of design. Most semiconductor development teams not only lack the technical tools to perform this complex simulation and analysis, but they also face cultural obstacles as they undertake system-level analysis. Diverse teams working with disparate tools simply aren’t equipped to perform seamless handoffs and collaborate effectively on a complex 3D IC design from an early stage. Instead, they scramble to address system-level issues later when launch delays are likely, the cost of rework is high and their positive contributions to the design are diminished. The Value of a True Multiphysics, Multivariate Approach As market demand for 3D-ICs increases, semiconductor development teams need a single simulation platform that enables simultaneous multiphysics analysis — including power integrity, reliability, electromagnetics (EM), thermal, computational fluid dynamics (CFD) and mechanical studies ― across the entire assembly. A unified simulation platform that brings together best-in-class solutions for every physics enables semiconductor engineers to collaborate across functions, seamlessly hand off analysis tasks between engines, and partner to optimize 3D-IC designs across every performance parameter. Costly surprises from signal integrity to thermal conductivity and structural strength are far less likely when the team reaches physical assembly to help ensure on-time, cost-effective product launches. An example of simultaneous multivariate analysis of a chip stack showing both thermal gradients and mechanical stress/warpage of the package at an early prototyping stage. By contrast, applying multiple physics sequentially can lead to ongoing and expensive setbacks. For example, as one team resolves signal integrity issues, another team could discover that timing failures or thermal risks have arisen. It’s not only back to the drawing board, but back to a series of time- and resource-intensive handoffs across disconnected simulation and analysis tools, as well as across functional boundaries. The Importance of Considering Novel Physics Because the pressure is on to launch innovative 3D-IC designs rapidly, development teams might be tempted to focus on existing signoff metrics ― which are complicated enough, across today’s multi-die assemblies — but overlook the application of more novel physics. This is a mistake that can result in failures in the field, product recalls, warranty expenses and lasting damage to the brand reputation. To achieve full product confidence across the entire 3D-IC system, semi engineering teams need a solution set and associated best practices that make it fast and intuitive to not only optimize performance and cost, but to concurrently analyze novel physics that will impact electrical reliability, mechanical stability and thermal failure modes. The number of physical effects that need careful simulation has risen in lockstep with Moore’s Law and has increased even more for 3D-IC design. The use of a single, connected platform enables this kind of true multiphysics analysis. A multiphysics platform should interface with popular design systems, and be extensible by Python API's to the user and to other vendors. For example, engineers can check the thermal behavior and the likelihood of melting and local failures of each solder bump based on the electrical current it carries. The engineers can apply computational fluid dynamics to evaluate how well airflows generated by fans and heat sinks work to cool down the assembly. They can maximize system reliability by examining unfamiliar effects like low-frequency power oscillations on the distributed power supply network. Best of all, a unified and purpose-built simulation platform enables semiconductor development teams to conduct all these studies simultaneously to rapidly reveal design trade-offs that arise when many elements are brought together in a complex assembly. Only this type of multiphysics, multivariate, concurrent approach enables engineering teams to reach all their goals for speed, confidence, innovation and product performance as 3D-IC designs take over the global market. Supporting a Culture of Vertical Integration Global leaders in the semiconductor and electronics industries benefit from a culture and organizational model based on vertical integration, which supports high levels of design collaboration. It can be tough for horizontally integrated, smaller companies to establish this depth of collaboration. Customers require open and extensible platforms that support a broad range of analysis tools across many different abstraction levels – from device to chip to board to system. The right simulation technology platform can significantly help. A shared platform that brings cross-functional engineering teams together for simultaneous, not sequential, multiphysics design can make it easy and seamless to collaborate across functional boundaries and support excellence in every aspect of power, performance, reliability and cost. By balancing these foundational performance aspects with simultaneous optimizations of temperature, mechanical stress and other subtle effects, semiconductor engineering teams can position themselves as leaders, not followers, in the 3D-IC revolution. Learn More at the Ansys IDEAS Digital Forum Register for Ansys IDEAS Digital Forum on demand to learn more about 3D-IC best practices from leading industry experts (www.ansys.com/ideas). John Lee is General Manager of the Electronics and Semiconductor Business Unit at Ansys.