FD-SOI

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

The industry continues rewarding luminaries of the SOI ecosystem. Recently recognized are Jean-Pierre Raskin for RF-SOI, Lattice Semi and NXP for FD-SOI products, and Bich-Yen Nguyen for her work in SOI. The SOI Consortium extends hearty congratulations to all the winners and their teams. Professor Jean-Pierre Raskin was awarded by the prestigious Médaille Ampère 2019 for the originality of his scientific work in the field of RF-SOI technologies for wireless communication. The international award was delivered by Mr. François Gérin, president of the SEE - Société de l'électricité, de l'électronique et des technologies de l'information et de la communication, on December 3rd, 2019, in Paris, France. We’ve long covered the work of Professor Raskin and his UCLouvain team – which is largely responsible for why SOI is in every smartphone on the planet. It’s a great story (read it here) and it goes on! In his Ampère acceptance speech, Professor Raskin said, “...significant industrial research and development is being performed toward fully integrated SOI front-end-modules. Notably, the 45nm PD-SOI [RF-SOI] and 28nm and 22nm FD-SOI nodes are being extensively designed with to develop 5G mm-wave low-noise amplifiers (LNA), power amplifiers (PA) and switches, in particular at 28 GHz. […] Overall, SOI is expected to be a big contender as a technological platform to enable mass production of millimeter wave 5G and ultra-low power RF IoT devices and products in the near future.” [caption id="attachment_27119" align="alignleft" width="294"] Lattice CEO Jim Anderson (left) and Mark Lipacis (right), Managing Director of Jefferies (Courtesy: GSA Lattice Semi)[/caption] Lattice Semiconductor was the recipient of the Global Semiconductor Alliance’s (GSA) 2019 Analyst Favorite Semiconductor Company award based on technology and financial performance. The GSA awards recognize the achievements of top performing semiconductor companies and the 2019 winners were announced at the annual GSA Awards Ceremony held on December 5, 2019. In thanking his team, Lattice CEO Jim Anderson, added, "We are even more excited about the solid execution of our product roadmap, specifically, the accelerated product rollouts of both CrosslinkPlus and our next generation FPGA platform based on FDSOI technology, which will be key catalysts to our achieving sustained long-term revenue and profitability growth.” [caption id="attachment_27120" align="alignright" width="71"] (Courtesy: NXP)[/caption] NXP was a recipient of a Best-in-Show Award at the 2019 Arm TechCon this fall. As was noted by Brandon Lewis, Editor-in-Chief of Embedded Computing Design, “The i.MX RT1170 crossover MCU marks a technology breakthrough in MCUs, running up to 1GHz while maintaining low-power efficiency. It is architected to deliver a record-setting performance, with a 6468 CoreMark score and 2974 DMIPS while executing from on-chip memory. The solution uses advanced 28nm FD-SOI [note: fabbed by Samsung Foundry] technology, making NXP the first company to build MCUs in this advanced technology node. This new MCU family is redefining the "edge" and MCU landscape, bringing unprecedented performance and high levels of integration to propel industrial, IoT, and automotive applications.” And finally, Soitec Senior Fellow Bich-Yen Nguyen was elevated to the status of IEEE Fellow in the Class of 2020 “for contributions to silicon on insulator technology”. As previously noted in her IEEE bio, “Her honors and awards include the Dan Noble Fellow, the highest technical award at Motorola; the Master of Innovation Award; and the first national Women in Technology Lifetime Achievement Award. She holds over 200 worldwide patents and has authored more than 180 technical papers on integrated circuit technologies.”

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

As 2019 draws to a close, the SOI Consortium would like to recognize members that have joined over the course of this year: Applied Materials, Analog Bits, Antaios, Silicon Catalyst and SmarterMicro. And as we start off 2020, the Consortium is pleased to welcome Thalia Design Automation. Here’s a bit of SOI-ecosystem background for each of them: Applied Materials: AMAT has a long history in the heart of SOI ecosystem – in fact they’ve been working with SOI wafer-leader Soitec for over 25 years. AMAT is leading supplier of SOI-related process equipment, with systems for ion implantation, epitaxial deposition and chemical mechanical polishing (CMP). In fact their ion implanters are a key enabler to what became and is Soitec’s industry-leading Smart CutTM SOI wafer manufacturing process. And of course AMAT equipment is used to make virtually every chip in the world, so their breadth of vision as a Consortium member is clearly a wonderful addition. Analog Bits: SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. Analog Bits has been revolutionizing SERDES IP by drastically cutting the power it pulls. In fact in porting the IP to the FD-SOI processes of leading foundries, Analog Bits has laid claim to the industry’s lowest-power SERDES IP. They have been an active and generous sponsor of SOI Consortium events for several years now. Antaios: Antaios is a start-up in advanced memory technology. They are developing Spin Orbit Torque (SOT) non-volatile (NV) memory IP that is ultra-fast, durable, and reliable. The SOT-MRAM was proposed by SPINTEC and is now being developed by Antaios for nodes below 28nm where an STT-MRAM process is available. It is writable/readable in the nanosecond time scale making it particularly promising for cache memory applications (such as SRAM) for IoT, edge computing, AI and high-performance computing. SOT is an MRAM flavor that Antaios explains solves the STT-MRAM tug-of-war between endurance, speed and retention, thereby addressing both eFLASH and eSRAM replacement. Silicon Catalyst: Silicon Catalyst is the world’s only incubator focused exclusively on accelerating solutions in silicon. They address the challenges faced by startups while guiding them from concept to product, providing a path to funding, free access to tools, testing and shuttle runs, along with advice on proper corporate governance and strategic execution. The 21 startups admitted since 2015 to the incubator are developing innovative solutions in a variety of areas including energy harvesting, wearables, silicon photonics, memory technology, loT, high performance computing, artificial intelligence, machine learning, wireless communications, and biomedical devices. SmarterMicro: SmarterMicro is a fabless RF chip company. Their portfolio includes switches, power amplifiers and front-end modules FEMs. SOI technology provides the ideal platform for the software-defined RF front end module. They presented at several SOI Consortium events in Shanghai in recent years. Their 2018 presentation, RF-SOI in 5G Era and their 2017 presentation Reconfigurable RF PA and FEM with RF‐SOI, are available from our website. Dr. Li Yang of SmarterMicro received an SOI Consortium Industry Achievement Award in 2018 for outstanding contributions to RF-SOI, particularly citing the reconfigurable FEM, which debuted at Mobile World Congress in 2019. Thalia Design Automation: Thalia’s Re-use Platform-as-a-Service (RePaaS) solution combines an innovative methodology, advanced design automation technology and experienced analog engineering resources. It helps analog IP providers to maximize re-use of their existing product portfolio, to create new product variants quickly and easily, and to adapt their designs for manufacture using any semiconductor foundry service. Thalia’s AMALIA™ EDA design tools comprise an intelligent analog design optimisation automation toolset. The company has worked on multiple FD-SOI projects with body biasing, some of which are described in a recent company blog (read it here). Interested in joining this dynamic organization? For information on how your company can become part of the SOI Consortium, visit our About Us page, then use the Contact page to make your request.

The first day of the SOI Consortium’s recent China event – the 7th Shanghai FD-SOI Forum – was full to bursting in every way: the room, the networking, the level of expertise, the in-depth presentations and the overall energy. We covered the Samsung and GlobalFoundry keynotes in our previous post (if you missed it, read it here).This post will recap the rest of the presentations given during the day. (If your company or institution is a member of the SOI Consortium, you’ll be able to access the full presentations online.)International Business Strategies (IBS) – Impact of AI on Automotive and IoT, and Opportunities in China (Handel Jones, CEO) When it comes to deep insights on China + tech + analytics, and especially with a thorough understanding of FD-SOI markets, Handel Jones is arguably the world’s leading expert. Here are some of the observations he shared. Though the chip industry will see declines across the board in 2019 (he sees 13.5%), he sees a return to growth in 2020. By 2030, he sees it as a trillion dollar market, of which China will have half. AI is a key driver – and will become more prevalent at the edge. Major drivers will include preventative medicine, gaming, NB-IoT and 5G. At the chip level, FD-SOI has a lower cost/chip compared to bulk – you’ve got small chips and high yields. Sensors – especially image sensors – are a key area, and this is another place where FD-SOI is better than bulk. He sees chip shortages in the 2022-24 time frame (as opposed to the current oversupply), so now is the time that China should be establishing large FD-SOI capacity.NXP – Automotive, Industrial and IoT Solutions Leveraging FD-SOI (Ron Martino, VP GM) In terms of power consumption, computing is easy but data transmission is hard, Ron Martino reminded the audience at the onset. That’s why you need the edge. This is where FD-SOI comes in, and if you want to have leadership, you should be leveraging body biasing, he said. In terms of machine learning, a lot can happen at the edge on the smallest devices. NXP is now shipping a very wide range of products based on FD-SOI, including the i.Mx7 and 8 families and the new RT crossovers. The latest announcement is the i.Mx RT 1100 MCUs, a very low-cost processor solution for high volumes. The i.MX7 ULP is in mass production for wearables, with record low leakage and high performance. The i.Mx8 and 8x are going into a broad range of applications – from retail solutions for automated checkout to pasta makers, and automotive applications for full cockpits with vision detection, as well as things like parking, V2X and in-vehicle monitoring.Sony Semi – Low Power IoT Products with FD-SOI eMRAM Technology (Kenichi Nakano, GM) Chips built on FD-SOI with eMRAM are in production, said Kenichi Nakano. In GNSS/GPS, Sony is the #1 in lowest power consumption worldwide, thanks to FD-SOI, he continued. They’ve had 70 remarkable design wins, giving them over 50% market share in the sports and health watch markets, he said with a tip of the hat to the FD-SOI ecosystem and SOI Consortium. In GNSS, performance is very important – and now they can do it in water, which is huge. Development cycles are shorter than ever – for the latest chip it started in February 2018 and was in production by the spring of 2019, achieving decreases of 20% in power, 30% in area and 10% in cost. Integrating eMRAM was easy in terms of the design flow and manufacturing, with production yield of 97-100%. So with the GXD5605GF they’ve got the first GNSS chip with FD-SOI/eMRAM/RF in the world and it’s on 28FDS/eMRAM technology. It’s very reliable and very good, he concluded.Rockchip – Challenges of AIoT Chip (Feng Chen, SVP) At the beginning of this year Rockchip announced the launch of their RK1808, a low-power AIoT solution with built-in high performance (3TOPS) NPU fabbed in GlobalFoundries 22FDX, said Feng Chen. Their clients were very happy that Rockchip delivered the real power and performance numbers they’d promised. Because of the power/performance it delivers, FD-SOI (both 22 and 28nm) is very well suited for AIoT chips, he said. It’s very cost-effective in terms of NRE and die, and there’s room for further savings. While the ecosystem needs a unified push, FD-SOI is good for the market in China, and China has the volumes FD-SOI needs. Rockchip sees particular potential in retail and smartphones.Panel – Verticals Driving FD-SOI VeriSilicon CEO Wayne Dai moderated the first panel, asking first why China should adopt FD-SOI. Soitec CEO Paul Boudre said because it is a big, dynamic market (noting that Sony’s first FD-SOI GPS win was in China). Handel Jones said that at the wafer level, there was cost parity, but with FD-SOI chips are smaller and higher yield. The main reason it’s taken so long to get going was IP, but that’s changing now, he added. Dai’s next question was about the top application fields the panelists predicted for 2020. Sony’s Kenichi Nakano said wearables with connectivity, low power consumption, small size and high levels of integration; Rockchip’s Feng Chen agreed. NXP’s Ron Martino said FD-SOI for automotive, machine learning and edge computing was shipping now, with wearables ramping.VeriSilicon – Low Power IoT Connectivity IP Design Based on FD-SOI (Yi Zeng, Director, IoT Connectivity Platform) The “value” of IoT data is not yet being generated, noted Yi Zeng but AI can help here. The IoT industry needs innovation for both chips and networking. SiPaaS – which stands for Silicon Platform as a Service – as offered by VeriSilicon can help lower the barrier to entry. [In the SiPaaS model, VeriSilicon has its own IP-based core. Based on the company's advanced chip design capabilities and mass production service experience, it has created a variety of silicon-proven chip design platforms that can significantly reduce the customer's chip design cycle.] They have FD-SOI IP for NB-IoT, BLE, GNSS and sub-1 GHz. The BLE (Bluetooth) RF IP is a complete offering optimized for low power on GlobalFoundry’s 22FDX. The NB-IoT IP is also optimized on their 22FDX ZSPNano, an energy efficient general purpose MCU+DSP core on 22FDX. And they’ll have results of test chips for GNSS RF IP on 22FDX by the end of this year.Secure-IC – AIoT Embedded Security Using FD-SOI (Hassan Triqui, CEO) While AI enables products and services, it’s important to plan for security early in the design cycle, said Hassan Triqui. Software is not enough to protect edge-to-cloud. Secure-IC’s hardware security module, Securyzr, is an IP block that can be embedded into every device to answer security functionalities such as root-of-trust and key management. In sleep-mode/tunable cryptography, FD-SOI allows the creation of physically secure systems. (Note that designers are leveraging FD-SOI’s unique body biasing for ultra-low-power deep-sleep modes.) Because safety and privacy require a combined solution, Securyzer is particularly well-suited to IoT chips built on FD-SOI, he concluded, so that IoT adds value to AI, and not just the other way around.Soitec: FD-SOI – The 5th Gear for mm-Wave Radio (Michael Reiha, GM FD-SOI Business Unit) There are four key areas to 5G, explained Michael Reiha: coverage, number of antennas, frequency and traffic density. 5G mmW access architectures are currently inefficient in terms of power and performance, but FD-SOI is ready for 5G access as both an analog and hybrid beamformer. For MU-mMIMO (massive MIMO), the RF front-end modules (FEMs) and transceiver will fully exploit FD-SOI. Sensing, calibration and control enabling hybrid beamforming and multiple users is easy in FD-SOI. The adaptive body biasing on the horizon will reduce power of FEM mixed-signal circuitry, and be a disruptive technology.STMicroelectronics – Automotive MCUs in 28nm FD-SOI for ePCM NVM (Shan-Lin Liu, Automotive Marketing Manager) As a leader in the automotive market, ST has seen that increased data flows in automotive are driving demand for higher performance and bigger memory in automotive MCUs, said Shan-Lin Liu. ST has taken a unique approach to NVM with embedded PCM (phase change memory) on 28nm FD-SOI. This gives them energy-efficient, high-performance cores with larger NVM memories, and it’s already qualified up to auto grade-0. PCM (vs MRAM) is BEOL. It uses two cells, so it’s more reliable and is good at high temperatures, he said. With FD-SOI, they can go up to 165o, and it’s soldering compliant. The preliminary results of the first MCU chip are excellent. It’s now running in a car, replacing the previous generation 40nm eFlash product.Leti – Advanced FD-SOI for Edge AI (Emmanuel Sabonnadiere, CEO) To fully run artificial intelligence on the edge, research powerhouse Leti is working on an unsupervised learning neural network using advanced FD-SOI and a mix of other technologies. These include embedded non-volatile memory (NVM), 3D integration, and new design tools. Sabonnadière said this new approach is expected to exceed the performance levels of current digital deep learning with neural networks that are capable of handling time-domain signals, sound and speech—and may produce a first "killer app" for advanced SOI. AI will require compact and power-efficient circuits for the inference phase, when neural networks infer things based on new data they receive, close to the end user. The combination of FD-SOI, 3D integration, and NVM opens a path towards dedicated circuits with major performance improvement within the limited power budgets of distributed electronics. In Europe, he noted, privacy concerns are driving the move from the cloud to the edge. On the Leti roadmap, they’ve broken through the 10nm limit for FD-SOI, using strain and body biasing to compensate for transistor mismatch. Also of note: since 2016 Leti has had an ongoing collaboration with SITRI, the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating the innovation and commercialization of More than Moore technologies to power IoT.GlobalFoundries – GF Fab 1 Dresden: Delivering Differentiation with FDX for the Future of Automotive (Thomas Morgenstern, SVP GM Fab 1) Dresden Fab 1, Thomas Morgenstern reminded the audience, is the biggest in Europe, where it is part of the Saxony ecosystem. GF is moving advanced mask-making to Dresden, which is the lead site and Center of Competence for FD-SOI. With the “pivot”, GF is providing platforms. Fab 1 is automotive certified for 22FDX (GF’s 22nm FD-SOI technology), with automotive tapeouts in 2019. “Automotive is a journey,” he said, of continuous improvement, and a mindset: it’s a zero defects culture. The ramp to volume production is well underway, with 26 tapeouts of 22FDX products this year – almost double that of last year. He showed high yield data of about a dozen products, adding that since the beginning of the year every tapeout was first-time right with decreased cycle time. The key specifications for 22FDX with eMRAM for Auto Grade-1 have all been demonstrated, and customer feedback has been excellent.Next: Shanghai International RF-SOI Workshop recap As you can see, it was a packed day for the FD-SOI part of the SOI Consortium’s Shanghai event. In fact the room was still packed at the very end of the day. Several hundred VIPs then headed out for the ever-popular and festive evening riverboat dinner cruise, where the non-stop networking continued.A big shout-out to our sponsors and supporters: VeriSilicon, Simgui, SIMIT, Soitec, Samsung, IBS Ion Implant, ShinEtsu, GlobalFoundries and NXP.The next day of the event was devoted to RF-SOI. That will be the subject of our next post.

The SOI Consortium’s next annual event in Japan takes place on the 30th and 31st of October in Yokohama. Both days of the SOI Design Symposium will take place in the Yokohama Landmark Tower. The event is complimentary, however pre-registration is required – just follow the link here. Rest assured that in addition to the excellent program, the agenda provides ample time for networking.Wednesday, October 30 -- RF and ULP on SOI: IP ProductsOctober 30th showcases industry leaders with ULP IoT applications by NXP, and opportunities in the RF space by STMicroelectronics and Toshiba. The strong development of the design and EDA platform is discussed by ARM, Silvaco, Attopsemi and Dolphin. GlobalFoundries will present on their predictive reliability platform for RF, while Incize discusses the criticality of RF characterization and Secure-IC addresses to important topic of IC security.The day finishes with an overview of the SOI ecosystem by the SOI Industry Consortium. (See the full agenda here.)Thursday, October 31st -- SOI Enabling Photonics and Power InnovationWe start the day with two keynotes on High Voltage SOI electronics for automotive by NXP followed by Soitec on engineered substrate solutions. The Silvaco overview on RF modeling and SOI NB-IoT by SITRI promises to be very interesting. Then the day will offer a deep dive into Photonics touching applications with Cisco, foundry offerings with TowerJazz and GlobalFoundries, EDA with Cadence, and advanced SOI Photonic solutions by Leti-CEA. An ecosystem and market outlook by Soitec wraps-up the day. (See the full agenda here.)We look forward to seeing you there!

The 45th (yes!) IEEE SOI Conference takes place 14-17 October 2019 in San Jose. Now called S3S –since it also covers 3D and subthreshold – it’s a networking event par excellence: a unique opportunity to meet firsthand the movers and shakers in the SOI ecosystem and the giants of R D. As always, it has a strong technical program you won’t want to miss. Plus this year there’s a full-day short course dedicated to FD-SOI design, and half-day tutorial on RF design. Get all the details and registration info at http://s3sconference.org/.The SOI Consortium’s own Executive Co-director Jon Cheek of NXP is one of the keynoters. In fact the consortium membership is extremely present at this event, with over half our member organizations having a hand in it. There’s a plenary talk by GF’s CTO/VP Subramani Kengeri, keynotes by ST Fellow Andreia Cathelin and NXP Fellow Rob Cosaro, and invited talks from Arm, Samsung and Dolphin Design, for example. And this year’s General Chair is Incize CEO Mostafa Emam. Focus Sessions #12 and 13 are all about FDSOI Platforms and Products, with invited speakers from Renesas, NXP, ST, ARM, GF, Huali and Dolphin Design, while focus Session #2 is all about RF-SOI. Here’s the agenda for the FD-SOI Design short course (which takes place on Thursday, 17 October):Short Course Opening and Welcome Philippe Flatresse, Business Development Marketing Director, Dolphin DesignGLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIESEmbedded Flash Memory Technologies and Applications in Advanced Nodes Memories Koji Nii, Vice President, Global Marketing Sales, Floadia CorporationEnabling the Adaptive Body Bias in Modern IoT Applications Vincent Huard, CTO, Dolphin DesignSoC Design Realization with Adaptive Body Bias Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics Didier Roland, Application Engineers Manager, Mentor GraphicsAnalog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R DLow Power Solutions for SoC Architectures Antonio Pullini, Senior Hardware Designer, GreenWaves TechnologiesSOI to RF Sidina Wane, CEO, eV-technologiesIf you know the way to San Jose, you'll want to be at S3S 2019, for sure!

The recent SOI Consortium’s FD-SOI and RF-SOI events (Shanghai, September 2019) were record-breakers, with attendance approaching 1000 over the two days. The event was extensively covered in the China tech press, which often cited the opportunities SOI-based technologies offer for technology leadership. Indeed, as SOI Consortium Executive Co-Director Carlos Mazure noted in a follow-up press conference, the SOI technology drivers dovetail perfectly with the semiconductor industry’s top growth drivers*: IoT, 5G/smartphones, AI/ML and automotive. Here are the takeaways he cited from the China events:SOI for AIoT, consumer and automotive: the FD-SOI ecosystem is in place (substrate supply, foundry offering, EDA and design IP). The 1st wave of adoption is ramping at NXP, STMicroelectronics, Sony, Rockchip, Synaptics, Renesas and more Fast followers are lining up, with the number of tape-outs increasing at Samsung and GlobalFoundries SOI for 5G: development is driven by the need for low cost, low latency and high data throughput the SOI ecosystem for 4G/5G technologies is in place with a strong market pull RF-SOI, the reference FEM 4G technology, will extend its benefits to sub-6Ghz: low power consumption, high linearity, low insertion loss, co-integration of RF components. 5G mmWave requirements are addressed by multiple SOI platforms (RF-SOI, PD-SOI and FD-SOI) enabling integrated analog mixed signal solutions at low power consumption. Two RF-SOI luminaries were honored at a post-event dinner sponsored by China wafer purveyor, Simgui. Jim Cable, Chairman and CTO of pSemi, a Murata Company, and Herb Huang, CEO and GM of Ninbo Semiconductor received awards for their contributions to the advancement of RF-SOI (more on this later). There’s an enormous amount to tell you about from the conferences, so this will be the first round-up post of several.Gitae Jeong, SVP, Samsung Electronics (Courtesy: VeriSilicon live.photoplus.cn) But briefly, in his talk entitled, "IoT Platform with FDSOI", the main points made by Gitae Jeong, SVP, Samsung Electronics were: 28FDS is fully mature. It has the same design rules as bulk, has an integrated security key, a wide range of packaging options for IoT, and a design guide that makes back biasing easier and simpler with complete IP solutions. 18FDS development is on track for this year, with 14nm BEOL and a 35% increase in performance, a 55% decrease in power (!) and a 35% decrease in area compared to 28nm. 1st products are now shipping with eMRAM on 28FDS with yields over 90%, operating temperatures have been extended to 125C for automotive, and a 1Gb version has been demo’d. 1st 5G products mmWave products on 28FDS are now available Americo Lemos, SVP, GlobalFoundries (Courtesy: VeriSilicon live.photoplus.cn)In his talk, "Leading Industry Innovation by Differentiated SOI-based Solutions", key takeaways made by Americo Lemos, SVP, GlobalFoundries included:They have leadership in RF-SOI, with over 50 billion chips shipped 22FDX (FD-SOI) is in production. Last year they had 14 tape-outs, this year they had 26 – half of which are for companies in China. By the end of this year they’ll have shipped 100 million good dies to customers, marking the full transition from ramp to volume. In the ecosystem, they’ve got 285 IP titles from providers worldwide, with more announcements coming soon. Work continues on 12FDX – more to come on this. Edge AI is the next growth engine for IoT, combining vision + voice + audio, with China coming in strongly with ultra-low-power design for home connectivity, industrial, personal and medical applications. The RF-SOI day was lead off by the reading a letter from Dr. Xi Wang. The leading proponent of SOI in China for over a decade as head of the Shanghai Academy of Sciences, he’s now the country’s Vice-Minister of Science Technology. Until this year, he’s always had the first keynote at the SOI Consortium events in China, but this time he was in a meeting with the VP of Russia. However, his warm letter confirmed his support for the SOI ecosystem, especially the role of SOI-based technologies for China in the 5G era. Danni Song, China Mobile Project Leader. (Courtesy: Simgui live.photoplus.cn) This was followed by a talk by the ever popular and insightful Project Leader Danni Song of China Mobile, the largest of the operators there. China issued 5G licenses in May 2019 as the country gears up for 5G commerce. By next year, 5G will be deployed in all cities above the prefecture level. For now, it’s all about sub-6GHz. The challenge, she noted, is in power consumption, which is 2-3x that of 4G in base stations and devices. They see two development spaces: one for consumer and one for verticals, and have teamed up with Sprint on a 5GS (S being for Superior) module. They released a basic modem chip and dongle in June, and a smart chip is coming. She suggests people consult the China Mobile white paper on 5GS for more info. We’ll cover the many other presentations over the next few weeks – so stay tuned! --------*as cited in a 2019 CEO survey by KPMG/GSA.

Since the beginning of the year, there’s been a steady stream of excellent news around Samsung Foundry’s 28FDS, their highly successful 28nm FD-SOI offering. Let’s take a look at what’s been happening, as things do seem to be accelerating. By way of reminder, they announced the industry’s first eMRAM (embedded MagnetoResistive RAM) testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here) - which was just a year after they had announced mass production of 28FDS process technology.At the end of 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology. Follow that with this announcement at the beginning of 2019: Soitec Expands Collaboration with Samsung Foundry on FD-SOI Wafer Supply. The two companies announced that Samsung had secured a high-volume supply of FD-SOI technology to meet industry's current and future demands especially in consumer, IoT and automotive applications. In March came two more big announcements. First: Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process. As they noted in the PR, “Samsung’s 28FDS-based eMRAM solution offers unprecedented power and speed advantages with lower cost. Since eMRAM does not require an erase cycle before writing data, its writing speed is approximately a thousand times faster than eFlash. Also, eMRAM uses lower voltages than eFlash, and does not consume electric power when in power-off mode, resulting in great power efficiency.”Hard on the heals of that came the news that Arm and Samsung Announce IP Platform including eMRAM for 18nm FD-SOI. At the SOI Consortium’s Silicon Valley Symposium in April, Tim Dry (he’s Samsung’s Director of Foundry Marketing for Edge and End Point), gave a terrific presentation. Entitled Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products, it details the company’s FDSOI roadmap for the IoT Endpoint Platform (and yes, you can download in its entirety). Then in May at the big Samsung Foundry Forum in Silicon Valley, Arm, in collaboration with Samsung Foundry, Cadence, and Sondrel, demonstrated the first 28nm FD-SOI eMRAM IoT test chip and development board. The Musca-S1 test chip demonstrates a new choice in SoC design for IoT solutions, said Arm. (Sondrel, btw, is Europe's largest independent IC design consultancy.)In parallel, Cadence announced: Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology. Especially aimed at digitally-assisted analog designs, what’s new here is that the Cadence custom and analog/mixed-signal IC design flow is now Samsung Foundry certified for 28FDS. Samsung’s 28FDS PDK techfile is Mixed-Signal OpenAccess ready, enabling customers to deploy OpenAccess-integrated, fully interoperable Virtuoso-Innovus implementation flows. For its part, at its Foundry Forum, Samsung unveiled extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions. They indicated that the development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.And finally, companies like NXP are shipping exciting new products fabbed on Samsung’s 28FDS. Ron Martino, VP GM of NXP’s i.MX Application Processor Product Line covered key products in his presentation at the SOI Consortium’s Silicon Valley Symposium (see our coverage here). Among them: the i.MX7ULP for long battery life with 2D 3D graphics for wearables and portables in consumer and industrial applications; the i.MX 8 and 8X subsystems for automotive and industrial applications; and the i.MX RT series of “cross-over” processors. The i.MX RT ULP (real-time, ultra-low-power) series, which Martino says is the “new normal”, deals with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier.In July, linuxgizmos.com reported that, “In June, NXP began volume shipments of its super power-efficient i.MX7 ULP, which it announced in 2017. The SoC is billed as the most power-efficient processor on the market that also includes a 3D GPU. […] the ULP version includes a 3D graphics capable Vivante GC7000.” (Vivante, btw, is a VeriSilicon company, which is an SOI Consortium member and a leading proponent of FD-SOI design and IP in China and worldwide.) This is leading to some really nice wins for NXP. For example, they’ve got Amazon's Alexa Voice Service (AVS) leveraging the i.MX RT crossover processor, enabling developers to quickly and easily add Alexa voice assistant capabilities to their products. The RT series has rapidly been expanded, with versions for voice-controlled devices and offline face and expression recognition capabilities for smart home, commercial and industrial devices.Also announced this summer: NXP and Microsoft Bring Microsoft Azure Sphere Security to the Intelligent Edge with a New Energy-Efficient Processor. That collaboration includes development of a new crossover applications processor in NXP’s i.MX 8 series integrating Microsoft’s Azure Sphere security architecture and Pluton Security Subsystem. Their customers “will be able to harness the high-performance and energy efficiency of NXP’s i.MX 8 applications processors combined with Microsoft’s unequaled security and assurance provided by Azure Sphere certified chips”. As Martino concluded in his presentation, “The future of embedded processing [is] enabled by FD-SOI.” And Samsung Foundry’s FD-SOI offerings are clearly a massive enabler of that future.

ASN had a chance to talk to François Brunier of Soitec, who’s leading this important project.Advanced Substrate News (ASN): Can you tell us briefly about OCEAN12?Francois Brunier (FB): OCEAN12 stands for Opportunity to Carry European Autonomous driviNg further with FD-SOI technology up to the 12nm node.Francois Brunier, Partnership Program Manager, Soitec.OCEAN12 deals with “Ultra-low power computing solutions for automotive and aeronautics using all the range of FDSOI technologies”. This project with a budget of 103M€ brings together 27 partners from 7 different countries. The project received the ECSEL JU* label under the 2017 call. ECSEL is an EU-driven public-private partnership enabling the co-financing of innovation in electronic components and systems both by Member States and the European Union.ASN: Why is this project needed?FB: As of today a car has around 500 million transistors. These electronic components represent already an important vector of valorization and differentiation for the automotive industry and for the consumer. The increased autonomy of the vehicles will require a very strong build-up of computational capacities. 50 to 100 times more transistors could be required for a level 5 (fully autonomous car). Following this trend an autonomous car will require power consumption equivalent to 50 to 100 computers running continuously (without taking into account the car propulsion).The OCEAN12 partners.The power consumption of these components becomes a key element in the choice of technologies. We believe that our technologies on SOI present the best assets to meet this challenge.The FD-SOI substrates, technologies and designs developed in OCEAN12 offer a palate of different solutions to this challenge: increased performance for data processing (including Artificial Intelligence); much higher energetic efficiency; and smaller form factors to fit in embedded systems like autonomous cars with higher integration and reliability, and enabling safe connectivity.The OCEAN12 project will demonstrate that SOI technologies are able to meet these challenges through relevant demonstrators in the targeted fields.ASN: What are the project goals?FB: OCEAN12 will bring concrete solutions to the main challenges of smart connectivity and low power consumption in the automotive industry.As such, OCEAN12 will build awareness around the key enabling technologies in substrate development, transistor behavior, and the design and fabrication of integrated circuits up to the system and end-user application levels. We will show that the technology is advantageous for automotive and aerospace applications, which are strategic sectors for Europe. Having the whole supply chain in Europe means having trusted and secured components made in Europe.The OCEAN12 project goals stand on three pillars:First: Confirming the technology foundation. Ocean12 puts the FD-SOI substrate and device developers in direct contact with the full value chain of suppliers and end users. This gives the entire ecosystem visibility into current and future needs, and ensures that substrate and device solutions are both technically feasible and correctly aligned with actual system requirements.Second: Creating concrete, innovative demonstrators in automotive (Audi, Bosch) and aeronautics (Airbus, Thales). These demonstrators are a first step in defining the context and environment to prove the advantages of these technologies in real application cases, showing they are useful and as such prefigure a final system and a potential future product roadmap. Demonstrators should be as close as possible to the final application.Third: Broadening the design ecosystem, with the big companies, the small- and medium-sized companies (SMEs) and the research organizations (universities, RTOs). We have a critical mass of 16 design ecosystem partners focusing their efforts on FD-SOI. The project leverages that dynamic FD-SOI design ecosystem for IC product migration to FD-SOI and the creation of new IP. Inventing the future components in Europe is also key.ASN: Can you tell us more about the demonstrators? When will we see them?FB: There are four demonstrators. All these demonstrators will be delivered by the end of the project in 2021:Always-on wake-up systems (Audi, Bosch, Leti). With such a system we can imagine an application to monitor our car when it is parked in a parking lot for a long time. The sensors would remain aware of everything that goes on around the car. Based on sensor observations, the car can make decisions on further actions to take. This can be used in many future car applications like intrusion detection or vehicle access systems. But you will not have to worry about battery drain: even though all the sensors are always on, they go right back into a very low-power sleep mode thanks to FD-SOI technology.mm-Wave integrated radar SOCs (Bosch and Audi), which will benefit from all the innovations of FD-SOI thanks to its low consumption properties, but also the optimization of the sensors. The performance gain is made over the entire system with adaptations between analog and logic.High-performance video processor for aeronautics. (Airbus, Thales, Kalray). Kalray, a French SME working on Massively Parallel Processor Arrays (MPPA) aims to demonstrate an ultra-low power, low-cost, high-performance neural processor on FD-SOI technology. This demonstrator would be key for Airbus and drones with high-performance, low-power cameras. Airbus and Audi have partnered on air and ground mobility services.Microcontroller plug-and-play board. This demonstrator lead by ST will allow for the development of new solutions in the domain of GNSS/GPS.ASN: Can you tell us more about the partners?FB: The OCEAN12 consortium of 27 partners involves 8 large groups, 9 SMEs and 10 universities/RTOs. These partners come from 7 different European countries.The eight large groups include: Soitec, the world’s leading provider of FD-SOI substrates; EVG, a leading global equipment supplier; GlobalFoundries and STMicroelectronics, the two major European FD-SOI foundries; and Bosch, as a Tier 1 automotive supplier. At the top of the value chain, high-end European automotive manufacturer Audi, the avionics industrial giant Airbus, and Thales for security issues, will develop product demonstrations.Ten highest-level research institutes support the industrial consortium. They include CEA-Leti (FR), Fraunhofer(GE), IMS (FR), INP Grenoble (FR), TU Dresden (GE), U. Paderborn (GE), Bundeswehr U. Munich (GE), Eberhard Karls U. Tübingen (GE), Instituto de Telecomunicações (PT), and Warsaw UT (PL). They increase the competitiveness through technological innovation and transfer of technical know-how while gaining new expertise working with global leaders.In addition, OCEAN 12 has a very strong SME consortium covering the supply chain in the fields of new equipment, IP, system integration and fabless companies. They include: IBS, UnitySC (HSEB), MunEDA, Kalray, AED Engineering, ISD, EVOTEL, M3 Systems and Design Reuse.All these partners have longstanding experience of cooperation in various national and international frameworks and are specialists in their fields of activity. Their contributions are essential for the success of the project.ASN: What is the timetable?The OCEAN12 kick-off event at Soitec’s headquarters near Grenoble.FB: The project started on April 1st 2018. The kick off with all the partners was held at Soitec on 29 September 2018. It was a great success. The project runs through December 2021, by which point everything has to be demonstrated.ASN: Can you clarify the funding structure?FB: The budget is about €103.6M. If the project succeeds, we get European Commission funding. In that case, just over 20% of the eligible cost – about €23M – is subsidized at the European level. The seven countries with companies or organizations participating in the project will then roughly match the European subsidies, contributing about €27M. These ECSEL-type public-private projects are a tried and true model in Europe, maximizing synergy across ecosystems. To conclude, in the name of the consortium I’d like to thank the ECSEL JU, the European Commission and our National Funding Agencies from France (DGE), Germany, Portugal, Greece, Spain, Austria and Poland. Such a project would not exist without them.______*ECSEL JU: Electronic Components and Systems for European Leadership Joint Undertaking