Dresden, 21 June 2023. On 19 June, Masao Hodai, Chief Operating Officer of EBARA Precision Machinery Company Tokyo, visited EBARA’s German site in Dresden-Weixdorf. After a welcome by Dr Reinhart Richter, Managing Director of EBARA Precision Machinery Europe, an informative tour followed, during which Masao Hodai inspected the Overhaul Centre for vacuum pumps, built in 2021, the warehouse, the training facilities currently being built, and representatives from the most important product divisions. A joint lunch with members of Dresden’s staff rounded off his visit.

Strong signal for the Dresden location
“The visit of COO Masao Hodai reinforces our location within the Silicon Saxony region and shows the significant status of the semiconductor industry in Dresden for EBARA’s headquarters in Japan. Our progress in terms of safety, quality, CO2 reduction and market acquisition has made a deep impression. All EBARA employees in Dresden feel very honoured by this visit from Japan”, said Dr Reinhart Richter, happily. In the afternoon, in-depth client meetings were on the agenda at the Dresden site before Masao Hodai returned home to Tokyo.

About EBARA
EBARA Precision Machinery Europe (EPME) GmbH, headquartered in Sauerlach near Munich, is the European sales and service company of EBARA Corporation Tokyo. EBARA is a leading global manufacturer of vacuum and semiconductor systems used to produce wafers, liquid crystals, solar cells and other high-tech products. EBARA Corporation was founded in 1912 by Issey Hatakeyama and employs over 19,000 people worldwide. With an annual turnover of 4.7 billion euros, EBARA is one of the largest companies in the industry. EBARA supplies 16 of the top 20 manufacturers in the chip industry.

About EBARA Precision Machinery Europe
The EPME portfolio includes dry and turbomolecular vacuum pumps as well as modern gas abatement systems for the chemical industry, for example. In addition, EPME distributes state-of-the-art CMP tools, wafer bevel polishing and substrate coating systems for chip manufacturing. In 2021 EBARA opened its second modern overhaul centre for vacuum pumps in Dresden. EPME has been operating a vacuum pump overhaul centre in Livingston (UK) since 1993. EPME employs over 250 people in Europe and Israel.
Photo: EBARA / Tommy Halfter

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Brewer Science’s High-Temperature-Stable, Gapfilling Planarizing Material Revolutionizes Advanced ArF and EUV Processes

OptiStack® SOC450 material provides zero shrinkage up to 550°C when baking in N2

June 15, 2023 – Rolla, MO – Brewer Science, Inc., a global leader in developing and manufacturing next-generation materials for the microelectronics and optoelectronics industries, is thrilled to announce the latest breakthrough in high-temperature gapfilling materials – OptiStack® SOC450 material, enabling advanced node processes by providing unparalleled performance at extreme temperatures.

A basic overview of a spin-on carbon and the need for a high-temperature stable material.
Overcoming the Industry Compromise: Thermal Stability for Planarization and Gapfilling

One of the greatest challenges in the advanced ArF and EUV industries has been finding a material that can withstand high temperatures without sacrificing its planarization and gapfilling capabilities.

Shrinkage in spin-on glass (SOG) coatings, or annealing processes, can result in incomplete coverage, pattern distortion, delamination, or cracking. Insufficient thermal stability properties can affect subsequent process steps, compromising the overall performance and reliability of the device. To prevent significant yield loss caused by unstable materials during high-temperature annealing, such as those necessary in self-aligned double patterning (SADP) applications, it’s important to ensure gapfilling materials are stable over 400°C.

A typical low-temperature SOC has 50% weight loss when baked to 400°C which makes planarization suffer due to the film shrink.

OptiStack® SOC450 Material Enables SADP Processing with High Thermal Stability

With OptiStack® SOC450 material EUV processes will no longer have to sacrifice temperature stability for superior gapfilling and planarization.

OptiStack® SOC450 material is a carbon-based high-aspect-ratio spin-on-carbon material designed to withstand high temperatures and provide low shrinkage, offering significant benefits to ArF, EUV, SADP, SAQP, 3D NAND, and advanced memory processes.

The following simplified example illustrates one potential application of OptiStack® SOC450 material to improve a SADP process by utilizing high-temperature CVD deposition of the spacer.

The following simplified example illustrates one potential application of OptiStack® SOC450 material to improve a SADP process by utilizing high-temperature CVD deposition of the spacer.

Key Features and Benefits of OptiStack® SOC450 Material

Zero Shrinkage: Unlike traditional SOC materials, OptiStack® SOC450 material boasts a remarkable 0% shrinkage when subjected to high-temperature baking, up to 550°C when baking in N2 after a 170°C soft bake step. This means precise planarization and gapfilling are possible without worrying about dimensional changes, maintaining the integrity of valuable components.

High Thermal Stability: OptiStack® SOC450 material can withstand high-temperature vacuum-deposited SiXn films over 200 nm. The high thermal stability enables integration schemes utilizing chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) processes.

OptiStack® SOC450 material offers narrow trench and high-aspect ratio gapfilling, including a complete fill, without void or delamination.

CMP Compatibility: When a strict global-level planarization is needed, OptiStack® SOC450 material can be further planarized by chemical mechanical planarization (CMP) for use in high topography, and/or highly variable pattern density devices. With many spin-on carbons facing challenges with long-range planarization, the ability to OptiStack® SOC450 material enables superior planarization by controlling the rate of removal, based on the slurry and pad type.

CVD Processing: Chemical vapor deposition (CVD) can pose many problems if the spin-on carbon material vaporizes or sublimates, including contamination that leads to defects. Ineffective CVD can cause film thickness variation or that challenge the integrity of the device. Off-gassing, delamination, and cracking are also seen with traditional SOC thermal decompositions. OptiStack® SOC450 material does not sublimate or vaporize in conditions up to 400°C, and demonstrates superior stability in conditions up to 550°C.

Increase Efficiency: High carbon content of OptiStack® SOC450 material enables CF4 plasma etch rates better than SiOx. Ultralow metal ions less than 1,000 part-per-trillion ensure decreased post-etch defects. Additionally, the solubility in fab-friendly solvents and compatibility with other spin-on materials eliminates potential drain clogging issues.

OptiStack® SOC450 material will redefine what you expect from high-temperature-stable, gapfilling planarizing materials. Its unique combination of thermal stability, zero shrinkage, and exceptional performance will enable new possibilities for your products, helping you achieve unprecedented levels of quality and reliability. Don’t settle for compromises between thermal stability and superior gapfilling when you can have it all with OptiStack® SOC450 material. Connect with a product expert or learn more by visiting our website.

About Brewer Science
Brewer Science is a global leader in developing and manufacturing next-generation materials and processes that foster the technology needed for tomorrow. Since 1981, we’ve expanded our technology portfolio within advanced lithography, advanced packaging, smart devices, and printed electronics to enable cutting-edge microdevices and unique monitoring systems for industrial, environmental, and air applications. Our relationship-focused approach provides outcomes that facilitate and deliver critical information. Our headquarters are in Rolla, Missouri, with customer support throughout the world. We invite you to learn more about Brewer Science at www.brewerscience.com.

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Xpeedic of Cupertino, Calif., unveiled RF EDA Solution 2023 edition today at the IEEE MTT International Microwave Symposium (IMS) here, showcasing its ability to accelerate the design of highly integrated RF modules and systems using its differentiating chip-package-system EDA tools and mass-production proven Integrated Passive Devices (IPD) IP.

The RF Electronic Design Automation (EDA) Solution includes XDS, Xpeedic’s RF system-level design and simulation platform, IRIS, its on-chip passive modeling and simulation tool, and iModeler, a passive model generation tool.

XDS provides schematic design and simulation, post-layout electromagnetic simulation with both method-of-moments (MoM)- and finite-element-method (FEM)-based solver technologies, electro-magnetic (EM) circuit co-simulation and tuning/optimization. In the new 2023 edition, XDS features a new filter synthesis algorithm and supports parametric padstack and permittivity, SNP-based LC matching in Smith Chart, bondwire simulation and hierarchy design for schematic and layout.

IRIS has been widely adopted for RFIC designs and certified for advanced process nodes. In the new 2023 edition, IRIS upgrades its accelerated 3D EM solver engine with improved run time and peak memory usage.

iModeler now includes built-in MoM cap, MiM cap, inductor and transformer templates, enables parameterized result exploration using built-in templates.

Xpeedic at IMS
Xpeedic will be in Booth #1121 at the IEEE MTT International Microwave Symposium (IMS) in the San Diego Convention Center in San Diego. Hours are today from 9:30 a.m. until 5 p.m., Wednesday, June 14, from 9:30 p.m. until 6 p.m. and Thursday, June 15, from 9:30 a.m. until 3 p.m. Attendees can stop by the booth to schedule demos or meetings by sending email to [email protected].

“Overview of Integrated Passive Devices (IPD) for RF Front-end Applications” will be presented by Xpeedic Wednesday at 3 p.m. at the MicroApps Theater in Booth #2447.

About Xpeedic
Xpeedic is a leading EDA provider to accelerate designs and simulations of next generation high-frequency, high-speed intelligent electronic products. Powered by its proprietary electromagnetic, circuit, and multi-physics solver technologies, Xpeedic is addressing challenges in designing IC in advanced nodes, 3D-IC with advanced packaging, high-speed digital, and RF systems for the markets including data center, automotive, communication, mobile, and IoT. Founded in 2010, Xpeedic has offices in both U.S. and China. For more information, please www.xpeedic.com.

Engage with Xpeedic
www.xpeedic.com
Twitter: @xpeedic
LinkedIn

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Xpeedic of Cupertino, Calif., today announced its Integrated Passive Devices (IPD) shipments surpassed an unprecedented two-billion units accomplished through its mass production-proven IPD development platform that enables proliferation of IPDs to RF front-end modules.

Xpeedic’s IPDs and IPD development platform will be showcased today through Thursday at the IEEE MTT International Microwave Symposium (IMS) in San Diego.

“This is a momentous milestone for Xpeedic,” remarks its CEO Feng Ling. “Our commitment to continue addressing RF and other significant design challenges remains unchanged.”

Adoption of Xpeedic’s IPDs is driven by the need for smaller, high-performance, cost-effective, and reliable electronic systems across various industries. Advantages of the solution include:
• A rich set of IPD libraries on various IPD processes, such as high-resistivity silicon and glass for common, ready-for-mass production building blocks used in RF front-end modules.
• Trusted foundry and packaging ecosystem partners supporting both quick prototype and mass production.
• Home-grown electronic design automation (EDA) design flow tailored to meet specific needs for greater efficiency and productivity. Developing an in-house EDA design flow also fosters innovation and differentiation by incorporating internal design methodology that results in unique designs with competitive advantages.
• A dedicated and experienced design team enabling quick turnaround for customized IPDs.

Xpeedic at IMS
Xpeedic will be in Booth #1121 at the IEEE MTT International Microwave Symposium (IMS) in the San Diego Convention Center in San Diego. Hours are today from 9:30 a.m. until 5 p.m., Wednesday, June 14, from 9:30 a.m. until 6 p.m. and Thursday, June 15, from 9:30 a.m. until 3 p.m. Attendees can stop by the booth to schedule demos or meetings by sending email to [email protected].

“Overview of Integrated Passive Devices (IPD) for RF Front-end Applications” will be presented by Xpeedic Wednesday at 3 p.m. at the MicroApps Theater in Booth #2447.

About Xpeedic
Xpeedic is a leading EDA provider to accelerate designs and simulations of next generation high-frequency, high-speed intelligent electronic products. Powered by its proprietary electromagnetic, circuit, and multi-physics solver technologies, Xpeedic is addressing challenges in designing IC in advanced nodes, 3D-IC with advanced packaging, high-speed digital, and RF systems for the markets including data center, automotive, communication, mobile, and IoT. Founded in 2010, Xpeedic has offices in both U.S. and China. For more information, please www.xpeedic.com.

Engage with Xpeedic
www.xpeedic.com
Twitter: @xpeedic
LinkedIn

• Read more about Xpeedic Ships Unprecedented Two-Billionth Integrated Passive Device

Axiomise, the leading provider of cutting-edge formal verification solutions that include training, consulting, services and custom apps, today launched its next-generation formalISA® app with open-source, formally verified RISC-V processors such as cv32e40p and WARP-V.

Also announced today is a new RISC-V Studio Portal with real-world formalISA applications and product demonstrations to help the RISC-V ecosystem understand the necessity of exhaustive formal and the kind of bugs that can be caught with formal methods.

“We are excited to share the app launch in conjunction with a new studio portal with real-world applications of formalISA and product demos,” remarks Dr. Darbari. “The app will enable the wider ecosystem of RISC-V to see why exhaustive formal verification is a necessity and what kind of bugs can be caught with formal methods. formalISA app is a powerful offering in realizing our vision of making formal normal. Axiomise has the tools and the skills to become the ‘go to’ RISC-V Verification expert.”

Dr. Darbari and his team will be at the RISC-V Summit Europe to demonstrate formalISA in Bay 7 from Tuesday, June 6, to Thursday, June 8, at Hotel Barcelo Sants in Barcelona, Spain.

About formalISA
Axiomise’s formalISA is a push-button formal verification solution used for architectural and micro-architectural verification of RISC-V processor cores. Initially launched four years ago, it has been used to formally verify numerous open-source and commercial RISC-V processors by identifying deep corner-case bugs and mathematically proving the absence of bugs on complex out-of-order and in-order cores.

A state-of-the-art proof status dashboard captures reporting and coverage information and provides full automation, saving time and cost. formalISA is powered by i-RADAR®, and a reporting and coverage solution called SURF.

formalISA is available now. Pricing is available upon request.

About Axiomise
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, FIETE, DPhil (Oxford), who has been a formal verification practitioner for more than two decades with 60 patents in formal verification and over 70 publications.

Engage with Axiomise at:
Website: www.axiomise.com
Twitter: @axiomise
LinkedIn: https://www.linkedin.com/company/axiomise/
Facebook: https://www.facebook.com/axiomise
Axiomise, formalISA and the Axiomise logo are trademarks of Axiomise Limited, UK.
Making formal normal is a registered trademark of Axiomise Limited, UK.

• Read more about Axiomise Launches Next-Generation formalISA App for RISC-V Processors

Virginia Beach, Virginia - Busch Vacuum Solutions, a leading provider of reliable solutions for SubFab Management, is proud to exhibit at this year's SEMICON West show and conference. As a reliable partner for vacuum pumps, gas abatement systems, leak detection and more, Busch provides the semiconductor industry with the highest quality solutions and services.

At SEMICON West, Busch is showcasing their comprehensive subfab management services. Critical SubFab systems are monitored and predictively maintained by Busch. Their SubFab management minimizes production downtime and enables energy-efficient operation and cost savings. Continuous monitoring extends maintenance intervals and the entire product life cycle. All Busch on-site service teams are certified to ISO9001:2016, ISO14001:2016 and ISO45001:2018 standards.

"We are proud of our comprehensive solutions for the semiconductor industry," said Mark Magill, Vice President of Medium High Vacuum at Busch Vacuum Solutions. "SubFab service capabilities and innovative products provide customers with reliable performance and maximum process safety to achieve optimal yields."

Magill also said they are featuring a new patented redundancy vacuum system at the show, “It uses an optimized combination of two pumps plus one booster to minimize changes in chamber pressure in case of pump failure.” This vacuum system eliminates wafer scrap and process excursion.

Visit Busch Vacuum Solutions at SEMICON WEST from July 11-15 in San Francisco, CA. Meet their experienced vacuum experts, exchange ideas and get valuable advice at booth #541.

About Busch
For more than 50 years, Busch has been an integral part of the global semiconductor industry by providing reliable solutions that enable manufacturers to produce advanced microchips. Their commitment to quality is in every product they offer and service provided. Continuous advancements ensure that Busch solutions are always state-of-the-art and used by hundreds of subfabs worldwide. www.buschusa.com | [email protected]

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PEER Group® has announced an upcoming webinar designed to help semiconductor equipment manufacturers prepare for the increasing demand from backend factories for automation capabilities and SEMI® Standards compliance in assembly and test processes.

Taking place on June 22, 2023, at 1:00 p.m. ET/11:00 a.m. MT, the webinar, Standardizing the Assembly and Test Process, will feature an in-depth discussion between Jason Cicero, Micron Technology’s Senior IT Domain Architect, and PEER Group’s Director of Marketing, Doug Suerich.

Topics covered will include: why the backend, including assembly and test, needs more automation and standardization, how this will impact equipment design and integration, common issues faced by factories when integrating new tools, and how equipment suppliers can help solve these issues. There will also be a live Q&A for attendees to ask questions during the webinar.

“The SEMI Standards Program has been around for more than 40 years,” says Suerich. “During that time, these standards have evolved into the guiding principles which ensure compatibility and interoperability across suppliers and factories, improving manufacturing productivity, quality, and reliability, and reducing the cost and pain of integrating new equipment onto the factory floor. Universally adopted in the frontend, we are starting to notice increasing demand from factories to implement standards in the backend, including assembly and test processes.”

Evidence of this shift is seen as major players in the frontend enter the assembly and test market while established facilities announce major capital investments into their operations. This expansion introduces new, high-value processes to assembly and test and closer integration with the frontend – both of which are enabled through the application of standards. Meanwhile, the SEMI Advanced Backend Factory Integration task force continues to investigate and promote the adoption of SEMI Standards for assembly and test.

The webinar is scheduled to last 30 minutes followed by a 15-minute Q&A. All registrants will have the opportunity to access a recording of the webinar. For more information, including how to register, visit: https://bit.ly/3mq2yf3

About PEER Group
PEER Group® is the largest supplier of innovative factory automation software products for the semiconductor industry. Since 1992, our solutions have helped the world’s most advanced OEMs and factories reduce time to market and lower costs by solving their equipment automation, data management, and process control problems. A multi-award winning company, PEER Group has been named a Best Workplace by Great Place to Work Canada 11 times, and most recently was one of six recipients of Intel’s 2022 EPIC Outstanding Supplier Award, which recognizes the absolute top performers in the Intel supply chain. Follow PEER Group on LinkedIn and Twitter at @PEERgroup_Inc..

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PENANG, MALAYSIA - MAY 2023 ViTrox, which aims to be the world’s most trusted technology company, is honoured to announce our participation at Semicon Southeast Asia (SEA) 2023 as a Platinum sponsor! We will be showcasing our breakthrough innovations at Booth #A304 in Setia SPICE Arena, Penang, Malaysia from 23rd to 25th May 2023.

Semicon SEA is one of the biggest and most influential events in the regional semiconductor industry, attracting thousands of visitors from around the world. The event provides an excellent opportunity for us to unleash cutting-edge New Product Introductions (NPIs) and a full range of inspection solutions, ranging from Middle & Back-end Semiconductor Vision Solutions to SMT PCB Assembly Vision Solutions, Electronics Communication Systems, and Industry 4.0 Manufacturing Intelligence Solutions – V-ONE, and engage in networking sessions with customers while sharing knowledge. We are excited to meet with industry professionals and players physically.

You will be able to experience the wonders of our advanced and Industry 4.0-ready solutions through our live product demonstrations and new product launch sessions, which is the key highlight of our participation in this grand event. Among the NPIs that will be showcased will be the:
• Wafer Vision Inspection Solution – the Wi8i G2 PRO!
• Die Sorting and Vision Inspection Solution – PX740i
• Advanced 3D Solder Paste Inspection (SPI) Solution for advanced packaging and microelectronics.
• Advanced 3D Optical Inspection (AOI) Solution for advanced packaging and microelectronics.
• V-ONE’s All-New Imaging Analytics with Deep Learning – DeeLIA

In addition, visitors will also have the opportunity to attend insightful sharing sessions from our technical experts at TechStage on 24 & 25 May (Wednesday & Thursday), SMART Enterprise Forum on 24 May (Wednesday) and Advanced Product Testing Forum on 25 May (Thursday)! Furthermore, we have also prepared a mini virtual-reality game called “Treasure Hunt”, whereby visitors get to virtually experience ViTrox Campus 2.0 and learn more about our company's background and culture.

Another thrilling news is that we will be stationed at the Workforce and Talent Development Pavillion (Booth #A1012) to showcase both career and education opportunities with ViTrox. The education arm of ViTrox – ViTrox Academy (VA) team will be on-site to promote their available courses and training programmes and our People Management team will be there to welcome aspiring candidates looking to join ViTrox! Moreover, the Sr. Manager of People Management, Ms Yeoh Siew Eng, will share about our company’s background and culture, internship and career opportunities at ViTrox.

ViTrox team is well-prepared and ready to present innovative solutions and technologies during the show! It's a great platform for us to reconnect and meet with our customers and visitors in person after the pandemic! Please send in your appointment request via the registration link to meet up with our field experts in person!

Registration Link: https://docs.google.com/forms/d/e/1FAIpQLSfXQoB0pe-RLHRY2oi4cJ0XVNNVBja…

• Read more about ViTrox Features Cutting-Edge Vision Inspection Technologies and Solutions at Semicon Southeast Asia 2023: Don't Miss Out!

Verific Design Automation today announced Vorak Solutions is its vendor of choice to assist Verific customers to accelerate projects that implement its SystemVerilog, Verilog, VHDL and UPF Parser Platforms.

“Vorak engineers are well-versed in Verific’s APIs,” remarks Rick Carlson, vice president of sales at Verific. “They are highly experienced and able to jump in to do small- to medium-sized projects, quickly understanding the project scope and details, communicating regularly and delivering high quality on schedule and on budget. We couldn’t have a better engineering services partner.”

Founded in 2015 in the United States and Armenia, Vorak Solutions provides cost-effective and high-quality development and quality assurance services for software, cloud migration and electronic design automation (EDA) flow integration and quality assurance testing.

Vorak’s knowledge of the Verific parser platforms and engineering expertise has been used to develop numerous applications and programs for Verific customers including Rapid Silicon and other noted semiconductor companies. It accelerates application development projects for customized solutions, product development and testing. In one example, a floorplan estimator was developed for a Verific customer who needed block-level initial estimates. In another, Vorak designed a custom hierarchy report that specified characteristics at each level.

“Verific is a company with a reputation of providing exceptional value and it’s a pleasure to work alongside its engineers,” says Georgi Mikichyan, COO of Vorak. “Our projects implementing the Verific parser platforms or building on top of the platforms always reinforce that Verific’s reputation is well warranted.”

About Vorak Solutions
Vorak Solutions, founded in 2015 in the United States and Armenia, was formed by experienced professionals from both countries based on a long-standing successful collaboration of the management and engineering teams. Vorak, Armenian for Quality, provides high-quality development and quality assurance services in the areas of software, cloud and EDA products at a fraction of first world engineering costs.

About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:
Email: [email protected]
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

• Read more about Verific Confirms Vorak as its Vendor of Choice for Providing Custom Development Services to Verific’s Customer Base