Today, AI algorithms are primarily run at large data centers-- in the cloud. For this intelligence to be used at the edge, data must be transmitted to the cloud, analyzed there, and the results transmitted back to the field of operation, such as a mobile phone, medical implant or autonomous vehicle.

As we round the corner on 2021, the microelectronics industry continues to face a severe talent crisis. With more than 34,000 jobs remaining unfilled at SEMI member companies in the United States alone, everyone is competing for the same talent pool. While the semiconductor shortage has received extensive media coverage, a critical talent shortage deserves equal attention. One way to address the talent shortage is to hold the line. Meaning, in addition to recruiting more diverse talent into the chip industry, we must retain the quality workforce we have. I believe that a key component of a diversity, equity and inclusion program must be retention. At Edwards, we feel so strongly about this that we have made retention a key part of our Diversity, Equity and Inclusion program – even changing the acronym to DEIR (pronounced DEER; diversity, equity, inclusion and retention) for emphasis. There are three overarching approaches we can take to promoting diversity-focused retention:Investment in on-boarding practices that allow time to hire appropriately and ensure a diverse pool of qualified candidatesEmbedded programming and policies that are learning and development (L D) based including career planning, succession planning, unconscious bias training, employee resource groups (ERG) and mentoringCorporate culture that respects employees through a healthy work life balance and promotes the well-being of society and the planetThis is a very important conversation. I asked Lubab Sheet-Davis, vice president of Strategy Innovation in the Office of the CTO at Lam Research, and Emerald Greig, executive vice president Americas at SurplusGLOBAL USA, to share their considerable experience and insight related to retention and DEI. Following is an excerpt from our conversation, which has been edited for clarity and brevity.Balaguer: In the context of DEI, why is employee retention so important?Sheet-Davis: In my view, there is a strong correlation between inclusion and retention. If people feel that their voices and perspectives are valued, they are more likely not only to stay, but also to perform at a higher level. Driving both inclusion and retention is having a seat at the table, having your voice heard, respectful treatment and fair opportunity. Retention is a core component of our inclusion and diversity strategy, which involves increasing representation by building a pipeline of diverse candidates, recruiting and retaining, fostering an inclusive culture (which supports retention) and open communication to share our progress.Balaguer: What role does data play in the drive to increase retention?Greig: Ours is a data-driven industry and I am surprised that we have not let the statistics drive us into action sooner. Clearly, diversity, equity, inclusion and retention all affect the bottom line. Millennials and Gen Zs already leave faster than any other generational group. The turnover rate in the tech industry averages around 13% with stays around 2-3 years.The cost to hire, train and integrate someone into a company is far more expensive than having a DEIR program in place to keep them. The Society for Human Resource Management (SHRM) reported that, on average, it costs a company 6 to 9 months of an employee's salary to replace them (which includes the costs of hiring, onboarding and training, L D and time to fill the role). For an employee making $60,000 per year, that comes out to $30,000 to $45,000 in recruiting and training costs.Sheet-Davis: Yes, which gives us all the more reason to move quickly! Given how central DEIR is to innovation, and that the challenges and opportunities facing our industry are bigger now than ever before, I believe we should be addressing DEIR with the same vigor that we address Moore’s Law.I worry if we keep saying DEIR will take time, it will take time. Granted many DEIR issues are cultural and culture is hard to change. However, this industry has demonstrated the capability to drive breakthroughs and to do so quickly. Let’s focus on DEIR with urgency while also ensuring the progress is sustainable.Balaguer: There is no doubt we need to move with a sense of urgency. I think a good way to keep the pedal to the metal is to create a DEIR roadmap that tracks our progress on multiple programs and helps us be accountable and stay focused. Meaningful retention strategies begin with solid diversity-focused hiring strategies.Balaguer: How does corporate culture inform retention?Greig: Let’s not forget: Employees, especially millennials, are looking for a corporate culture that demonstrates social responsibility as well as leadership and career development. In a recent study, 65% of employees said positive corporate culture has encouraged them to stay with their company. In fact, companies with strong cultures have seen a four-fold increase in revenue growth.We have raised a generation that strongly believes in being accepting of others and embraces equity and inclusion in their daily lives. They expect their employer to have this as part of their DNA. They believe in science, climate change, recycling, conservation, and similar sustainability issues and they want to know that they are making or doing something that makes the world a better place. If tech companies cannot convince millennials and Gen Z's that the companies are socially responsible and are doing all they can to embrace DEIR as part of their company culture, then the millennials will go elsewhere. Balaguer: How can employee resource groups be a building block for retention?Sheet-Davis: We support employee resource groups that are voluntary, employee-led and coalesce around demographic factors such as gender, ethnicity, sexual orientation or generation. Each has an executive sponsor, budget, plans and leadership structure. ERGs support inclusion by creating a sense of belonging, building comradery, and providing a safe space to raise awareness and help educate the rest of the company through a number of activities such as community service, holiday celebrations, guest speakers, networking, training courses and more. I serve as the executive sponsor of our Women@Fremont group, which is focused on accelerating the advancement of women in their early to mid-career at Lam’s headquarters. I know ERG members genuinely value the company’s support.Balaguer: What can we do during the hiring process to lay a strong foundation for employee retention?Greig: I believe that the work we do at the front end in terms of hiring practices are one of the main reasons we have a low turnover rate at SurplusGLOBAL. We have a policy to have three interviews for each candidate. Not three different people, but bring them in three times. Additionally, we have a 90-day trial and review period to make sure there is a good fit for both parties. Investing time up front ensures the right hire and the small size of our company allows us to know our employees. We can be nimble and quickly respond to employee needs as they arise.Balaguer: In what ways do you think mentoring can help improve retention?Sheet-Davis: Another aspect of building a more inclusive culture, and hence promoting retention, is through mentoring programs. Mentorship supports an employee’s development, growth and career planning. It’s a great way to get to know people, understand their ambitions and support their development. Hopefully, it results in sponsorship because that is what helps drive career advancement. Ultimately, I want to advocate for those that I mentor.Balaguer: At Edwards, we are refreshing mentoring as part of our DEIR program. I see mentoring as a program that can support employee retention in multiple ways including career planning, professional development, succession planning and promoting inclusivity. Encouraging and empowering personal development is key in growing a productive workforce and mentoring does all these things. Often overlooked is the fact that mentoring is a benefit to both the mentor and the mentee. I have personally mentored several young professionals at Edwards, and I can attest that I have learned as much from them as they have from me. Mentoring is definitely a two-way street.Balaguer: What’s your message to our readers about retention as an element of diversity, equity and inclusion?Greig: I am excited to see DEIR and especially, retention, gaining traction. The semiconductor industry has always tended to have a cyclical rhythm to it. A generation of potential employees have grown up witnessing the fallout from periodic down cycles and the inevitable reductions in workforce. I think there is an element of rebranding we need to do in this area to support our retention efforts. Sheet-Davis: If we only focus on recruiting and not retention, we tread water. Consistent with any other successful business strategy, a holistic integrated approach to DEIR that is prioritized, resourced and sustained over time is key. Balaguer: We all agree that retention is a key component in the war for talent. While this conversation has been more wide-ranging than we can share with our readers, the prime takeaways have focused on these elements: Follow the data. Execute with a sense of urgency. Hire right. Work hard on inclusionary programming such as ERGs, mentoring and sponsorship. Build a genuine corporate social responsibility program. Retention will result.Many thanks to Lubab Sheet-Davis and Emerald Greig. As always, comments, questions and suggestions are welcome. We can be reached at [email protected], [email protected] and [email protected]. I invite our readers to join the conversation, as well as review the recently released SEMI Foundation DEI Roadmap and Toolkit.Scott Balaguer is Vice President and General Manager, Semiconductor Division at Edwards Vacuum LLC and Chairman of the SEMI North America Advisory Board.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.

AEM Holdings Ltd, a Singapore-based multinational corporation, is listed in Forbes Asia’s 200 Best Under A Billion 2019 and 2020 spotlighting small and midsized companies in the Asia-Pacific region with sales under $1 billion. AEM clinched the Singapore Business Review Technology Excellence Award 2020 for Analytics-Semiconductor and the Singapore Business Awards Enterprise Award 2019/2020. These achievements are testament to AEM’s vision and innovation and the company’s contributions to the increasingly complex testing of chips in a rapidly evolving technological world. I spoke with AEM CEO Chandran Nair, a new Regional Advisory Board (RAB) member of SEMI Southeast Asia, about the company’s intelligent test and handling solutions, its role in digital transformation, the company’s key role in the smart manufacturing movement and the growth prospects for Singapore’s electronics sector. SEMI: AEM’s application-specific, intelligent system test and handling solutions for semiconductor and electronics companies serve the advanced computing, 5G and AI markets. How do you differentiate your solutions from those offered by competitors? Nair: A key differentiation for AEM is that we work closely with our customers to develop application-specific integrated test and handling solutions that meet their needs in a scalable manner from lab to production. We offer our customers customized, full-stack test and handling solutions that give them the agility to accelerate their delivery cycles and enhance product quality. Over the years, AEM has developed and acquired world-class technologies in instrumentation, test, automation, robotics, optical inspection, high-end thermal control, and software. These technology pillars, along with our deep know-how to customize test and handling solutions using the technology pillars as a platform, enable AEM to meet the fast-changing needs of our customers faced with the challenges of testing heterogeneous and complex devices. In addition to investing in technology, AEM has also invested in delivering application-specific solutions to meet customer demand. Our recently announced acquisition of CEI with its manufacturing capabilities in Vietnam and its specialization in low-volume, high-mix manufacturing increases our geographical reach and our ability to quickly turn application-specific test and handling solutions to be deployed. We have a unique and differentiated approach that enables our customers to test high-performance computing devices, automotive devices, and mobility devices with maximum test coverage, cost-effectively, in a manufacturing environment. Our experience in serving the high-performance computing market that traditionally drives advancements in thermal control also puts us at the forefront of delivering comprehensive thermal management, vision, and deep automation and test solutions for the computing, automotive, and mobility markets. AEM also has a strong instrumentation portfolio, including high-density digital instruments and mixed-signal and protocol-aware instrumentation that is well-suited for ATE solutions for SoC, high-power devices, and CMOS image sensors. Over the last few years, we have also established leadership positions in developing and deploying application-specific test solutions for MEMS devices and offering wafer and frame probing stations suitable for R D, wafer sort, and final test. We form strong partnerships with our customers, provide them with end-to-end support in product development, and take them through the entire life cycle process from concept to mass production. Chandran Nair and Goh Meng Klang, vice president of operations, at the AEM manufacturing site in Singapore. (Photo credit: AEM) SEMI: Digital transformation is powering strong growth of advanced computing, 5G and AI. Will AEM be expanding its AEM manufacturing plants in China, Malaysia and Singapore to meet rising demand for these technologies in the coming years? Nair: In regards to manufacturing, AEM currently has manufacturing facilities in Singapore, Malaysia, the U.S., Finland, and China. With our recently announced acquisition of CEI, we will add manufacturing capability in Vietnam and Indonesia. AEM will continue to expand manufacturing appropriately to give our customers cost-effective solutions while maintaining our proven track record of delivering on time and scaling rapidly in times of crises like the pandemic or geopolitical disruptions. As for advanced technologies, the three key factors that will bring the full potential of 5G to fruition are 1) cost-effective, high-powered processing devices at the edge, 2) easy access to high-bandwidth communications, and 3) cost-effective sensor technology. Semiconductors are the primary drivers of these three key success factors. As devices become more complex and our reliance on semiconductor-powered devices in all aspects of our lives deepens exponentially to include mission-critical applications, AEM’s role is to ensure that our customers' electronic and semiconductor devices are shipped thoroughly tested, safe to use, and highly reliable. It is imperative that, as a testing company, we find innovative ways to help our customers test their products with maximum coverage and minimum cost. To do this, we are focusing our R D efforts and investments to continue building on our key technology pillars to ensure that we stay ahead of the curve when it comes to test and handling solutions. We prepare our customers to test increasingly complex devices manufactured on the latest process node. SEMI: During your career you’ve driven projects in test and automation and more recently robotics solutions for ports, logistics warehouses and transport. With robotics and automation a key part of Industry 4.0, what role do AEM solutions play in powering the smart manufacturing movement? Nair: The smart manufacturing movement is powered by semiconductors, software and increasingly by artificial intelligence (AI). Test is at the heart of the process of ensuring that semiconductor and electronics devices reach the consumer well-tested for reliability. With our vision of enabling A Zero Failure World, AEM addresses the necessity for safe, highly reliable devices. The semiconductor companies themselves are adopting smart manufacturing methods. AEM’s tools are Industry 4.0-ready, and we continue to invest in machine learning and data analytics, which are integral to the future of test. Our tools are automated and feature embedded sensors to provide our customers with data about tool usage, the state of a machine’s health, and more. Our tools are connected to our customers’ manufacturing automation platforms. Additionally, we continue to invest in our ability to better slice and dice test data to understand trends and patterns to help our customers analyze data and make decisions faster. SEMI: You also have experience heading autonomous vehicle projects. With the COVID-19 pandemic hastening digital transformation, do you see an acceleration in the development of fully autonomous vehicles and smart manufacturing? Research and development efforts for autonomous vehicles (AV) continue at a fast pace worldwide. With shutdowns and restricted movement rules globally, the pandemic has hastened digital transformation in many ways. The delivery of goods and services is transforming, and AV will surely play a part, especially in secure environments for autonomous transport. The pandemic has accelerated the development of autonomous vehicles and smart manufacturing technology in automation-friendly environments like factories and ports. SEMI: At the recent Global Technology Summit hosted by SEMI, you spoke about testing innovations to meet the demands of highly complex devices. Please elaborate on innovative testing solutions versus traditional testing? Nair: AEM offers a disruptive and differentiated solution, one that is driving a paradigm shift to asynchronous, modular, highly parallel, smart testing solutions. ​ The traditional approach of ATEs to test increasingly complex devices on advanced nodes has reached a point of diminishing returns as it gets exponentially more expensive to increase test coverage to acceptable levels. Additionally, as devices get more complex and companies are rapidly adopting heterogeneous packaging technologies, the realization that System Level Test (SLT) is necessary is forcing a rethink of the entire test process. AEM’s provides asynchronous, modular, highly parallel test cell solutions that enable each test cell to run SLT, final test, or burn-in all in one system and its ability to handle hundreds of test cells independently with each test cell testing multiple devices. Our solutions suddenly make comprehensive testing of every complex device cost-effective. Freeing us from legacy ATE allows AEM to provide these innovative solutions to our customers. AEM engineering and manufacturing teams in Singapore at work on semiconductor test and handling systems for global deployment at world-class semiconductor facilities. (Photo credit: AEM) SEMI: Singapore seems to be in the sweet spot of digital transformation. Singapore’s industrial production grew 8.6% year-over-year in January 2021, an expansion driven mainly by a surge in sectors including electronics, and more growth is seen in the year ahead. Digital technologies such as 5G technology and cloud computing together with continued demand for work-from-home equipment is behind this growth. What are the growth prospects for the region’s electronics sector? Nair: Singapore is well-poised to benefit from the current digital transformation accelerated by the adoption of these technologies during the pandemic. Being a safe, well-governed country with strong IP protection, excellent infrastructure, and the rule of law, Singapore is in a great position to play a central role in cloud-based services, 5G, and the semiconductor industry. Singapore’s semiconductor sector output is at a record high, and the prospects for renewed growth in the region are very good. SEMI: As a new Regional Advisory Board member of SEMI Southeast Asia, how is your industry experience relevant to the scope of this role? What opportunities lie ahead for the region? Nair: I am honored to represent AEM in the SEMI’s Southeast Asia RAB. The SEMI RAB can influence policymakers with ideas and information on the current and future needs of the industry. I also believe that SEMI Southeast Asia can cultivate a strong innovative semiconductor ecosystem that helps regional and global growth. I look forward to working with other very experienced and accomplished board members. Bee Bee Ng is president of SEMI Southeast Asia.

Becoming a Certified B Corporation™ comes with many benefits, most of them extending beyond the walls of the company and into the hands of employees, community members, and industry partners. The designation makes the meticulous and rigorous process to certification well worth the endeavor. In 2021, Brewer Science announced that it’s the first company in the semiconductor industry to become a Certified B Corporation. Our journey to become a Certified B Corporation inspired us to share our top five reasons for meeting the high standards the designation sets for both environmental and social responsibility. 1. Pave a pathway for continuous improvement B Lab™, the certifying organization for B Corps, believes in continuous improvement, and B Corps must create an improvement plan to demonstrate the areas of social and environmental performance they focus on in the coming years. Brewer Science will hold B Corp certification for three years before submitting to a renewal process. In order to be recertified, a company must score higher on recertification than on the previous certification. The assessment evaluates all facets of the company, and it’s a learning process to help the company target and identify ways to improve business practices. Brewer Science has already identified improvement areas for the recertification. We’ve implemented several human resource initiatives that are not written into policy yet, such as flexible and expanded work options. Additionally, we have expanded our use of a cloud-based learning platform to provide employees with more training options and performance conversations held quarterly instead of annually. Brewer Science scored many points for community involvement and charitable giving. However, we are still expanding community engagement by supporting or donating to a new local organization each month. Brewer Science became Certified Employee-Owned in 2020, but since it was the first year of the ESOP and shares were not yet dispersed, B Lab didn’t fully recognize the program. 2. Share the values of your stakeholders In 2006, Brewer Science started externally reporting environmental, safety, and health performance every year through its annual Corporate Sustainability Report in order to be transparent with customers, suppliers, and employees. The impact of this report on all of our stakeholders motivated us to pursue other ways to promote sustainability and inclusion as a shared asset for our customers and suppliers. In 2016, Brewer Science became GreenCircle Certified Zero Waste to Landfill, an annual certification that we have achieved every year since then. Certified B Corporations are businesses that meet the highest standards of verified social and environmental performance, public transparency, and legal accountability to balance profit and purpose. The standard is highly respected standard, in part because of B Lab’s rigor with the questionnaire and certification process. Not only does becoming a B Corp show your stakeholders that you care, and that you are walking the walk, but it also allows you to show how much your company cares through your B Corp Impact Area. Brewer Science pursued the impact area of environmentally innovative manufacturing, a category that required detailed evidence of how Brewer Science manages the manufacturing waste and minimizes its carbon footprint. The B Impact Area Scores reflect the five areas where the business excels. 3. Be competitive in an industry that demands sustainability and social responsibility Sustainability is of growing importance in the semiconductor industry. A company can convey its commitment to sustainability by becoming a Certified B Corp. The B Impact Assessment requires benchmarking to other companies in the industry in areas of social concern, such as sustainability, inclusion, and diversity. While benchmarking was nearly impossible for Brewer Science since we rank high as an innovator in these areas, we were able to not only set the benchmark for ourselves, but other industry partners who pursue B Corp certification in the future through our collaboration with B Lab. 4. Connect with a community that cares Becoming a Certified B Corporation instantly opens companies up to a network of other B Corps across the world. The more than 4,000 B Corps in 150 industries and 74 countries enables makes it easy to network in the areas such as environmental initiatives, attracting top talent, and even just using business as a force for good in the semiconductor industry. Knowing that a business is actively trying to make a positive social change will help attract top talent looking to find meaning in their careers. B Corp certification validates a company’s employee-centric culture, which can help beef up employee retention. What’s more, an exclusive job posting board called B Work, sponsored in part by B Lab, helps connect job seekers with companies that share their values. Employees are connected through an exclusive B Corporation community platform, B Hive, enabling them to collaborate and share ideas with other B Corp employees. There is also a section within the B Hive where other B Corps can share benefits with other B Corp member employees. With such a diverse range of companies that are Certified B Corps, shared benefits can include anything from discounted clothing to travel deals or even free consultations. Additionally, employees of B Corporations can collaborate on local recycling events and community engagement. 5. The bottom line Companies don’t pursue the Certified B Corp designation to drive improvements to their bottom line. Yet by sharpening their focus on environmentally sustainable initiatives and diversity and inclusion, most companies could indirectly see significant return on investment. For example, having a pathway for continuous improvement, sharing the values of your stakeholders, being competitive in the industry, and connecting to clientele and employees that value social responsibility all enable your business to grow. In the long run, becoming certified as a B Corp can save a company money by giving companies access to community data that provides insights into cost-effective ways to be more sustainable. Plus, the certification process helps companies identify wasteful spending. For more information about Certified B Corporations, and to get started on your company's application, visit the Certified B Corporation website. Jessica Albright is a content marketer at Brewer Science, Inc.

As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Higher on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries are driving demand for advanced packaging technologies that address these issues but introduce challenges of their own such as efficient power delivery to all the different domains in a heterogeneous system. SEMI spoke with Kaladhar Radhakrishnan, Intel Fellow at Intel, about heterogeneous system integration trends and new developments in the semiconductor industry. Radhakrishnan shared his views ahead of his keynote at the SEMI Connecting Heterogeneous Systems Summit, 1-3 September 2021, an online event. Join the summit to meet experts from Intel and other key industry influencers. Registration is open. SEMI: What is driving the adoption of electronics and semiconductor devices nowadays and why is the development of new and innovative technologies important? Radhakrishnan: We are living in an increasingly data-driven world where devices have become an integral part of our lives. A recent study estimated that in the United States alone, 13.6 connected devices per capita consume an average of 300 gigabytes worth of data every month. In the workplace, COVID-19 has driven fundamental business changes that has sped up the adoption of digital technologies such as virtual conferencing, remote work, and e-commerce. Organizations are realizing that a high-quality video conference can be an adequate substitute for many in-person meetings. As a result, businesses are accelerating the digital transformation in order to adapt and thrive in this new environment. Five decades of sustained exponential growth in semiconductor performance has conditioned the average digital consumer to expect more from their devices. However, there are some headwinds ahead as traditional scaling slows down and power density rises. Because consumers and businesses are now generating data at a faster rate than they can consume it, technologists need to scale compute, storage, and bandwidth even faster to keep pace. Without investments in research and development of new and innovative technologies to address these challenges, the full potential of this data will go unrealized. SEMI: What forces are heightening the importance of heterogeneous system integration? What are the implications for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries? Radhakrishnan: The semiconductor industry increased transistor density and scaled performance through classical Dennard scaling until the turn of the century. By then, the gate oxide thickness had scaled down to atomic dimensions and the exponential increase in sub-threshold leakage signaled the end of scaling through traditional methods. Since that time, the chip industry has been relying on innovations in transistor materials and structures such as high-k metal gate, strained silicon, and FinFETs to keep pace with Moore’s law. However, this alone will not be sufficient to continue scaling and the industry needs to explore other vectors to augment improvements in transistor technology. Heterogeneous integration through advanced packaging is one key technology that can help drive these gains. Technologies like Foveros can enable device density scaling by creating a 3D stack of multiple die using high-density interconnects. Heterogeneous integration enables chipmakers to move from a monolithic system designed on a single large chip to a heterogeneous system comprised of a number of smaller chiplets. The main benefit of using smaller chiplets is that they improve yield and enable application based customization of the foundry processes. However, if the disaggregation to smaller chiplets is not accompanied by an increase in on-package bandwidth, the power and performance penalties associated with chiplet-to-chiplet communication will hobble system performance. This is why advanced packaging technologies that improve die-to-die communication are key enablers for heterogeneous integration. SEMI: What are some of the key technology challenges in developing heterogeneous systems? Radhakrishnan: The obvious challenge that most people focus on is the need for improved on-package bandwidth. However, as we rely on 3D stacking to continue device scaling at the package level, it is important to comprehend power delivery and thermal challenges as well. Power to the top die has to be delivered through TSVs on the bottom die, which not only adds resistance but also reduces the useful area available on the bottom die. This problem is further exacerbated when we stack more than two die. Excessive noise on the power delivery network can cause timing issues that limit the maximum operating frequency of the transistor. Similarly, when we stack multiple die, we must take into account associated thermal challenges. For example, each interface of the multi-die stack adds thermal resistance, which makes it harder to cool the chips at the bottom. SEMI: What are some of the key global market trends that driving demand for heterogeneous and system-level integration? Radhakrishnan: The number of artificial intelligence (AI) and machine learning applications have grown dramatically due to their ability to solve highly complex problems across a wide range of segments. AI and machine learning models require more memory bandwidth and compute capabilities that are difficult to achieve without some form of heterogeneous integration. Another market trend driving demand for heterogeneous integration is the increasing reliance on custom hardware accelerators. To combat the slowdown in frequency scaling and single-core performance, we have moved to multi-core architectures by tackling the inherent parallelism in our workloads. However, Amdahl’s law tells us that such an approach will hit a bottleneck when we reach the limits of the serial portion of the workload. As these constraints slow the performance of general-purpose processors, the reliance on custom hardware accelerators to boost performance for specific workloads is growing. Heterogeneous integration at the system level with a combination of CPUs, GPUs, FPGAs and other accelerators can optimize system power and performance. SEMI: What solutions is Intel developing to address these market needs? Radhakrishnan: Intel is actively involved in the development of the industry ecosystem for heterogeneous integration. We have developed a number of innovative advanced packaging solutions such as the EMIB and Foveros that are used in products today. Intel is also developing the next generation of advanced packaging technologies, Foveros Omni and Foveros Direct, which will dramatically scale the IO density by using direct Cu-Cu bonding technology. Foveros Omni is a crucial building block technology to enable high-voltage power conversion on the package for efficient power delivery. Intel is uniquely positioned to predict the design needs for future systems and deploy its resources to develop the technology building blocks needed to continue performance scaling. Our IDM 2.0 strategy enables us to leverage our leadership in packaging technologies to design the best products and use the best IP to deliver leading products across a broad range of categories. SEMI: What do you expect from your participation at SEMI Connecting Heterogeneous Systems Summit? Radhakrishnan: I’m hoping to shed some light on some of the new technologies we have been developing at Intel to enable heterogeneous system integration. I also want to bring awareness to the power-related challenges we are facing with heterogeneous systems. I also look forward to listening to what other industry leaders have to say on the topic. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He plays a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise include integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award, the highest Intel honor an individual or small team can receive. He has authored four book chapters, over 40 technical papers in peer-reviewed journals, and has been awarded 35 U.S. patents. He has also served as an adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after receiving his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Serena Brischetto is senior manager of marketing and communications at SEMI Europe.

Autumn promises to be a busy season of policy developments on a host of issues that could significantly help – or harm – the chip industry in the United States.

Spend any time with Ansys’ John Lee, Rich Goldman or Marc Swinnen and you’ll hear plenty of optimism about the semiconductor industry even though they tick off a long list of looming design challenges. The need for reliable and effective electronic systems, they emphasize, is great and runs through high tech, aerospace and defense, automotive, IoT and 5G with communications being a common denominator. The three are especially bullish these days on changing market dynamics brought on by systems companies building company-specific bespoke, or custom, silicon. These systems companies are building chips with a different perspective and a fresh look at silicon design, a move away from the more traditional segment-specific silicon due to much more complexity. Ansys, a member of the ESD Alliance, a SEMI Technology Community, is a 4,100-employee company with a comprehensive portfolio of multiphysics engineering simulation software for product design, testing and operation products and services. John, Rich, Marc and I focused on Ansys’ semiconductor and electronics segment for our conversation. Smith: When did you notice the move by systems companies to build their own chips? What drives this trend? Lee: The inflection point was about three years ago when hyperscale data center and system companies recognized they needed an enterprise system design platform. They are designing bespoke silicon, driven to do this for cost efficiencies and to avoid relying on outside suppliers. They also want differentiation based on their specific platform needs so they can optimize compute power to their specific needs. Smith: What is driving the trend for multiphysics experience to ensure effective and reliable electronic systems? Lee: The increasing need for multiphysics analysis is acute. The physics of 3D IC, for example, brings in mechanical engineering with the convergence of mechanical and electrical as 3D emerges at the intersection of IC and System. As a result, physics becomes a necessity to analyze the stability of the chip in the package. Goldman: As well, the move to stacked chips, 3D IC and wafer-on-wafer requires thermal, electromagnetic and mechanical analysis in addition to the traditional analysis for function, performance and power. They all need to be analyzed together, not serially. It becomes multiphysics, not multiple physics. Smith: Two distinctly different disciplines – multiple physics and multiphysics – are needed for semiconductor design. How are they different? Why the need now? Swinnen: Multiple physics refers to the sheer breadth of physics that is now needed to analyze from the IC up to the largest system whereas multiphysics refers to the capability to analyze several physical effects concurrently, accounting for their impact on the design and interactions between various physics. Multiphysics are necessary to analyze the full context of the system environment – from nanometers to kilometers – for multi-chip packaging, chip-to-package-to-silicon and systems with multi-domain guidance. Goldman: A self-driving car, as an illustration, includes AI systems-on-chip, solid-state sensors, infotainment systems and radar/lidar detectors that must all work in the rain, the heat and the bitter cold. Smith: Why are design groups being reorganized to include expertise in mechanical and electromagnetic issues? Swinnen: Complexity has exploded, driven by a long list of technical requirements and, perhaps, mischaracterization. Goldman: Just consider the system on chip, mischaracterized by the semiconductor industry. The chip is never a system by itself. Rather, it is a complex component in a larger system and must be analyzed in that context. 3D IC is where this comes together and forces a recognition of physics outside the traditional scope of SoC design. 3D IC chips are much closer together on the board and it takes multiphysics embedded into the workflow of semiconductor design, packaging, system design and 3D IC to ensure they work reliably and efficiently. Smith: What is the solution? Goldman: It’s clear a specialized digital thread is necessary to move disparate groups with expertise in systems, physics and silicon together. Today, these groups or disciplines might not exist in the same company, whether it be a foundry, fabless or outsourced semiconductor assembly and test (OSAT) company. Lee: In order to unify the entire system design environment, a cloud-based, open and extensible heterogenous enterprise compute platform is required. It is similar to the SaaS-based business model and known as Simulation-as-a-Service (also SaaS). While vertical integration of design groups is already taking place at leading system design houses, there have also been advances in electronic design tools. These are starting to offer more comprehensive multiphysics capabilities including thermal, fluid dynamics (CFD), mechanical stress and reliability analysis in a single analysis cockpit. Today’s system designers face two platform challenges: First, they need an environment that is open enough to accept analysis results from multiple sources so that they can be overlapped and cross-analyzed. Second, the design platform must have the capacity to handle the enormous amounts of data generated by the latest 3-nanometer chips and 3D IC systems, and this implies an intimate coupling to elastic cloud computing. The days of an engineer writing Perl scripts and handing it off to someone else are gone. We believe that the industry is responding to this challenge with a new generation of design platforms that a cloud-native, open and extensible to allow heterogenous enterprise design. We are definitely at an inflection point in electronic design today, but the electronic industry has faced these before an we are confident it will master these challenges as well. About Rich Goldman Rich Goldman is director of marketing for the Electronics and Semiconductor Business Unit of Ansys. He holds a Bachelor of Science degree from Syracuse University and an MBA and Master of Science degree in Engineering Management. Moscow Institute of Electronic Technology (MIET)’s first honorary professor, he is also the recipient of honorary PhD degrees from Russian-Armenian (Slavnoic) University and State Engineering University of Armenia for contributions to the advancement of Armenia’s high-tech education and economic ecosystem. Rich served on EDAC’s board of directors. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University. About Marc Swinnen Marc Swinnen is director of product marketing for the Electronics and Semiconductor Division of Ansys. He holds Master degrees in Electronic Engineering and Industrial Management from KU Leuven, Belgium, as well as an MBA from San Jose State University. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Vacuum pumps, pressure gauges, and vacuum valves combined make up the biggest expense on the bill of materials for semiconductor OEMs. The semiconductor industry consumed almost $2.7 billion worth of vacuum subsystems in 2020, with over 60% supplied by vendors based in Europe.

The USEPA recently established the PFAS Low Volume Exemption Stewardship Program, encouraging all PFAS Low Volume Exemption (LVE) holders to withdraw the LVEs or submit Pre-Manufacturing Notice (PMN) applications in order to continue to manufacture and/or import the substances in the U.S.