Bob Smith

Spend any time with Ansys’ John Lee, Rich Goldman or Marc Swinnen and you’ll hear plenty of optimism about the semiconductor industry even though they tick off a long list of looming design challenges. The need for reliable and effective electronic systems, they emphasize, is great and runs through high tech, aerospace and defense, automotive, IoT and 5G with communications being a common denominator. The three are especially bullish these days on changing market dynamics brought on by systems companies building company-specific bespoke, or custom, silicon. These systems companies are building chips with a different perspective and a fresh look at silicon design, a move away from the more traditional segment-specific silicon due to much more complexity. Ansys, a member of the ESD Alliance, a SEMI Technology Community, is a 4,100-employee company with a comprehensive portfolio of multiphysics engineering simulation software for product design, testing and operation products and services. John, Rich, Marc and I focused on Ansys’ semiconductor and electronics segment for our conversation. Smith: When did you notice the move by systems companies to build their own chips? What drives this trend? Lee: The inflection point was about three years ago when hyperscale data center and system companies recognized they needed an enterprise system design platform. They are designing bespoke silicon, driven to do this for cost efficiencies and to avoid relying on outside suppliers. They also want differentiation based on their specific platform needs so they can optimize compute power to their specific needs. Smith: What is driving the trend for multiphysics experience to ensure effective and reliable electronic systems? Lee: The increasing need for multiphysics analysis is acute. The physics of 3D IC, for example, brings in mechanical engineering with the convergence of mechanical and electrical as 3D emerges at the intersection of IC and System. As a result, physics becomes a necessity to analyze the stability of the chip in the package. Goldman: As well, the move to stacked chips, 3D IC and wafer-on-wafer requires thermal, electromagnetic and mechanical analysis in addition to the traditional analysis for function, performance and power. They all need to be analyzed together, not serially. It becomes multiphysics, not multiple physics. Smith: Two distinctly different disciplines – multiple physics and multiphysics – are needed for semiconductor design. How are they different? Why the need now? Swinnen: Multiple physics refers to the sheer breadth of physics that is now needed to analyze from the IC up to the largest system whereas multiphysics refers to the capability to analyze several physical effects concurrently, accounting for their impact on the design and interactions between various physics. Multiphysics are necessary to analyze the full context of the system environment – from nanometers to kilometers – for multi-chip packaging, chip-to-package-to-silicon and systems with multi-domain guidance. Goldman: A self-driving car, as an illustration, includes AI systems-on-chip, solid-state sensors, infotainment systems and radar/lidar detectors that must all work in the rain, the heat and the bitter cold. Smith: Why are design groups being reorganized to include expertise in mechanical and electromagnetic issues? Swinnen: Complexity has exploded, driven by a long list of technical requirements and, perhaps, mischaracterization. Goldman: Just consider the system on chip, mischaracterized by the semiconductor industry. The chip is never a system by itself. Rather, it is a complex component in a larger system and must be analyzed in that context. 3D IC is where this comes together and forces a recognition of physics outside the traditional scope of SoC design. 3D IC chips are much closer together on the board and it takes multiphysics embedded into the workflow of semiconductor design, packaging, system design and 3D IC to ensure they work reliably and efficiently. Smith: What is the solution? Goldman: It’s clear a specialized digital thread is necessary to move disparate groups with expertise in systems, physics and silicon together. Today, these groups or disciplines might not exist in the same company, whether it be a foundry, fabless or outsourced semiconductor assembly and test (OSAT) company. Lee: In order to unify the entire system design environment, a cloud-based, open and extensible heterogenous enterprise compute platform is required. It is similar to the SaaS-based business model and known as Simulation-as-a-Service (also SaaS). While vertical integration of design groups is already taking place at leading system design houses, there have also been advances in electronic design tools. These are starting to offer more comprehensive multiphysics capabilities including thermal, fluid dynamics (CFD), mechanical stress and reliability analysis in a single analysis cockpit. Today’s system designers face two platform challenges: First, they need an environment that is open enough to accept analysis results from multiple sources so that they can be overlapped and cross-analyzed. Second, the design platform must have the capacity to handle the enormous amounts of data generated by the latest 3-nanometer chips and 3D IC systems, and this implies an intimate coupling to elastic cloud computing. The days of an engineer writing Perl scripts and handing it off to someone else are gone. We believe that the industry is responding to this challenge with a new generation of design platforms that a cloud-native, open and extensible to allow heterogenous enterprise design. We are definitely at an inflection point in electronic design today, but the electronic industry has faced these before an we are confident it will master these challenges as well. About Rich Goldman Rich Goldman is director of marketing for the Electronics and Semiconductor Business Unit of Ansys. He holds a Bachelor of Science degree from Syracuse University and an MBA and Master of Science degree in Engineering Management. Moscow Institute of Electronic Technology (MIET)’s first honorary professor, he is also the recipient of honorary PhD degrees from Russian-Armenian (Slavnoic) University and State Engineering University of Armenia for contributions to the advancement of Armenia’s high-tech education and economic ecosystem. Rich served on EDAC’s board of directors. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University. About Marc Swinnen Marc Swinnen is director of product marketing for the Electronics and Semiconductor Division of Ansys. He holds Master degrees in Electronic Engineering and Industrial Management from KU Leuven, Belgium, as well as an MBA from San Jose State University. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected with me for a discussion about the chip design verification space. As he pointed out, verification and validation of systems is a fast-growing and important market segment to the electronic system design ecosystem. Smith: What trends do you see in chip design? What is driving these trends? Brunet: Chip verification costs continue to grow faster than design costs because of factors such as increasing design complexity, rising computing power, surging I/O traffic activity, increasing energy consumption and the widespread use of peripherals. These dynamics are being driven by new data center networking, communications/5G, autonomous driving, artificial intelligence (AI) and machine learning (ML), and storage applications. These trends also indicate the need for more powerful verification tools and expanded verification objectives that include power and performance analysis. Hardware-assisted verification tools are perfect for meeting these demands. Smith: Chip design verification consumes the most time in a project cycle. Why is this so? Brunet: The verification of designs reaching multi-billion gates and supported by voluminous software stacks is fraught with challenges. To exhaustively check every possible state in a billion-gate design with simulation alone would require up to trillions of verification cycles. That’s why hardware-assisted verification is one of the fastest-growing technologies in EDA. Given the complexity of today’s SoC design, it’s no surprise that verification is the largest undertaking in the entire project design cycle, consuming more than 50% of it. It also has the greatest impact on quality, cost and schedule because it prevents designs from failing at first silicon. While a respin of a large design taped out at a node below 10 nanometers could cost more than $10 million, delaying delivery of a new product for a few months in a highly competitive market may cost hundreds of millions of dollars. Smith: What other challenges do engineers face trying to verify a chip design will work as intended? Brunet: Verifying an SoC design is a massive undertaking and, in parallel, verification teams are trying to streamline and optimize verification cycles. SoC design groups are tasked with completing full system-level verification prior to creating production masks by thoroughly vetting all hardware blocks, interactions between those blocks, and the software developed for the end application before the chip is built. To alleviate this enormous pressure, they are starting to adopt a shift-left methodology for early functional verification as soon as individual blocks of a SoC design become available. It helps jump-start embedded software validation before full system validation is completed to save time and allow engineers to work in parallel, not serially. While it is an effective approach, it creates the need for a complete and integrated suite of hardware-assisted verification tools to verify and validate a design’s hardware and software components. Smith: How do you define hardware-assisted verification and how does it help solve these challenges? Brunet: A typical definition of hardware-assisted verification is special purpose hardware to accelerate verification. In other words, hardware emulation and FPGA prototyping. Hardware-assisted verification is a mandatory investment as single-die or multi-die chips get larger with more complexity and more interfaces, making hardware and software code integration critical early in the design cycle. Because software performance defines a chip’s success, the need to perform software workload-based analysis is acute, not just analysis of chip functionality, but also accurate performance and power consumption in the context of real-world applications. Hardware-assisted verification is the only option when hardware and software meet. By combining emulation, desktop FPGA prototyping boards and enterprise FPGA prototyping platforms to work on the same SoC design, a verification group can assemble a complete hardware-assisted verification system for thorough and exhaustive verification and validation. Smith: Where are the big opportunities for hardware-assisted verification? Brunet: New end-user applications are coming from computing and storage, AI/ML, 5G, networking and automotive. Recently released market data from the ESD Alliance shows that in 2020, hardware-assisted verification revenues exceeded $700 million. It is reasonable to assume that revenues of $1 billion will be within reach in the next few years given the amount of chip design activity at advanced nodes below 10nm. Smith: With the design/verification and manufacturing phases of the semiconductor supply chain more closely aligning, what role does hardware-assisted verification play? Brunet: Semiconductor manufacturing and the supply chain that supports it benefits greatly from the continued innovation in verification and validation tools and methodologies. With this innovation, designs are delivered to the manufacturing flow with a much greater chance of passing first silicon with success. This reduces friction in the semiconductor supply chain since IP and chips are available when anticipated. Hardware-assisted verification is a quick-moving, highly leveraged resource that helps a design and verification team to ensure chips are manufacturable and meet the functionality, power and performance requirements for the end-product application. Jean-Marie Brunet is the senior director of product management and engineering for the Scalable Verification Solutions Division at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron, among other companies. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at [email protected]. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Adnan Hamid, CEO, founder and visionary of Breker Verification Systems, an ESD Alliance member based in San Jose, Calif., once described his job in chip design verification at AMD as “breaking things.” When it came to naming his startup, Breaker was a natural choice. After some consideration, the “a” was dropped and the company became Breker. Now Hamid is breaking the most complex semiconductor designs and Breker, moving from a startup to a scale-up company, is a noted part of the functional verification space. Smith: Why does verification continue to take the most amount of time in a project cycle? Hamid: The project cycle for semiconductor design has changed. Design abstraction has been raised to a much higher level than the days when developers were connecting logic gates. Today’s developers are typing functions that don’t include lower-level implementation details. Designs incorporate more blocks of reusable IP. Both reduce design time. Meanwhile, designs are getting bigger with more blocks of IP stitched together, all in need of testing. As design complexity grows, the amount of testing and verification increases as a square of design effort. One block requires one functional verification effort. Four blocks of IP mean up to 16 functional interactions require verification. While design is moving up the abstraction level, that’s not the case for verification, where plenty of detail must be reimplemented. Verification has certainly evolved, but engineers still think at the level of independent stimulus, response and coverage, driving the need to allocate so much time for verification. Smith: Are chips targeting artificial intelligence and machine learning applications more difficult to verify? If so, why? Hamid: Yes, absolutely and it’s an interesting challenge, especially given that machine learning is based on massively connected processing element arrays. Attempting to verify the individual processing elements and the critical interconnects is complex. AI device arrays and, interestingly, verification test content operation may both be thought of as a mathematical graph of processing elements and interconnect. Their operation involves walking through the graph form to generate a result. Finding the optimum path through these arrays is key. To understand how these systems may be effectively verified, it is worth investigating planning algorithms. Originally proposed by IBM, these hold the key to this type of verification process. The AI- style algorithm starts backward at the end of the processing element array and tracks down the most optimal and likely paths through it. At Breker, we have used these planning algorithms extensively to drive our graph-based test content synthesis process. Smith: Does system integration require verification? Hamid: Yes, it does. In the past, most functional verification has been performed at the block level. However, with the increase in more specialized SoCs, functionality is spread across multiple blocks, as well as the software running on the processors, driving full system-on-chip (SoC) functional verification. In addition, new requirements such as security and safety must be validated. A system-level infrastructure such as cache coherency and power domain execution has become more complex and these must also be tested. The new frontier in verification is ensuring a fully operational SoC. Of course, given the size of these SoCs, hardware-assisted verification such as emulation is essential, and porting tests from block simulations to SoC emulations has become a requirement. This porting process is problematic and this in turn has driven portable tests, giving rise to the idea behind Accellera’s Portable Stimulus Standard (PSS), of which Breker was a major participant. Indeed, some companies are taking this to the next level by composing their system-level testbench at the same time as they commence SoC architectural design, and then developing the hardware design, software design and test content all in parallel, in the so-called “shift-left” manner. Smith: Is “shift-left” a growing trend that are you seeing in verification? Hamid: Yes. Shift-left is taking hold in hardware and software design, giving way to an increase in early test content composition. Then as individual blocks are finished and connected, their verification is driven from this same test content, saving a significant amount of time and effort. This is a huge verification and test generation change that was inevitable given the increased time-to-market constraints and SoC complexity. Figure 1: Shift-left is ushering in the next generation of SoC verification. Source: Breker Smith: As an entrepreneur, what advice would you give someone founding a startup or thinking about starting one? Hamid: Do not take the attitude “Build it and they will come.” My best advice for an entrepreneur or fledgling entrepreneur is to solve a specific customer problem, however narrow it might seem. Including services as part of a product offering and developing partnerships with other vendors helps with this and turns your company into a solution provider not a product developer. This is essential for getting the right products to market on time and within budget, and then ultimately scaling them across the market. The ESD Alliance and Accellera are hosting a two-part webcast series on the work-from-home experience titled Remote Work, Remote Chip Design: Building Chips During a Pandemic. The first panel, Wednesday, June 9, at 9:00am PDT, will feature a discussion led by Tom Fitzpatrick, strategic verification architect from Siemens EDA verification engineers through their experiences converting their home offices into verification test labs. The second panel in July will explore how executives managed a remote workforce and explain how they plan to bring employees back to physical offices. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

As we pass the work-from-home one-year mark, most of us still work remotely and will do so for the foreseeable future. As live trade shows and technical conferences were cancelled one after the other, virtual events became the norm. And, teleconferencing became a way of life. While possibly overstating our role, we have the semiconductor industry – from system design through manufacturing and system integration – to thank for a long history of achievement that made the transition to working remotely relatively seamless and straightforward. The shift, in some cases, took some time to sort out as we set up a workable home office, moved to video conferencing with intermittent connections and settled into a routine. Nonetheless, many of us became more productive and, in some cases, even too productive. Each spoke in the global electronic products hub contributed through creativity and innovation with a pinch of ingenuity and grit. Of course, we could have worked remotely 10 years ago, but not nearly as efficiently. Over the last 10 years, the economy moved to the cloud, producing new opportunities across the global market. Many of these opportunities were made possible by the electronic system supply chain and combination of semiconductor technology, electronic product innovation and people who figured how to leverage it with software platforms to tie it together. Zoom, one of our teleconferencing lifelines, is a good example, as are Netflix, our ongoing source of entertainment, and Roblox, a platform to build games. Facebook, Twitter, LinkedIn and the like sourced the news for us and kept us in touch. Amazon delivered our online purchases and GrubHub brought us our takeout dinners. All rely on cloud computing with thanks to the semiconductor industry. Another great example are data centers powered by semiconductors and the amount of data they processed last year. According to International Data Corporation (IDC), 64.2 zettabyte (ZB) of data was created or replicated due to the dramatic increase in the number of people working, learning and entertaining themselves from home. (Its revised model for global data creation and replication predicts the CAGR will grow to 23% over the 2020-2025 forecast period, a sure bet that the semiconductor industry will address ways to manage the growth, possibly through new AI chips.) Our connectivity is driven by smartphones optimized for low power and the performance of more complex chips. Over the last 10 years, design tools have been enhanced and new methodologies have been introduced to respond to the needs of the increasing complex chips for applications that demand high bandwidth, low latency and reduced power consumption and area. Manufacturing is retooling for higher automation under smart manufacturing initiatives and packaging is even more sophisticated with increasing integration and the 2.5D and 3D packaging rollouts. Let’s take stock of our success. The semiconductor industry has a storied tradition of breakthrough technology since its inception. The consumer electronic product craze started when the first PCs were rolled out in 1971, notes the Computer History Museum. Primitive laptops that followed in 1986 gave way to notebooks in 2007 and the ubiquitous smartphone in 2002 – and the rocket fuel for much of this was the buildout of computer networks, hyperscale datacenters and the cloud. Nothing’s been the same since. The next time we turn on our laptop, click on the link for the latest teleconference from our remote home office in comfortable sweats sitting in our ergonomic chair, let’s take a minute to acknowledge our industry’s grand achievement. And, thank one and all for their contribution and consider what’s coming next. About the Author Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Strategic Association Partner. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

No, that wasn’t a fancy chandelier on the periphery of ES Design West’s exhibit area, the co-located event at SEMICON West. It was IBM’s Q quantum computer, a striking bit of industrial design that looks like a chandelier from a stately ballroom.While it resembled an ornate lighting fixture, IBM Q does much more than illuminate a room. The Q contains 20-quantum bits (20 qubits), equivalent to 2**20 or two to the 20th power classic bits. Impressively, IBM is currently readying (or may already have) a 50-qubit computer.During ES Design West, IBM demonstrated the Q Experience quantum cloud services platform and Qiskit, an open source quantum software framework. IBM’s booth staff showed how Q can solve problems beyond the practical reach of even today’s conventional supercomputers. Examples include the Traveling Salesman Problem (TSP) of finding the shortest route to enable the salesman to visit every city once and return to the starting point. Other examples are chemistry, drug and medicine discovery, weather and climate modeling, and security and advanced cryptography.The demos did even more, highlighting just how far semiconductor design and manufacturing advances have come to make quantum computing architecture possible.We have Dr. Jeffrey Welser, vice president of IBM Research–Almaden, to thank for bringing Q to SEMICON West and ES Design. During his keynote, The Future of Computing: Bits + Neurons + Qbits, he noted that Quantum computing holds the potential to solve problems even the most powerful classical computers cannot and challenges our community to drive innovation from materials to devices to systems. Both he and the booth staffers made the point out that Q will not replace conventional computing but augment it to solve complex problems beyond computational limits and/or the storage capacity of conventional computers.Challenges of Quantum Computing are not insignificant, however, and start with coherence time or the time interval over which the qbit is in a quantum state. The 20-qbit Q shown at ES Design West has a coherence time of 90 microseconds. Noise and variance are other challenges. The IBM booth staff said that a typical program must be run at least 1,000 times. Results are filtered with the extremes removed to get the most consistent result.Fault tolerance is high on the list of challenges as well because a solution for fault tolerance in quantum computing has yet to be discovered. Users like us take fault tolerance for granted in modern classical computers, addressed in hardware and firmware. Programmers don’t need to be concerned about it because the computer takes care of it through error correction.Finally, Q and most other quantum computers require near 0 Kelvin temperatures to operate. The refrigeration systems are large, expensive and not easily portable. Research is ongoing to find materials, such as carbon nanospheres, that will allow quantum computing at room temperature.Most experts agree that we are years away from practical deployment of large quantum computer systems. IBM’s open system for users around the world to access a Q computer to run programs is helping drive the way forward.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Strategic Association Partner. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.