Bob Smith

Electronic Design Automation (EDA) is essential for the entire semiconductor design-to-manufacturing process. EDA tools streamline the design process, speed up development cycles, and ensure higher precision in chip design. Accellera Systems Initiative, an independent standards body, focuses on standards for system-level design, modeling and verification used extensively in the EDA ecosystem. These standards facilitate industry-wide collaboration and accelerate innovation, working closely with many members of the Electronic System Design (ESD) Alliance.Bob Smith, Executive Director of the ESD Alliance, recently talked with Lu Dai, Senior Director of Technical Standards at Qualcomm and Chair of Accellera Systems Initiative about Accellera’s new and future standards, and its successful global Design Verification Conference (DVCon) events.Smith: What’s new in Accellera’s standards effort since we last spoke?Dai: We are working on two new initiatives. The first and biggest initiative is our recently formed Federated Simulation User Group. Our members requested an end-to-end simulation environment or models that can be plugged into a system-level simulation environment. This challenge triggered industry-wide discussions among Qualcomm, NXP and many other semiconductor companies, especially those from Europe tied to auto and avionics industries.The need for this new standard effort is being driven by industries such as automotive where tiny microcontroller chips are traditionally used. The automotive industry has some existing simulation standards that include physical devices. With autonomous vehicles, systems on chips (SoCs) are replacing microcontrollers and handling system-level features that require rigorous system-level simulation. The user group is tasked with reviewing current automotive industry simulators and discovering how our traditional register transfer level (RTL) code- or emulation-based simulations could work with them via an interface.This effort has attracted new companies outside of the traditional EDA world. Ford, for example, is now an Accellera member and has a seat on our board. It’s exciting to see this collaboration.Functional safety is another initiative that we started a few years ago, also driven by the advancements in autonomous vehicles. Accellera’s focus is to define functional safety as a format that can be carried through the design stages from intellectual property (IP) to SoC, and from front-end design to back-end. Across the different stages of design and verification, an engineer can then confirm that the functional safety goal is maintained. We’ve published resources including whitepapers and are currently working on developing the language format. Smith: Where do you see Accellera’s next standards efforts?Dai: We have a mixed-signal standard coming out soon. It adds a mixed-signal interface to the SystemVerilog standard, currently under IEEE management because Accellera donated it to IEEE.A common question we’re asked is, “What are you doing with AI?” Accellera is a heavily EDA-centric standards body, and EDA tools are increasingly incorporating AI. AI consumes and outputs large amounts of data. A challenge is how to ensure the AI work output from one vendor’s EDA tool can propagate to another EDA tool. Accellera may look at defining an AI data format for EDA. It comes with a unique challenge because AI data is highly proprietary, both from the vendor’s and customer’s perspectives, so a robust security solution is needed. We may need to consider an interface standard, because companies may not be willing to share data, even with other groups that are in the same company. among their partners. They might need to hide the data and have a special interface to extract the data that they are willing to share. Accellera could investigate how to make AI deployment cross-vendor while allowing vendors and customers to protect their IP. Another area for potential new standards is around supply chain security challenges. This is a global issue driven in part by the COVID experience and geopolitical concerns. One possible approach is to use tagging. When a chip comes out of the fab, it would have a tag designating where it was designed and manufactured, and where the tooling is from. The tag would also include data about the regions or countries the design traveled through during the entire flow from design to manufacturing. Smith: Is Accellera looking into any standards or addressing any open-source design and verification flows?Lu: Accellera has been in the open-source domain for quite some time. Accellera has a language reference manual, user guides and reference implementations. Because many Accellera standards are related to language, we often work on libraries when a new language comes out and reference implementations to help our community deploy that standard. Reference implementation libraries are open source, as is our SystemC material. We have an active open-source SystemC community.Smith: I hear that the DVCon conferences are expanding globally. What’s driving that?Dai: Engineers enjoy attending conferences in person where they can reconnect with peers, build new connections and foster collaboration. We have regional DVCon events to bring information to our community and make Accellera more accessible to them. We now host several DVCon conferences in North America, Europe and Asia. Our next DVCon will be held in San Jose, Calif., from Feb. 24-27.Smith: How can readers of this blog post get more information about Accellera?Dai: For up-to-date information about Accellera’s activities, please visit our website: https://accellera.org/. Lu Dai is Senior Director of Technical Standards at Qualcomm and is a leader in semiconductor standards and industry organizations including Accellera. Dai holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science degree in Electrical Engineering and Computer Science from UC Berkeley.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Verific Design Automation is an electronic design automation (EDA) developer of front-end software and a member of the Electronic System Design (ESD) Alliance. Verific is also viewed as a valued supplier to many EDA, field-programmable gate array (FPGA) and semiconductor companies –– some still around, some acquired by larger EDA companies, and some long gone –– for the past 25 years. With this backdrop, Bob Smith, executive director of the ESD Alliance, talks with Rob Dekker, Verific’s founder, president, and CTO, and Michiel Ligthart, its COO, about the evolution of the company and the industry over the last 25 years, the emerging EDA products space and what’s to come. Smith: This is the 25th anniversary of the founding of Verific. How did it get started? Dekker: The company I worked for before I started Verific was Exemplar Logic (now Siemens EDA), founded by Ewald Detjens in the 1990s. Exemplar started off making an RTL-to-Xilinx FPGAs path using the VHDL hardware description language (HDL) as the entry language. I worked on the VHDL language parser. As I was doing that work, I looked at the VHDL language reference manual and made sure that all the code complied with the rules set by the IEEE standards committee. I wondered why I was doing it for just one company, because it was and still is an IEEE standard language. Every tool vendor that wants to support VHDL would have someone like me looking at the language reference manual and building a language front-end that complies with all the rules in the standard. As I gained experience and finally left Exemplar, I already knew how to make a language front-end and started building a good one for the Verilog HDL. The initial idea was not to sell it to different companies but to build an equivalence checker formal verification tool that could be installed on every designer’s desktop, where they could check their designs at various stages in the design flow. I needed funding, and started selling the language front-end thinking that no one should have to rewrite a language front-end because it's already a standard. That's when the idea came to start Verific. I wanted to build a standard language front-end, with the possibility of creating a formal tool based on that front-end. The language front-end was popular among various EDA tool vendors and startup companies. Formal tools, synthesis tools, simulators or virtual prototyping tools, emulators, and so on all need a language front-end. I was starting to license the front-end and got so busy that I asked my good friend Michiel to run the business so I could focus on the technical side. After that, we started to grow, acquired an exceptional team in India run by my friend Abhijit Chakrabarty, and hired Rick Carlson as VP of sales. It quickly became a real company, and we started to license the language front-ends to the entire EDA industry. One company wanted to license our language front-end to build an equivalence checker. At that point, we had to decide whether to stay in the language front-end business or to make an equivalence checker and compete with our customers. We decided that competing was not a good idea and chose to focus on language front-end for the EDA industry. We have been doing this ever since for most EDA tools, from startup companies, all the way to large semiconductor companies. Their tools have been built with a language front-end developed at Verific, and we are proud of that. Smith: What have you seen change since you started? Have you seen any big changes that surprised you as the industry has evolved? Dekker: I wouldn't say big changes overall, but I've been impressed by the amount of innovation in the EDA industry. The industry is dynamic, with new tool vendors coming up and good ideas being explored. We are in a wonderful industry that is vibrant with innovation and talented people. This is what impressed me about the industry initially, and it still does. At Verific, we want to be an incubator for new innovations to flourish in an EDA industry dominated by a small number of large players. Ligthart: One change that had a significant impact on Verific specifically is the introduction of SystemVerilog. When Rob started out, there was Verilog 95 and VHDL. Verilog 95 was a relatively simple language. VHDL was complicated. We saw that early customers often wrote their own Verilog parser and came to Rob for the VHDL parser. In 2005, the IEEE 1800, also known as SystemVerilog, was introduced. That was a game changer, because suddenly, adopting SystemVerilog in the Verilog customer base required a new front-end that was as difficult to create as writing VHDL parsers. That was an inflection point for the company, and it started to grow. Before then, it was a nice company. After 2005, it became a growth company. Nowadays, we equally support SystemVerilog and VHDL. They're both complicated languages. People for the past 20 years have proclaimed the death of VHDL. It did not happen and will not happen. The two languages go hand in hand in different parts of the world. Most EDA companies support both because their end users require both. Smith: Verific coined the term “bespoke EDA.” How do you define it? Ligthart: For that, we need a bit of history. Fifty years ago, semiconductor companies started to write their own software tools to design their semiconductors. Those days, it was still called CAD, computer-aided design. Over time, we saw the introduction of EDA companies that tackled singular problems like simulation, place and route, or logic synthesis, and they started replacing in-house developed tools. In the past seven years, many of the larger semiconductor companies and system companies have started to develop in-house EDA tools again. Of course, they still license most of their design tools from EDA companies, but for certain design aspects, they develop their own design flow. They write their own internal EDA tools that are specific to that company, and they don’t go outside of that company. That's what we call “bespoke EDA.” Smith: These chip companies can afford to do this? Ligthart: Yes, because they are large enough and have the people to do it. They license their SystemVerilog and VHDL front-ends from us, so they do not have to invest five years of development for that piece of their flow. They take our parsers and elaborators and build something of their own — bespoke for their semiconductor design flow. Smith: It makes me think of Google, Meta. Ligthart: Let me put it this way. Of the magnificent seven technology stocks, six have a Verific license. Smith: How do you see AI changing EDA design tools? How will AI impact you? Dekker: This question about AI is coming up quite a bit, and I have a more conservative opinion. I don't know if AI is going to change EDA tools by themselves. EDA tools are highly optimized to do a particular task, it would be difficult for AI to beat that. If it did, it would surprise me. Outside of tools, like the design exploration phase for example, I think AI might make a humongous difference. AI could make it much quicker to explore different design alternatives. Right now, several AI-based companies are engaging with Verific, and they provide the design environment to do optimizations. AI could also help engineers improve their work. This would be more at the micro level, where individual engineers use ChatGPT type of engines and language models to enhance their programming styles, algorithms, and implementations. At the micro level, I think AI has an impact. At the macro level outside of the tools, I think AI will also have an impact. I doubt AI will change anything with the tools themselves. Ligthart: I'm pretty much in line with everything Rob said. At the Design Automation Conference (DAC), we showcased our relationship with four EDA startups that are applying or are in the process of applying artificial intelligence to their design objectives. As Rob said, the first step is getting a Verific license so that they have SystemVerilog already in place. Then, they apply AI-based algorithms to tackle certain aspects of the semiconductor design cycle. In terms of how successful they are, that's up to them to prove, but we have a front-row seat to watch their progression and success. Smith: What trends in the industry are you seeing? Dekker: Niels Bohr, a renowned physicist of the 20th century, once said, "prediction is very difficult, especially if it's about the future." Our EDA industry is vibrant, and it’s hard to see where it's going. I think that the EDA industry is here to stay. EDA companies are becoming more and more popular in the stock market. This industry is 40 years old, but it’s still dynamic and still full of innovation. It's extremely important that we keep this industry open, that we share ideas with each other, and that we provide solutions for the increasing complexity of chip and system designs, especially as AI gains prominence. The industry will change, and as it changes, the requirements for EDA tools will also need to be adjusted and there's a range of directions that our industry can go in. Verific is here to support that. About Rob Dekker Rob Dekker is president, founder, CTO and principal developer of Verific’s HDL source code software. Prior to founding Verific, Dekker was a software developer, manager, and director at Exemplar Logic, where he was the architect and a primary developer of Leonardo. Dekker started his career with Philips Research in the Netherlands, where he worked on the testability of VLSI circuits. He graduated from Delft University of Technology, the Netherlands, with a Master of Science degree in electrical engineering. About Michiel LigthartMichiel Ligthart is Verific’s COO and has an extensive background in engineering, product marketing, and general management. Prior to Verific, Ligthart was vice president and general manager of west coast operations for Theseus Logic, a startup in asynchronous logic. Previously, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in electrical engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Executive Advisor Jeff Lewis held the position of Vice President of Marketing and Business Development for Artisan Components, one of the early companies developing blocks of intellectual property. Lewis, who worked at Artisan from 1996-2000, and his colleagues were members of an elite group who built the mega-successful IP market, estimated today at $7.48 billion. Arm acquired Artisan Components in 2004 for $913 million.In my role as Executive Director of ESD Alliance and publisher of the quarterly Electronic Design Market Data (EDMD) report that includes IP, I recently talked with Lewis about what he remembers from the early days of IP.Smith: You were part of the IP revolution. What were the high points and low points that you most remember? Lewis: The high point was starting with a relatively blank slate and innovating. Some things worked, some didn't. We kept trying different things and seeing what would work with plenty of failed tries, successes, and repeats. We got a chance to be on the ground floor of a new industry. Another high point was watching this nascent industry emerge into a powerhouse. In the ‘90s, EDAC (Electronic Design Automation Consortium, the predecessor to the ESD Alliance) wasn't interested in tracking IP. As the IP market started growing, EDAC was all over it because it helped pump up the size of the electronic design automation (EDA) industry. Suddenly, IP had become a big enough industry that people were starting to care. And of course, there were successful public companies like Arm, Rambus, Artisan, and others licensing IP. It was fun being part of that.The low points were the hard part. While everything was new for us, it was also new for customers. They had intense resistance to licensing IP that many viewed as product development. They would want the IP company to develop something under a consulting or NRE contract, and then they would own the product and all the IP around it. They wanted to own everything. Many companies had that mentality in the early days and were resistant to licensing or paying royalties.As a side note, Gary Smith, former analyst for Dataquest, now Gartner Group, who died in 2015, and I had an ongoing debate. We went to lunch quite frequently and he would say, “IP is great, but you aren't IP. You are a standard cell, and it is not IP.” It was one of his standard statements.He would make various presentations, and I would argue: “You can't think of it as a cell, think of it as an entire library. It's an entire library with all the design views, layouts, test and qualification data, and everything else. That’s intellectual property. Plenty of intellectual property goes into developing it.”He eventually changed his mind and agreed when he saw the revenue and the value –– IP companies do it better and cheaper than in-house development.A final high point was getting the idea and value of IP across to customers. Smith: At what point did people start to believe IP was a real market and they could trust a vendor? Lewis: I don't know if there was an inflection point. More and more people started getting used to the idea that IP was an industry. Arm was probably the major catalyst. Artisan had two different engagement models. One was the integrated device manufacturer (IDM) model. Mark Templeton, co-founder and CEO of Artisan who died in 2016, and Lucio Lanza, Managing Partner of Lanza techVentures and Artisan’s Chairman, are credited with developing the royalty model and the intellectual property category. They drove it with the IDM model. Executive Advisor Jeff LewisCustomers knew they were paying for a license, understood the terms and became both the licenser and the user of this technology. It was different when Artisan went to the foundry model, which extended the IDM model to the rapidly growing foundry space. In this model, Artisan had the ability to widely disseminate its IP to all the foundry customers for free. However, calling it a “free library” is a misnomer, because often overlooked in this process is that the foundry paid up front for every one of those libraries, and it also paid a royalty on each design that used them. Artisan was profitable from day one by building a library or memory compiler. The engagement model was one where Artisan could proliferate these to the foundry’s users. They would get the library, and the royalty would come from the foundry. Users were beneficiaries – they had a simple license agreement, but unless they needed some customization, they weren't writing checks to Artisan.From the user’s perspective, it was great. They got free libraries and IP. That helped open people’s eyes to the model that could be a good thing. Artisan had 1,000 users at one point, and it helped drive the proliferation of IP use in the industry.Smith: Is that foundry model still in place? Lewis: Largely, yes, with some exceptions because foundries have a standard library that can be used. They have some specialized IP that customers license. While there are variations, foundries provide libraries to their customers. TSMC has engineers developing libraries for its own processes. For a long time, Artisan was the standard IP provider for most of the foundries. Smith: How did companies overcome verifying and testing IP? Were engineers skeptical about buying from an unknown/unproven company? Lewis: This is an important and critical question. Engineers were skeptical about buying from an unknown or unproven company. Artisan’s library quality was our biggest selling point, and it was the same with Arm and Rambus. Size and reputation were a huge advantage.The key was to have a major win that demonstrated your bona fides, and our biggest early win was our work on the Sony PlayStation. At that time, LSI Logic was developing the chips for the PlayStation, but was looking to outsource some of the critical blocks, such as the embedded SRAMs. Sony engineers were nervous and wanted to meet the IP companies to see what they were doing, because the fate of their chip was resting on these little companies. Artisan developed high-performance embedded SRAMs that replaced the existing LSI SRAMs. Our memories were about half the size of the LSI SRAMs, higher performance, and worked the first time.What’s instructive is how Artisan later got the foundry relationships going and sold libraries. Enabling first-time success is a quality argument, because the design would work the first time. At that time, almost every foundry library had bugs in them that caused silicon failures after tape-out. Our primary argument to engage foundries was our impeccable QA story. We had customer testimonials confirming that the foundries would not have library-related failures. When foundries scheduled a volume like a PlayStation ramp, they couldn’t afford a production “bubble” or “hole” in their production schedule from a library bug causing a chip not to work and requiring a re-spin.That's why the argument on quality and first-time success was critical to TSMC.One more thing on quality, and this ties specifically to Artisan and almost all IP companies. Any company that focuses on a mass proliferation model must ensure their product has no quality problems. Mass proliferation needs to be as low touch as possible, so engineers can use it without constantly calling for support. Quality is an absolute fundamental before mass distribution, because the fastest way to go bankrupt is to massively proliferate a faulty product. Smith: According to the EDMD report two years ago, IP surpassed front-end EDA tools as the highest category. Are we now shifting into a world where IP in the form of chiplets may become the dominant player? Lewis: I think the shift is coming. These are different incarnations of Moore's Law and the Carver Mead-structured VLSI. Sometimes the structure may be a chiplet, or the structure may be embedded.Is it virtual or is it actual? Engineers will make tradeoffs with pros and cons of embedding it or keeping it separate. The deciding factor is which silicon process is best and how it will be implemented. The SEMI EDMD report’s tracking of the Semiconductor Intellectual Property (SIP) and its rise to one of the market’s leading category. Smith: You worked for several IP companies that were offering process-related IP. That's a completely different type of market selling cycle, correct? Lewis: It is, because I focused on technology licenses for manufacturing processes, as opposed to the much more understood design IP that was developed for the existing manufacturing processes. Getting inserted into a company’s manufacturing process is much more difficult and challenging.If a company is licensing a technology that modifies the front-end process, then the process parameters will change, presumably for the better. The re-optimization can be like whack-a-mole. While some parameters get better, some may get worse, and further re-optimization can be required. This can go through several cycles until the process converges. This also means that all existing IP must be recharacterized and/or redesigned, which is why it is best to insert a new technology at the beginning of the node development rather than as a retrofit.Adding new process technologies is inherently difficult unless it’s a separable piece. For example, many new memories such as ReRAM or MRAM are licensed technology and separable, because they are set up separately in the metal stack. They don't touch the transistors.For a long time now, companies have been able to pick and choose whether to do in-house development or procure design IP from a third party. We're now starting to see the same thing in process development, because they are getting so complex, and no one can be an expert in all areas. I see process IP as paralleling the early days of design IP, but with a 30-year delay. Back then, most customers were reluctant to procure design IP because they felt: “We can do it all in-house.” Almost no one says that today, and I think this gradual acceptance will apply to process IP as well.Smith: Should Mark Templeton be considered the innovator and creator of the IP industry? Lewis: I’m not sure there’s anything I can say about him that hasn’t been said already. He was a great guy and an important thinker. I credit him for doing an excellent job crafting a successful company. And, of course, Lucio Lanza was absolutely instrumental as well. He pushed Artisan to do royalties, and Mark helped drive it to fruition.About Jeff LewisJeff Lewis is one of the pioneers of the semiconductor IP industry, participating since its inception in the mid-1990s. Lewis is currently Executive Advisor for senior management and investors for semiconductor and AI companies. He was previously an operating executive serving as Senior Vice President of Business Development and Marketing at Atomera Incorporated, Spin Transfer Technologies, SuVolta Inc., and Innovative Silicon Technologies, and held operating roles at Synopsys, VLSI Technology, and HP. Lewis earned an MBA from the UC Berkeley Haas School of Business, and has a bachelor’s degree in electrical engineering, and a bachelor’s degree in economics from UC Berkeley.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

John Kibarian, CEO and founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, is a keen observer of the semiconductor ecosystem. Since PDF Solutions sits between design and manufacturing, Kibarian shared unique perspectives on both in a recent discussion.Smith: What trends are you seeing in the semiconductor industry. Are there any that surprise you? Kibarian: We see several trends that have been going on for quite a while.As much as we hear Moore’s Law is dead, there's still a strong drive to get to advanced nodes. The benefits are harder to achieve and require more than geometry scaling, but demand for these advanced nodes continues to grow. Another emerging trend is the need for insatiable compute power in data centers to support the explosion in AI applications. In recent history, the mobile phone market has been the key driver of the push to new advanced nodes, but that is changing as the performance needs of data centers and AI applications are now driving the shift.Next, as companies are still learning from the disruptions in the supply chain due to the pandemic, there’s a tremendous amount of movement to make the supply chain more resilient by expanding sourcing options for critical products or test applications. This is happening in conjunction with significant investment in high-performance compute from many countries that want to bring silicon to their shores.The next trend is that electronics companies are looking to limit investing solely in China or the U.S. Their China Plus One or U.S. Plus One strategies results in adding significant additional infrastructure and overhead. If it's not done right, it will cost the industry more money. It will be hard to sustain the cost benefits and economies of scale of the current single source model just by brute force and adding human capital. A new approach is required to manage cost effectively smaller and globally distributed manufacturing facilities.The final trend is the general electrification of the economy. Cars are moving from internal combustion engines to electric. That means more and more of our energy needs are met with electricity, putting a premium on solar and batteries. Batteries require power conversion.Silicon such as high bandwidth semiconductors on silicon carbide and gallium nitride have a tremendous amount of capacity. What is interesting is how fast and aggressive China is in that part of the market; they could be a major producer of the technologies needed to support electrification. With our exposure to the China market as well as the European and U.S. markets, Chinese manufacturers have come up quickly, and we may see a world with more viable suppliers than originally anticipated.Smith: You mentioned data centers and AI. AI is everywhere and revolutionizing the semiconductor industry. EDA companies are talking about incorporating AI. What are you observing? Kibarian: AI is used for chips that are manufactured for use in data centers. For example, our customers use PDF analytics or the Exensio platform via the cloud to analyze large amount of manufacturing data and product or test engineering data. Without this type of automated solution, only a small proportion of these data sets would actually be utilized.Companies staff their product design and test engineering using a budget based on a percentage of revenue. If a company has billions of dollars of revenue, it will put so much more into product and test engineering. But how productive can these people be? Without AI, they can only use some simple reports and graphics to analyze the subset of data they are looking at. AI solutions such as PDF’s Guided Analytics capability apply sophisticated machine learning tools to analyze entire large data sets. AI is enabling engineers to be more productive by allowing them to work with large data sets that ultimately deliver better results in the products.The amount of compute keeps going up at a rate that outpaced the rate of geometric scaling. More compute power makes it cost effective to go through large data sets and identify what is relevant.Additionally, AI is helping semiconductor companies build products. A conventional compute system is chips assembled on boards. AI is making system-in-package take off.The production flow is more complex, as fabless companies are becoming system companies. Conversely, system companies are becoming fabless companies and manufacturers. In the past, they ordered parts from their foundry of choice. Essentially, the foundry was the system manufacturer, supplying package and test yields of 99%.Now companies are building systems in more complex packages potentially with foundry partners, but this requires getting known good die. High bandwidth memory or other components from other suppliers means the company must make sure these products are available at the right time. In essence, they are becoming manufacturers and changing the way customers manage the problem of product test. They're adding more test insertion points and using machine learning and AI to be more productive.Smith: Let’s talk about digital twins or creating virtual models of everything from chips to the whole system. How do you see the impact or effectiveness of digital twins in manufacturing? Kibarian: From a manufacturing perspective, digital twins had been models for chamber behavior on a processing tool like an etch tool or TCAD simulation of devices and structures.The problem is that purely physics-based digital twins don't exist, and we must utilize empirical data. The joke was that the modeling for tomorrow’s systems was based on yesterday's technology. Trying to have the physics catch up with the materials, device structures and behaviors is why it’s so expensive to develop new technology.Principles-based models will never catch up with production. We can model 90-nanometer technology, but it doesn’t work for one or two nanometer wafers. AI and machine learning – and ways of building models using more sophisticated algorithms – can help close that chasm, and that’s starting to happen at the R D level.In production, no one has yet achieved a good merger of the physics-based and AI-modeling worlds to create a virtual model. Virtual modeling is a big opportunity.The rate of change and improvement in algorithms in large language models moves fast because machine learning can scrape the Internet for data to build huge training sets. In the semiconductor world, however, data sources are typically siloed within organizations and often not shared with vendors. This limits the rate at which the industry can take full advantage of existing data and create tangible economic benefit.By and large, there is a lot of wasted capacity in semiconductor manufacturing. The operational effectiveness of factory equipment is up to 90-95%. The reality is that most factories today process product wafers 40-60% of the time – maybe 70-75% of the time on a test floor. It is critical for the industry to start leveraging new types of AI models to increase the productivity of its manufacturing capacity.The industry needs to look at how companies can share data to take advantage of more sophisticated AI and create a new kind of operational digital twins. If the industry doesn't make a change; it will only be the largest facilities with the largest datasets able to take advantage, leaving one or two winners, with the others not being competitive.Smith: Is it possible for the industry to come up with a standard or some way of sharing information to build better models without giving away the underlying proprietary data? Kibarian: We can look at computer science with technology like homomorphic encryption. The relationships between parameters remain, but the underlying numbers or raw data is not visible after encryption. Pharma and the medical industry have ways to add noise to the data while preserving the information, as required by the Health Insurance Portability and Accountability Act (HIPAA).Our industry has a knee jerk reaction when it comes to looking at how to take full advantage of data and prefers to solve it as if information and data is more proprietary than medical data or financial data. And I don't think that’s true.Bob Smith: Is the open-source movement destined to bring change to the industry? Kibarian: PDF is a big believer in open source when it comes to OS-level virtualization and Kubernetes versus proprietary alternatives. We also use open-source database technology like Cassandra but are skeptical of the value of open-source solutions for end-market verticals. Having an underlying open and available IT layer has tremendous value, because it means a more rapid rate of innovation and greater ability to adjust security vulnerabilities and patches versus proprietary systems.Smith: PDF sits right between manufacturing and design. On the EDA side, more collaboration is going on between designers and manufacturing. How would you bring these two domains closer together? Kibarian: That's a good question. My first instinct is to look at the largest design organizations and manufacturers. They often invest heavily to figure out how to get jobs done right. This results in the concentration of the industry on a smaller number of players and leads to less innovation. However, in the world of chiplets and advanced packaging, there are more opportunities to become a chiplet supplier, because the whole system doesn’t need to be built by a single company. A supplier of chiplets could sell it into many systemsFrom a system view, connecting the pieces together through software, data sharing and analytics could drive more productivity gains that will offset some of the natural headwinds. This needs to be addressed in a way that changes the paradigm with software and systems used to bring manufacturing and design closer together.About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

Maheen Hamid is co-founder of electronic design automation company Breker Verification Systems and a member of both the ESD Alliance Governing Council and the SEMI North America Advisory Board. I spoke with Hamid about the EDA industry and her perspectives on the sector where electronics begins.

Niels Faché, Vice President and General Manager of the Electronic Design Automation business at Keysight and a member of the ESD Alliance’s Governing Council, has a diversified career that took him from an academic track to a technology startup to senior management positions.

ESD Alliance member company IC Manage enables global teams to efficiently collaborate during design and verification of systems and chips. IC Manage provides design data and IP management, data analytics, hybrid cloud bursting and high-performance computing software to systems and chip companies.

Cultivating trust and keeping his team agile and innovative as they engage with technology partners and customers is a core focus of John Lee, General Manager and Vice President of the Ansys Electronics, Semiconductors, and Optics Business Unit.

Belgium-based Sigasi, a member of the ESD Alliance, a SEMI Technology Community, is a digital chip design validation company that firmly believes in the shift-left methodology to get chip designs right the first time. Sigasi has developed an Integrated Design Environment (IDE) that does just that.

Aki Fujimura, CEO of D2S and a member of the ESD Alliance Governing Council, is an expert on curvilinear (aka curvy) chip design. He believes curvy chip designs will replace the traditional Manhattan routing methods, leading to smaller, faster and more power efficient devices.