semiconductor industry

Jennifer Braggin, director of technical training at Entegris, was honored with the inaugural SEMI Foundation Excellence in Achievement Award at SEMICON West 2021 in San Francisco in December for her contributions to advancing workforce development and DEI in the microelectronics industry.

29 new fabs will break ground globally between now and 2022. But who will staff them? With 34,000 current vacancies in the semiconductors industry worldwide, companies large and small are already competing for the same talent pool.

As part of bi-weekly meetings of the SEMI Environment, Health, Safety and Sustainability (EHSS) community to share information on the impacts of the pandemic, the EHSS COVID-19 Working Group recently revealed that companies are offering PTO to employees to get vaccinated.

Dr. Lanza, Managing Partner of Lanza techVentures and 2014 winner of the Phil Kaufman Award for Distinguished Contributions to Electronic System Design, addresses why he believes semiconductors in MedTech is about to become the next big thing.

Considering the history of computing and the low expectations for women that were once widespread in academia and the workplace, little wonder that women continue to face significant hurdles in the microelectronics industry. Today, women make up less than 25% of the computing workforce.

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at the technological forefront in incorporating ML techniques in its chip design products. I spoke with Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital Signoff Group, about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. Teng also offers advice on how engineering students can calibrate their education to prepare to work with this transformative technology and urges them to have fun in the process. Smith: How is ML changing the EDA industry? Teng: ML is changing EDA for the better in many ways. It’s more difficult than ever to design chips, and ML is helping by overcoming the complexity, size and technology interdependencies. At the same time, ML is helping our own engineers solve certain classes of EDA algorithm, tool, and flow/solution challenges so that we can deliver even better EDA tools to our user base. The benefits can include reducing runtime, increasing quality of results, and being better equipped to manage vast complexity and data. Also, and maybe even more significant, is the potential boost to user and team productivity, where engineers have more time to focus on high-value problems because they no longer need to spend time on managing overwhelming volumes of data and details that can be easily automated. Smith: What is the potential impact ML can have on semiconductor design? Teng: ML technology can be leveraged in several ways to improve EDA tool performance and engineering team productivity. For example, we initially applied ML to applications such as formal verification, simulation regressions, analog circuit design, and PCB design. We targeted ML toward specific algorithms that processed lots of data to sharpen and speed decision-making. Then we started to look at digital implementation flows that combine multiple steps with multiple decisions in a recipe, especially for chip implementation where the more efficient use of engineering knowledge can make a substantial difference in the chip’s resulting power, performance and area (PPA). These flows present more challenges and require different ML and optimization techniques since the data points are expensive to create and the volume of data is huge. But flow optimization offers the largest rewards for companies investing in data collection and analysis to improve their operations and product quality. By using ML to improve the implementation flow, our users are seeing up to 20% better PPA and 10x improved productivity in developing data center CPUs and AI engines, automotive sensor processing SoCs, and mobile devices. Smith: What is the cloud’s role in the evolution of ML in EDA? Teng: More ML usage means there will be an inevitable surge in compute demand resources, and engineers need the ability to scale in parallel. The cloud provides engineers with the best opportunity to scale computing resources without facing procurement limitations. The cloud also allows engineers to use task-specific compute and ML accelerators and capitalize on distributed computing innovations that leverage the cloud for greater design flexibility and availability. Smith: You have written that you see Moore’s Law accelerating. How does ML fit into this? Teng: We see the rapid adoption of new process technologies as the biggest trend surrounding Moore’s Law right now. ML technology in EDA will help speed tool certification processes, process design kit (PDK) development and other deliverables aimed at creating and improving customer support through all stages of the process lifecycle. This is a virtuous circle, and it’s expanding beyond hardware design and optimization to also include software. Today’s ML functionality works on the abstraction of register transfer level (RTL), optimizing the implementation and verification flows. ML will soon enable use of a higher abstraction of describing the target systems, exploring architectural options and optimizing across hardware and software partitioning. Smith: What advice would you give engineering students who are studying ML with the goal of becoming an electrical engineer? Teng: With the rapid pace of technology development, things are changing constantly. I’d absolutely encourage students to look at ML because ML isn’t going away — its growth is only going to accelerate from here. I’d also suggest that students look more broadly at computational mathematics because that’s foundational for ML. There are many, many opportunities to apply ML to real-world applications that will make a significant impact when it comes to optimizing computational software. Most important, students should explore and have fun while doing it. About Chin-Chi Teng Chin-Chi Teng has served as Senior Vice President and General Manager of the Digital and Signoff Group (DSG) since 2018. Prior to this role, Teng held senior leadership positions in research and development in digital implementation. Teng joined Cadence in 2002 via the acquisition of Silicon Perspective Corporation and subsequently led various research and development groups. He brought deep technical knowledge and more than 20 years of industry and academic experience to his role as leader of the IC Digital group. Teng holds a BS in electrical engineering from the National Taiwan University and an MS and Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He holds seven patents and has written many EDA papers, several deep learning papers, and the book Electrothermal Analysis of VLSI Systems. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger design. While the new market segment created excitement and new opportunities, it also was untested and created uncertainty. Many fledgling companies failed. It’s a different story today. Arm, as well as Cadence and Synopsys, are silicon IP suppliers and the segment’s yearly revenue tops $4 billion, a long way from those early garage startup days. ESD Alliance member CAST, a silicon IP provider since 1993, participated in the remarkable growth and impact on the semiconductor industry. Nikos Zervas, CAST’s CEO, and I discuss those early days of the IP business and what’s ahead. Smith: What were the early days of silicon IP like? Zervas: In those early Wild West days of IP, vendors and customers both wanted to benefit from IP, but nothing was standardized, and people just tried things to see if they worked. The perceived barrier to entry was low: hundreds of IP companies sprang up thinking they only needed RTL coding skills and tools, an FPGA to prototype, and a few thousand dollars to invest. IP deliverables, quality standards, and business practices varied from vendor to vendor and over time. Risk was high, and there are many horror stories of re-spins or market failures due to faulty IP cores. Smith: How has the silicon IP market changed from its early days? Zervas: Firms delivering high-quality IP and providing outstanding customer support survived. Others disappeared. Eventually the industry centered around a reasonably common sense of IP requirements and quality and a consistent set of business practices. IP product complexity has driven upwards as SoCs have grown. The largest ASICs used to approach a few million gates; today they’re hundreds of millions, and the granularity of IP has evolved from small functions to pre-integrated subsystems. Early on, a designer doing image processing might license individual functions like a Finite Impulse Response (FIR) filter or a Discrete Cosine Transfer (DCT) block. Today, instead they would license a complete JPEG compression core containing those functions and more, or even a complete black box subsystem streaming processed, stabilized, compressed video over Ethernet. IP selection criteria have also changed. Early IP was handcrafted to eliminate every extra gate, as being a few thousand gates smaller was a killer advantage in the era of 180nm ASIC processes. Today, at 7nm or 5nm process, tens of thousands gate differences are just noise, and it’s usually the reliability, functionality, and performance of an IP core that matter most. Smith: When did the silicon IP market start to take off? What was the driving force? Zervas: By the early to mid 2000s, uncertainty about what IP was and how best to use it – and the early wave of less-than-great providers – were being replaced by increasing acceptance and emerging best practices. The introduction of smartphones, the wild growth of Internet of Things applications, growing automotive system sophistication, and other advances fueled the explosion of the IP market in the late 2000s. In fact, according to the ESD Alliance Electronic Design Market Data Report, revenue from IP licensing today has surpassed the license revenue from front-end EDA tools. This would have been unimaginable in the late 1990s. Smith: How has silicon IP changed chip design? Zervas: Designers today must develop massive, complex systems with an even tighter time to market. Only the higher level of design abstraction and the distributed expertise that silicon IP provides make this possible. But IP also increases the challenge of differentiation: With the same IP available to everyone, how do you design a product that stands out in its market? The answer to differentiation today lies mainly in clever SoC architecture. Delivering better features with superior performance, lower power consumption, or other winning characteristics now depends not so much on perfecting each separate IP block but rather from selecting the best IP for the system’s requirements, integrating those IP cores for clean communication and efficient resource sharing, and other smart system-level decisions. It’s similar to modern building design: Every firm has access to the same materials and tools – concrete, glass, etc. – but only a few produce exceptional buildings. Smith: It seems that are several different business models for IP licensing, such as up-front license fees, subscriptions, royalties, or a combination of these. Do you think the IP market will gradually align around one basic model, or will it continue as is with a variety? Zervas: Different models serve different needs. For example, commodity IP like a SPI interface can’t demand royalties, but unique, leading-edge IP – like a 112Gbps SERDES – still can. I believe the market will continue with different business models, though the number of different models may shrink and their terms begin to align. About Nikos Zervas Dr. Nikos Zervas is the chief executive officer of CAST, Inc. He co-founded image and video compression IP developer Alma Technologies in 2001, and led the bootstrapped firm as chairman and CEO for nine years before joining CAST. He was a founding member of the Hellenic Semiconductor Industry Association and served on its board for several years with responsibility for strategic planning. He is a senior IEEE member and member of the Technical Chambers of Greece, had contributed to the GSIA's IP Working Group, and has published multiple technical papers on data compression design and related topics. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Demand for hi-tech manufactured goods is at an all-time high and is expected to grow significantly in our new digital age, COVID-19 economy. This is especially true for semiconductor chips. Chip manufacturers have been working to meet this demand by building new factories and by optimizing processes and equipment in existing fabs. While there is much media coverage about new factories planned by leading-edge chipmakers and government investments in the semiconductor sector, greenfield fabs entail significant capital expenditures and are sometimes fraught with complex political concerns. As a result, they can take several years to complete and reach their planned production capacity. Instead, the semiconductor industry needs to optimize existing factories in order to increase productivity and yield and meet growing demand by implementing smart manufacturing solutions. Smart manufacturing solutions will inherently reduce costs with more efficient and automated processes, and those savings can be reinvested for the next wave of solutions. Chip Industry on the Bleeding Edge Semiconductor manufacturers have always been focused on bleeding-edge technology to outflank strong competition and build the best products – faster and cheaper. Today, pioneering organizations are using data to optimize manufacturing processes and equipment, a practice known as Smart Manufacturing. While there are many definitions of Smart Manufacturing, the essence is maximizing the utility of big data generated in these factories by leveraging three pillars: Sensing, Connecting, and Predicting. It is not just the digitization in manufacturing, but it is also about turning the data into actions that generate value – an effort the SEMI Smart Manufacturing Committee is driving based on the three pillars. Optimizing return on investment is the ultimate goal. SEMI Smart Manufacturing Initiative activity is based on three pillars that support the goal of increasing ROI. Making the Right Decision, Faster Smart manufacturing practices enable organizations to make the right decisions and take action faster based on insights generated from real-time and historical data. This requires data management technologies and applications that can process, analyze, and act on information instantly. It has become ever more difficult to process and discern the relevant data or signal from the vast volume of data, perform analytics or develop new ML or AI analytic tools, and then make the critical decisions to solve problems as close to real-time as possible. Who’s Responsible – IT or OT? In the past IT (Information Technology) and OT (Operations Technology) were separate entities within organizations, with IT focused on storing large amounts of data for enterprise systems and OT concentrated on using data to perform specific functions. Smart Manufacturing often demands combining IT and OT, difficult in rigid organizations that operate the two organizations independently and lack the infrastructure to implement comprehensive solutions. Success requires executive leadership sponsorship, motivated technical personnel and, most importantly, a clear deliverable on the value in implementing Smart Manufacturing. Many organizations have introduced top-level leadership positions such as a Chief Information Officer or Chief Data and Analytics Officer to address this convergence and many of these leaders are embracing Smart Manufacturing practices. The SEMI Smart Manufacturing community includes many of these leaders and therefore has highlighted the importance in the return on investment for Smart Manufacturing solutions. Read more about IT and OT convergence and note that Smart Manufacturing is synonymous with Industry 4.0. The SEMI Smart Manufacturing Initiative covers the entire supply chain. Get Smart in Smart Manufacturing While new technologies and applications are being created to deal with mountains of data, it is the underlying methodologies and practices that are key to a successful Smart Manufacturing deployment. SEMI, the trade association representing the electronics manufacturing and design supply chain, is in a perfect position to evangelize Smart Manufacturing experiences and best practices for the entire manufacturing community. The more than 30 member companies participating in the SEMI Smart Manufacturing Initiative bring more than 500 years of collective experience and knowledge to the topic. Many segments of the supply chain participate in the SEMI Smart Manufacturing Initiative including packaging, assembly, SMT and PCB assembly, test, software, data management, sensor and material suppliers. Learn How to Manufacture Smarter SEMI SMART Manufacturing is hosting two great conferences in the coming months – the Global Smart Manufacturing Conference (GSMC) and the SEMICON West Smart Manufacturing Pavilion. As a leader of the organizing committee and chair for the SEMICON West Smart Manufacturing Pavilion, I encourage people who want to learn how to implement Smart Manufacturing or expand their knowledge of Smart Manufacturing to attend these events. The GSMC will feature keynotes highlighting the value of Smart Manufacturing, offer tutorials on the three pillars, and introduce several case studies for each of the pillars. Thirty-two organizations – ranging from global cloud providers, semiconductor factory operators, leading equipment vendors and software application solution companies – will present. See the full agenda here. The SEMICON West Smart Manufacturing Pavilion will compliment GSMC by showcasing a number of use cases that highlight the value of Smart Manufacturing. Panel discussions will deep dive into the challenges of implementing these best practices and the direction smart manufacturing is taking in the coming years. Our goal for these events is for you to take this knowledge back to your companies, implement and improve on the detailed solutions highlighted at the conferences, and return next year to share your success stories with the community. See you soon, in person or virtually! About the Author Bill Pierson is VP of Semiconductors and Manufacturing at KX, leading the growth of streaming data analytics in this vertical. Bill is also a chair for the SEMICON West Smart Manufacturing Conference and an active team member of the SEMI Americas Chapter. He has extensive experience in the semiconductor industry including previous experiences at Samsung, ASML and KLA. Bill specializes in applications, analytics, and control. He lives in Austin, Texas, and when not at work can be found on the rock-climbing cliffs or at his son’s soccer matches.

As we round the corner on 2021, the microelectronics industry continues to face a severe talent crisis. With more than 34,000 jobs remaining unfilled at SEMI member companies in the United States alone, everyone is competing for the same talent pool. While the semiconductor shortage has received extensive media coverage, a critical talent shortage deserves equal attention. One way to address the talent shortage is to hold the line. Meaning, in addition to recruiting more diverse talent into the chip industry, we must retain the quality workforce we have. I believe that a key component of a diversity, equity and inclusion program must be retention. At Edwards, we feel so strongly about this that we have made retention a key part of our Diversity, Equity and Inclusion program – even changing the acronym to DEIR (pronounced DEER; diversity, equity, inclusion and retention) for emphasis. There are three overarching approaches we can take to promoting diversity-focused retention:Investment in on-boarding practices that allow time to hire appropriately and ensure a diverse pool of qualified candidatesEmbedded programming and policies that are learning and development (L D) based including career planning, succession planning, unconscious bias training, employee resource groups (ERG) and mentoringCorporate culture that respects employees through a healthy work life balance and promotes the well-being of society and the planetThis is a very important conversation. I asked Lubab Sheet-Davis, vice president of Strategy Innovation in the Office of the CTO at Lam Research, and Emerald Greig, executive vice president Americas at SurplusGLOBAL USA, to share their considerable experience and insight related to retention and DEI. Following is an excerpt from our conversation, which has been edited for clarity and brevity.Balaguer: In the context of DEI, why is employee retention so important?Sheet-Davis: In my view, there is a strong correlation between inclusion and retention. If people feel that their voices and perspectives are valued, they are more likely not only to stay, but also to perform at a higher level. Driving both inclusion and retention is having a seat at the table, having your voice heard, respectful treatment and fair opportunity. Retention is a core component of our inclusion and diversity strategy, which involves increasing representation by building a pipeline of diverse candidates, recruiting and retaining, fostering an inclusive culture (which supports retention) and open communication to share our progress.Balaguer: What role does data play in the drive to increase retention?Greig: Ours is a data-driven industry and I am surprised that we have not let the statistics drive us into action sooner. Clearly, diversity, equity, inclusion and retention all affect the bottom line. Millennials and Gen Zs already leave faster than any other generational group. The turnover rate in the tech industry averages around 13% with stays around 2-3 years.The cost to hire, train and integrate someone into a company is far more expensive than having a DEIR program in place to keep them. The Society for Human Resource Management (SHRM) reported that, on average, it costs a company 6 to 9 months of an employee's salary to replace them (which includes the costs of hiring, onboarding and training, L D and time to fill the role). For an employee making $60,000 per year, that comes out to $30,000 to $45,000 in recruiting and training costs.Sheet-Davis: Yes, which gives us all the more reason to move quickly! Given how central DEIR is to innovation, and that the challenges and opportunities facing our industry are bigger now than ever before, I believe we should be addressing DEIR with the same vigor that we address Moore’s Law.I worry if we keep saying DEIR will take time, it will take time. Granted many DEIR issues are cultural and culture is hard to change. However, this industry has demonstrated the capability to drive breakthroughs and to do so quickly. Let’s focus on DEIR with urgency while also ensuring the progress is sustainable.Balaguer: There is no doubt we need to move with a sense of urgency. I think a good way to keep the pedal to the metal is to create a DEIR roadmap that tracks our progress on multiple programs and helps us be accountable and stay focused. Meaningful retention strategies begin with solid diversity-focused hiring strategies.Balaguer: How does corporate culture inform retention?Greig: Let’s not forget: Employees, especially millennials, are looking for a corporate culture that demonstrates social responsibility as well as leadership and career development. In a recent study, 65% of employees said positive corporate culture has encouraged them to stay with their company. In fact, companies with strong cultures have seen a four-fold increase in revenue growth.We have raised a generation that strongly believes in being accepting of others and embraces equity and inclusion in their daily lives. They expect their employer to have this as part of their DNA. They believe in science, climate change, recycling, conservation, and similar sustainability issues and they want to know that they are making or doing something that makes the world a better place. If tech companies cannot convince millennials and Gen Z's that the companies are socially responsible and are doing all they can to embrace DEIR as part of their company culture, then the millennials will go elsewhere. Balaguer: How can employee resource groups be a building block for retention?Sheet-Davis: We support employee resource groups that are voluntary, employee-led and coalesce around demographic factors such as gender, ethnicity, sexual orientation or generation. Each has an executive sponsor, budget, plans and leadership structure. ERGs support inclusion by creating a sense of belonging, building comradery, and providing a safe space to raise awareness and help educate the rest of the company through a number of activities such as community service, holiday celebrations, guest speakers, networking, training courses and more. I serve as the executive sponsor of our Women@Fremont group, which is focused on accelerating the advancement of women in their early to mid-career at Lam’s headquarters. I know ERG members genuinely value the company’s support.Balaguer: What can we do during the hiring process to lay a strong foundation for employee retention?Greig: I believe that the work we do at the front end in terms of hiring practices are one of the main reasons we have a low turnover rate at SurplusGLOBAL. We have a policy to have three interviews for each candidate. Not three different people, but bring them in three times. Additionally, we have a 90-day trial and review period to make sure there is a good fit for both parties. Investing time up front ensures the right hire and the small size of our company allows us to know our employees. We can be nimble and quickly respond to employee needs as they arise.Balaguer: In what ways do you think mentoring can help improve retention?Sheet-Davis: Another aspect of building a more inclusive culture, and hence promoting retention, is through mentoring programs. Mentorship supports an employee’s development, growth and career planning. It’s a great way to get to know people, understand their ambitions and support their development. Hopefully, it results in sponsorship because that is what helps drive career advancement. Ultimately, I want to advocate for those that I mentor.Balaguer: At Edwards, we are refreshing mentoring as part of our DEIR program. I see mentoring as a program that can support employee retention in multiple ways including career planning, professional development, succession planning and promoting inclusivity. Encouraging and empowering personal development is key in growing a productive workforce and mentoring does all these things. Often overlooked is the fact that mentoring is a benefit to both the mentor and the mentee. I have personally mentored several young professionals at Edwards, and I can attest that I have learned as much from them as they have from me. Mentoring is definitely a two-way street.Balaguer: What’s your message to our readers about retention as an element of diversity, equity and inclusion?Greig: I am excited to see DEIR and especially, retention, gaining traction. The semiconductor industry has always tended to have a cyclical rhythm to it. A generation of potential employees have grown up witnessing the fallout from periodic down cycles and the inevitable reductions in workforce. I think there is an element of rebranding we need to do in this area to support our retention efforts. Sheet-Davis: If we only focus on recruiting and not retention, we tread water. Consistent with any other successful business strategy, a holistic integrated approach to DEIR that is prioritized, resourced and sustained over time is key. Balaguer: We all agree that retention is a key component in the war for talent. While this conversation has been more wide-ranging than we can share with our readers, the prime takeaways have focused on these elements: Follow the data. Execute with a sense of urgency. Hire right. Work hard on inclusionary programming such as ERGs, mentoring and sponsorship. Build a genuine corporate social responsibility program. Retention will result.Many thanks to Lubab Sheet-Davis and Emerald Greig. As always, comments, questions and suggestions are welcome. We can be reached at [email protected], [email protected] and [email protected]. I invite our readers to join the conversation, as well as review the recently released SEMI Foundation DEI Roadmap and Toolkit.Scott Balaguer is Vice President and General Manager, Semiconductor Division at Edwards Vacuum LLC and Chairman of the SEMI North America Advisory Board.