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Materials

Driven by the recovery of the overall semiconductor market and rising demand for advanced materials for high-performance computing (HPC) and high-bandwidth memory (HBM) manufacturing, global semiconductor materials revenue rose 3.8% year-over-year in 2024. At the heart of this momentum, Strategic Materials Conference (SMC) Korea 2025 brought together approximately 300 industry leaders on May 14 to discuss bold innovation roadmaps and the evolving challenges of the new AI-driven era.Celebrating its 10th edition, SMC Korea served as a convergence point for leaders across the semiconductor ecosystem—including materials suppliers, equipment manufacturers, chipmakers, and academia.“This year’s SMC Korea has recorded the highest level of Q A engagement. A full hour was dedicated solely to an audience-driven panel discussion, where questions ranged from materials technology and business to semiconductor process roadmaps and market outlook. The depth and interactivity of the dialogue reflected the standards of leading technical conferences. Some attendees even noted that it surpassed any academic or industry symposium currently held in Korea,” said Oh Kim, Co-chair of the EMG Korea Chapter and representative of Air Liquide Solutions Korea.Exploring Next-Gen Technologies: 3D DRAM and CFETThe first session focused on next-generation semiconductor technologies, highlighting the future of materials and processes for 3D DRAM and Complementary FET (CFET) devices.Dr. SukKoo Hong, Head of the Material Development team at Samsung Electronics, kicked off the session by outlining a roadmap for materials innovation in 3D DRAM and CFET. Dr. Hong emphasized key technical challenges in the development of 3D DRAM and CFET, highlighting the need for continued innovation in process integration and material engineering. Building on this, Dr. Hong stressed the increasing complexity of material processes and the critical need for tight cross-industry collaboration.Dr. Inhee Lee, Director of imec’s Active Memory Program, highlighted the diminishing improvements in DRAM scaling and emphasized the urgent need for new high-k materials to enable higher density in next-generation 3D DRAM and 4F² DRAM architectures. Dr. Lee emphasized the need for further validation on performance shifts and data retention time resulting from changes in channel materials and architectures.Professor Changhwan Choi of Hanyang University presented key material and process trends for CFET devices, focusing on monolithic and sequential integration as well as Backside Power Delivery Network BSPDN) technologies.The session also featured a presentation by Linghzhi Zhang, Director of Product Management at Air Liquide Advanced Materials focused on “Si, Ge, B Hydrides for Next Generation Semiconductor Devices – Challenges and Perspectives.”The Future of Semiconductor Materials: Market Trends and Innovation StrategiesThe second session highlighted semiconductor materials from multiple perspectives, including market outlooks, advanced technology solutions, and strategic responses to industry challenges.Dr. Prayudi Lianto, Technology Manager at Applied Materials, discussed the technical barriers currently facing HBM, particularly the stacking height limitations. Dr. Lianto highlighted the importance of advanced packaging technologies such as through-silicon via (TSV) and hybrid bonding, and emphasized the critical role of material innovations. Key challenges include void formation during TSV gapfill and developing robust bonding strength and interfacial metals for low-temperature hybrid bonding.Andy Tuan of Linx Consulting provided a market outlook centered on macroeconomic shifts and evolving supply chain structures. Tuan noted that while the semiconductor industry is undergoing a short-term correction, the materials market continues to grow steadily—driven by 300mm logic, DRAM, and 3D NAND. Tuan projected that demand for process materials such as lithography, deposition, and CMP will see a notable recovery post-2025.Dr. Deoksin Kil, Senior Fellow at SK hynix, underscored the growing significance of advanced process materials—including high-performance photoresists, functional chemicals, and CMP slurries—as enablers of semiconductor scaling and 3D evolution. Dr. Kil also stressed the need to maintain consistent quality and supply chain resilience, while pursuing sustainability through low-GWP gases and PFAS-free materials.The session also featured the following presentations:Yohan Ahn, Senior Director, Entegris: “Technological Trends and Necessity of Material Contamination and Filtration for Wafer Defectivity Control in HBM Manufacturing”Dr. Mikko Utriainen, Chipmetrics: “Advancing ALD Tool Qualification Using Ultra-High-Aspect-Ratio Test Structures”SEMI Korea extends its gratitude to all SMC Korea 2025 sponsors for making this insightful conference possible. Dongwoo Fine-chemJSR Electronic Materials KoreaHuntsman Performance ProductsUP ChemicalDuPont Electronics IndustrialDongjin SemichemSK trichemTEMCEntegrisAir Liquide Solutions KoreaJaegwan Shim is Senior Specialist, Marketing at SEMI.
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The semiconductor industry continues to push the envelope to meet demands of key applications such as advanced computing, consumer electronics, and defense, as well as environmental sustainability. There remain several critical challenges that our industry is working diligently to address, but how can these issues be tackled more effectively and at a pace that can keep up with this ever-evolving landscape?SEMI sat down with Supika Mashiro, Advisor at Tokyo Electron, where she shares her perspective on the importance of strengthening industry collaboration and what SEMI is doing through its first-ever SEMI Global Standards Summit – “Innovating Tomorrow: Standards for Future Factories” – of which she chairs the Planning Committee responsible for organizing this Summit.Trio: What is the SEMI Global Standards Summit and why is this event timely?Mashiro-san: Topics such as advanced packaging, cybersecurity, as well as supply chain and materials innovation (and their impact to the environment) are considered strategic areas requiring more industry collaboration. Many of these areas also greatly benefit from standards, and the next generation specifications and guidelines will need to be engineered to meet the technical challenges we face today and in the future. The magnitude of these standardization efforts will require engagement from all stakeholders in the design-to-manufacturing value chain as well as multiple Standards Developing Organizations (SDOs) coordinating and collaborating with each other.This is the driving force behind the Summit, and the need to bring together industry stakeholders to identify standards-critical areas and align on developing an industry standardization strategy for the next 3- and 7-year time horizons. We are excited to host this inaugural event on December 12, 2024, in conjunction with SEMICON Japan 2024. Trio: What is the focus of the Summit?Mashiro-san: The Global Standards Summit will cover three main themes: Smart Manufacturing for Future Factories, Packaging Architectures Materials, Environmental Sustainability.Factories are increasing their use of digital twins, predictive maintenance, and AI/ML to improve productivity and yield across the entire manufacturing environment. To take full advantage of these approaches, factories must reduce cybersecurity risks and secure the transfer of “smart” data across the entire supply chain while protecting IP. There is a need for standards to address these risk areas, as well as help diverse advanced analytics systems interoperate to assist personnel in increasing factory productivity. In the Smart Manufacturing for Future Factories session, we will be focusing on autonomous fabs, cybersecurity, and flow-oriented manufacturing.Similarly, packaging technologies have been progressing since the early stages of semiconductor device development more than 70 years ago. More recently, where packaging occurs in the semiconductor process has evolved, and some of the packaging processes are now done as an extension of front-end manufacturing. Moving forward, packaging architecture and materials are becoming increasingly important, driven by the adoption of heterogenous integration to address demands for more complex functionality and reduced power consumption as well as enabling chiplet integration. In the Packaging Architecture Materials session, we will discuss what kind of standardization our industry requires for copper-copper (Cu-Cu) direct interconnection, hybrid bonding, and panel-level packaging. We will also explore glass substrates as well as standards needed to enable semiconductor assembly and test automation.Our third session recognizes that the semiconductor industry is heading into an era of NetZero, in which quantification of environmental performance can have meaningful financial impact. The methods of measuring and accounting the environmental impact such as carbon emissions and the presence of substances of concern in manufacturing and products are not uniformly consistent across the industry. In order for the semiconductor industry to better navigate and make a positive impact in this arena, a consistent set of standards will be crucial. In the Environmental Sustainability session, thought leaders will present on communicating substance of concern (SOC), reporting of process emissions from factories, as well as lifecycle assessment of materials and substances used in semiconductor manufacturing, including equipment.Last but not the least, we will feature a panel session where we will explore all of these topics in a discussion with our panelists.Trio: Who should attend the Summit and why?Mashiro-san: The Summit is intended for leaders who are interested in these standardization topics to come and engage. Attendees will hear and learn about the issues critical to the future advancements of semiconductor manufacturing, what’s happening to address them, as well as new standards development. Attendee engagement is critical as we want our participants to influence and be able to contribute to the direction of standards development by providing valuable insights to help optimize future factories. To facilitate industry collaboration, we have organized networking events with other stakeholders from suppliers and solutions providers to end customers. The Summit is just one of many compelling reasons for industry stakeholders and thought leaders to come to SEMICON Japan. There are several sessions on many related topics that we are covering in the Global Standards Summit. Ultimately, at the conclusion of the Summit, we expect to have identified lists of critical standards areas, and we would like for those leaders to be able to assign and dedicate resources to these standardization efforts.For more information about the inaugural SEMI Global Standards Summit, please visit the SEMICON Japan 2024 site and register today!Supika Mashiro works as an Advisor for Strategic Planning of Industry Initiative Group at Tokyo Electron Limited.She has been involved in Factory Integration (FI) IFT of IRDS since its inauguration in 2016 and a co-chair since 2017. Her area of interest and involvement encompasses “smart” technology applications in manufacturing equipment, its co-optimization with Fab operation as well as ESH/S (Environment, Safety, and Health/ Sustainability) road-mapping and related industry standard development. For the latter, she has taken a couple of leadership roles in SEMI Standards Program as well as IEC TC/44.Paul Trio is Director of the SEMI Standards program.
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New metrology and inspection technologies and new analysis approaches made possible by improving compute technology offer solutions to finding the increasingly subtle variations in materials and subsystems that meet specifications but still cause defects on the wafer. More collaboration across the supply chain is helping too. SEMICON West programs on materials and subsystems will address these issues. New metrology approaches needed to deal with process margin challenges As device process margins shrink and subtler materials variations cause unwanted deviations, the need for better monitoring of both surface and sub-surface material variations is driving a trend towards “metro-spection” – the convergence of metrology and inspection. “Device process margins have eroded to the point that traditional metrology strategies and techniques are no longer viable for controlling yield and parametric performance,” says Nanometrics Vice President Robert Fiordalice, who will speak in the materials program at SEMICON West. “Limited sampling capability, low throughput, insufficient sensitivity or the destructive nature of the techniques can often become problems. What’s more, deviations in material characteristics are not always determined by the initial quality of the material, but often arise from variations during the integration of the materials.” One new type of inline tool or line monitoring technology is Fourier Transform Infrared (FTIR) spectroscopy, traditionally used in quality control or tool characterization. Better sensitivity and higher throughput now enable rapid analysis and feedback for on-the-fly detection of subtle deviations in film properties that may compromise device performance or yield. More advanced analytics will help extract new information from old metrologyMore expensive metrology may not be required to identify subtle variations in in-spec materials that cause wafer defects. Today’s advanced compute capabilities now enable more sophisticated analysis of existing data and the identification of small but significant variations in raw materials and finished goods. The figure of merit (FoM) values presented in certificate of analysis (CoA) reports miss subtle variations in raw material properties. Of particular note is the reduction of molecular weight distributions to a mean, and standard deviation, whereas variations in the tails are associated with pattern defects. Advanced compute capabilities now allow the industry to step beyond the FoM in favor of more holistic measures, enabling predictive analysis of resist chemical variations associated with specific pattern defects. Source: JSR Micro“We often don’t need to find a new measure, but just a new way of looking at what we measure now,” says Jim Mulready, vice president of global quality assurance at JSR Micro. Mulready will speak in the SEMICON West program on materials defectivity issues. “The certificate of analysis reduces multiple measurements to a single figure of merit. But if we ignore all that raw data, we miss a chance to learn. One of our sayings in quality is ‘Customers don’t feel the average, they feel the variation.’ In many electronic materials, the quality of the raw material can have a big impact on the final performance, but the types of analysis needed to look at the tails of the distribution of these measures (such as molecular weight) in detail used to be really hard to do. Now it’s becoming increasingly straightforward and affordable.” Mulready says tools now available in the data processing sector enable the identification of subtle variations in materials that can cause defects on the wafer. These tools use methods like detailed subtractions of chromatography curves of polymer raw materials or analysis of tails of distributions of molecular weights. “Our job now is to drive these kinds of more sophisticated data analysis back into our chemical supply chain as well,” says Mulready. “We must work more closely with our suppliers to integrate their raw materials into our products. The reason the JSRs of the world exist is as a safety valve to reduce the variation from the chemical industry before it gets to the fab.”Continued collaboration with equipment suppliers required While the industry has been talking about the need for tighter collaboration between materials suppliers and equipment manufacturers for years, it still doesn’t always happen. “The material supplier and the equipment maker are tied together like kids in a three-legged race when we deliver an integrated system for consistent on-wafer performance,” says Cristina Chu, TEL/NEXX director of strategic business development, another speaker in the materials program. “When we introduce changes to the tool hardware, we need to make sure it doesn’t upset the system. Similarly, we need the material supplier to send a bottle over when a new chemistry formulation is under development. If a new chemistry runs into problems in the field, it will take much more time for both of us to fix it at the customer site. The toolmaker can provide a slightly different perspective on applications, while being more objective than a customer on how the formulation performs compared to earlier versions.”Regular and ongoing collaboration between chemistry suppliers and toolmakers enables the highest quality system solution to reach the customer. Chu notes that her team tries to maintain consistent collaborations with material suppliers across changes in organizations as the business environment changes. “For consistent on-wafer capabilities, we need a consistent collaboration process with chemistry suppliers. We need to meet with materials providers at a regular cadence throughout their development process. We need to check back with them as we scale up results from the coupon to the wafer level and to work out the kinks in the integrated solution together. The quality and consistency of our combined performance at the customer depends on ensuring the quality and consistency of our development and evaluation process as well.”Fabs and subsystems suppliers look to pilot data sharing program to improve process margins With ever tighter process margins, subtle variations in parameters that don’t appear in the specifications are also compromising results on the wafer, and neither the fab nor the supplier alone has the full information needed to improve performance. To help, a SEMI standards group is developing a protocol for a pilot program to standardize and automate some data sharing.The fab knows that performance is best with a particular parameter value, and knows when performance fluctuates, but often faces a black box problem with no way of knowing what exactly is wrong. In the rush to get the tool back up, the fab engineers may not get around to emailing the supplier about the issue for some time. The subsystems supplier, on the other hand, may know the cause of the variation, but likely has no way of knowing the critical parameters or ideal target values for the fab’s process. “In order for engineers to have constructive conversations about how to improve performance, we all need to exchange more information,” says Eric Bruce, Samsung Austin diffusion engineer, and co-chair of the SEMI Standards initiative addressing the issue, who will speak in the subsystems program at SEMICON West. A potential solution could be to create a standard and automated process to share particular data, agreed to in the purchasing contract, whereby the subsystems supplier shares more information about their parameters with the fab, and the fab in return gives feedback on what parameters work best to drive improved performance. The best place to start will likely be on parts that do not contain core yield-related IP, but where usage and lifetime information is useful.“We’re looking for people to participate in a pilot program to work together with suppliers to try sharing some information to improve performance,” says Bruce. “There’s a lot of this sharing in the backroom anyway, but this could make it fast and automated, and make everyone’s engineering job a lot easier.”Paula Doe, SEMI
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