Moore's Law

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at the technological forefront in incorporating ML techniques in its chip design products. I spoke with Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital Signoff Group, about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. Teng also offers advice on how engineering students can calibrate their education to prepare to work with this transformative technology and urges them to have fun in the process. Smith: How is ML changing the EDA industry? Teng: ML is changing EDA for the better in many ways. It’s more difficult than ever to design chips, and ML is helping by overcoming the complexity, size and technology interdependencies. At the same time, ML is helping our own engineers solve certain classes of EDA algorithm, tool, and flow/solution challenges so that we can deliver even better EDA tools to our user base. The benefits can include reducing runtime, increasing quality of results, and being better equipped to manage vast complexity and data. Also, and maybe even more significant, is the potential boost to user and team productivity, where engineers have more time to focus on high-value problems because they no longer need to spend time on managing overwhelming volumes of data and details that can be easily automated. Smith: What is the potential impact ML can have on semiconductor design? Teng: ML technology can be leveraged in several ways to improve EDA tool performance and engineering team productivity. For example, we initially applied ML to applications such as formal verification, simulation regressions, analog circuit design, and PCB design. We targeted ML toward specific algorithms that processed lots of data to sharpen and speed decision-making. Then we started to look at digital implementation flows that combine multiple steps with multiple decisions in a recipe, especially for chip implementation where the more efficient use of engineering knowledge can make a substantial difference in the chip’s resulting power, performance and area (PPA). These flows present more challenges and require different ML and optimization techniques since the data points are expensive to create and the volume of data is huge. But flow optimization offers the largest rewards for companies investing in data collection and analysis to improve their operations and product quality. By using ML to improve the implementation flow, our users are seeing up to 20% better PPA and 10x improved productivity in developing data center CPUs and AI engines, automotive sensor processing SoCs, and mobile devices. Smith: What is the cloud’s role in the evolution of ML in EDA? Teng: More ML usage means there will be an inevitable surge in compute demand resources, and engineers need the ability to scale in parallel. The cloud provides engineers with the best opportunity to scale computing resources without facing procurement limitations. The cloud also allows engineers to use task-specific compute and ML accelerators and capitalize on distributed computing innovations that leverage the cloud for greater design flexibility and availability. Smith: You have written that you see Moore’s Law accelerating. How does ML fit into this? Teng: We see the rapid adoption of new process technologies as the biggest trend surrounding Moore’s Law right now. ML technology in EDA will help speed tool certification processes, process design kit (PDK) development and other deliverables aimed at creating and improving customer support through all stages of the process lifecycle. This is a virtuous circle, and it’s expanding beyond hardware design and optimization to also include software. Today’s ML functionality works on the abstraction of register transfer level (RTL), optimizing the implementation and verification flows. ML will soon enable use of a higher abstraction of describing the target systems, exploring architectural options and optimizing across hardware and software partitioning. Smith: What advice would you give engineering students who are studying ML with the goal of becoming an electrical engineer? Teng: With the rapid pace of technology development, things are changing constantly. I’d absolutely encourage students to look at ML because ML isn’t going away — its growth is only going to accelerate from here. I’d also suggest that students look more broadly at computational mathematics because that’s foundational for ML. There are many, many opportunities to apply ML to real-world applications that will make a significant impact when it comes to optimizing computational software. Most important, students should explore and have fun while doing it. About Chin-Chi Teng Chin-Chi Teng has served as Senior Vice President and General Manager of the Digital and Signoff Group (DSG) since 2018. Prior to this role, Teng held senior leadership positions in research and development in digital implementation. Teng joined Cadence in 2002 via the acquisition of Silicon Perspective Corporation and subsequently led various research and development groups. He brought deep technical knowledge and more than 20 years of industry and academic experience to his role as leader of the IC Digital group. Teng holds a BS in electrical engineering from the National Taiwan University and an MS and Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He holds seven patents and has written many EDA papers, several deep learning papers, and the book Electrothermal Analysis of VLSI Systems. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.

As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Higher on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries are driving demand for advanced packaging technologies that address these issues but introduce challenges of their own such as efficient power delivery to all the different domains in a heterogeneous system. SEMI spoke with Kaladhar Radhakrishnan, Intel Fellow at Intel, about heterogeneous system integration trends and new developments in the semiconductor industry. Radhakrishnan shared his views ahead of his keynote at the SEMI Connecting Heterogeneous Systems Summit, 1-3 September 2021, an online event. Join the summit to meet experts from Intel and other key industry influencers. Registration is open. SEMI: What is driving the adoption of electronics and semiconductor devices nowadays and why is the development of new and innovative technologies important? Radhakrishnan: We are living in an increasingly data-driven world where devices have become an integral part of our lives. A recent study estimated that in the United States alone, 13.6 connected devices per capita consume an average of 300 gigabytes worth of data every month. In the workplace, COVID-19 has driven fundamental business changes that has sped up the adoption of digital technologies such as virtual conferencing, remote work, and e-commerce. Organizations are realizing that a high-quality video conference can be an adequate substitute for many in-person meetings. As a result, businesses are accelerating the digital transformation in order to adapt and thrive in this new environment. Five decades of sustained exponential growth in semiconductor performance has conditioned the average digital consumer to expect more from their devices. However, there are some headwinds ahead as traditional scaling slows down and power density rises. Because consumers and businesses are now generating data at a faster rate than they can consume it, technologists need to scale compute, storage, and bandwidth even faster to keep pace. Without investments in research and development of new and innovative technologies to address these challenges, the full potential of this data will go unrealized. SEMI: What forces are heightening the importance of heterogeneous system integration? What are the implications for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries? Radhakrishnan: The semiconductor industry increased transistor density and scaled performance through classical Dennard scaling until the turn of the century. By then, the gate oxide thickness had scaled down to atomic dimensions and the exponential increase in sub-threshold leakage signaled the end of scaling through traditional methods. Since that time, the chip industry has been relying on innovations in transistor materials and structures such as high-k metal gate, strained silicon, and FinFETs to keep pace with Moore’s law. However, this alone will not be sufficient to continue scaling and the industry needs to explore other vectors to augment improvements in transistor technology. Heterogeneous integration through advanced packaging is one key technology that can help drive these gains. Technologies like Foveros can enable device density scaling by creating a 3D stack of multiple die using high-density interconnects. Heterogeneous integration enables chipmakers to move from a monolithic system designed on a single large chip to a heterogeneous system comprised of a number of smaller chiplets. The main benefit of using smaller chiplets is that they improve yield and enable application based customization of the foundry processes. However, if the disaggregation to smaller chiplets is not accompanied by an increase in on-package bandwidth, the power and performance penalties associated with chiplet-to-chiplet communication will hobble system performance. This is why advanced packaging technologies that improve die-to-die communication are key enablers for heterogeneous integration. SEMI: What are some of the key technology challenges in developing heterogeneous systems? Radhakrishnan: The obvious challenge that most people focus on is the need for improved on-package bandwidth. However, as we rely on 3D stacking to continue device scaling at the package level, it is important to comprehend power delivery and thermal challenges as well. Power to the top die has to be delivered through TSVs on the bottom die, which not only adds resistance but also reduces the useful area available on the bottom die. This problem is further exacerbated when we stack more than two die. Excessive noise on the power delivery network can cause timing issues that limit the maximum operating frequency of the transistor. Similarly, when we stack multiple die, we must take into account associated thermal challenges. For example, each interface of the multi-die stack adds thermal resistance, which makes it harder to cool the chips at the bottom. SEMI: What are some of the key global market trends that driving demand for heterogeneous and system-level integration? Radhakrishnan: The number of artificial intelligence (AI) and machine learning applications have grown dramatically due to their ability to solve highly complex problems across a wide range of segments. AI and machine learning models require more memory bandwidth and compute capabilities that are difficult to achieve without some form of heterogeneous integration. Another market trend driving demand for heterogeneous integration is the increasing reliance on custom hardware accelerators. To combat the slowdown in frequency scaling and single-core performance, we have moved to multi-core architectures by tackling the inherent parallelism in our workloads. However, Amdahl’s law tells us that such an approach will hit a bottleneck when we reach the limits of the serial portion of the workload. As these constraints slow the performance of general-purpose processors, the reliance on custom hardware accelerators to boost performance for specific workloads is growing. Heterogeneous integration at the system level with a combination of CPUs, GPUs, FPGAs and other accelerators can optimize system power and performance. SEMI: What solutions is Intel developing to address these market needs? Radhakrishnan: Intel is actively involved in the development of the industry ecosystem for heterogeneous integration. We have developed a number of innovative advanced packaging solutions such as the EMIB and Foveros that are used in products today. Intel is also developing the next generation of advanced packaging technologies, Foveros Omni and Foveros Direct, which will dramatically scale the IO density by using direct Cu-Cu bonding technology. Foveros Omni is a crucial building block technology to enable high-voltage power conversion on the package for efficient power delivery. Intel is uniquely positioned to predict the design needs for future systems and deploy its resources to develop the technology building blocks needed to continue performance scaling. Our IDM 2.0 strategy enables us to leverage our leadership in packaging technologies to design the best products and use the best IP to deliver leading products across a broad range of categories. SEMI: What do you expect from your participation at SEMI Connecting Heterogeneous Systems Summit? Radhakrishnan: I’m hoping to shed some light on some of the new technologies we have been developing at Intel to enable heterogeneous system integration. I also want to bring awareness to the power-related challenges we are facing with heterogeneous systems. I also look forward to listening to what other industry leaders have to say on the topic. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He plays a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise include integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award, the highest Intel honor an individual or small team can receive. He has authored four book chapters, over 40 technical papers in peer-reviewed journals, and has been awarded 35 U.S. patents. He has also served as an adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after receiving his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Serena Brischetto is senior manager of marketing and communications at SEMI Europe.

On March 1, the semiconductor industry lost a true legend with the passing of Bill Tobey, an exemplary leader and contributor to the semiconductor industry throughout his career. SEMI honored Bill with our Bob Graham Sales and Marketing Excellence Award in 2006 for his work on wafer steppers. Bill and his team had the foresight to recognize that competing solutions such as Deep Ultraviolet (DUV) projection, e-beam, and x-ray would not be able to keep up with Moore’s Law. More importantly, Bill had the passion and marketing prowess to convince customers of this, even though early wafer steppers were twice as expensive and considerably slower than the alternatives. He used that passion to also convince management at GCA Corporation that they needed to shift resources to advance steppers and drive alignment with customers. I remember the critical role he played when we worked with GCA steppers during my early years at AT T Bell Labs. The Chip History Center virtual museum has a wonderful video interview with Bill Tobey on his conceptualizing of the wafer stepper and on his winning of the Bob Graham Award. Dan Hutcheson, CEO and chairman of VLSIresearch, shared these kind words on Bill Tobey’s influence: “The world of semiconductors and the products they made possible would have been much smaller, as Moore's Law might have stopped at 2 microns, without Bill's contributions. His ability to see what others could not probably explains why he was able to continue making contributions into his nineties. Companies all over the world continued to call on him to his last days.” Bill’s contributions were limitless. He was a member of the organizing committee for the SEMI Industry Strategy Symposium (ISS) and chaired it in its early years. After completing his term serving ISS, he joined the committee for the SEMI International Trade Partners Conference (ITPC). Bill also served as a member of the SEMI East Coast advisory committee in its early years and was responsible for industry meetings in the area. And he was involved with many other SEMI activities on behalf of the industry. Bill's obituary is posted on the funeral home website. For all of us working in the semiconductor industry, we are honoring Bill Tobey’s memory by continuing to build upon the foundation that he helped to establish. I hope you are inspired by the passion he displayed in his work throughout his career and encourage those who knew him to share stories of Bill to further inspire others to follow the example he set. Ajit Manocha is president and CEO of SEMI.

In the long unfolding arc of technology innovation, artificial intelligence (AI) looms immense. In its quest to mimic human behavior, the technology touches energy, agriculture, manufacturing, logistics, healthcare, construction, transportation and nearly every other imaginable industry – a defining role that promises to fast track the fourth Industrial Revolution. And if the industry oracles have it right, AI growth will be nothing shy of explosive.“The gains these days are not incremental,” said Ajit Manocha, SEMI president and CEO, said to a gathering in July of the Chinese American Semiconductor Professional Association (CASPA) for its Summer Symposium at SEMI’s headquarters in Milpitas. “They are hockey stick – exponential – with AI semiconductors growing in market size from $4 billion this year to $70 billion in 2025.”Manocha left little doubt that AI is remaking the semiconductor industry and, in the process, the world at large. Internet of Things (IoT) and 4G/5G, both key AI enablers, will account for more than 75 percent of device connections by 2025.“Today, 30 billion devices worldwide are connected,” Manocha said, citing an Applied Materials prediction that the number of connected devices globally will grow to between 500 billion and 1 trillion by 2030. Those devices will generate stunning amounts of data collected, interpreted and used to reason, solve problems, learn and plan, leading to the holy grail of autonomous machine behavior.To process this colossal amount of data central to the promise of AI, the industry must break through the limits of a key technology: memory. Memory a Critical AI BottleneckThe challenge for memory starts with performance. Historically, every decade gains in compute performance have outpaced improvements in memory speed by 100 times, and over the past 20 years that gap has grown, said Steven Woo, a fellow and distinguished inventor at Rambus, presenting at the symposium. The upshot is that memory has bottlenecked compute and, in turn, AI performance. The industry has responded with new ways to implement memory systems on AI chips. Each is suited to unique performance requirements and, of course, comes with trade-offs. Among the frontrunners: On-chip memory delivers the highest bandwidth and power efficiency but is limited in capacity. HBM (High Bandwidth Memory) offers both very high memory bandwidth and density. GDDR balances trade-offs among bandwidth, power efficiency, cost and reliability. Since 2012, AI training capability has grown 300,000 times, besting Moore’s law by 25,000 times in doubling every 3.5 months, a blistering pace compared to the 18-month doubling cycle of Moore’s law, Woo said. The staggering improvements have been driven by parallel computing capacity and new application-specific silicon like Google’s Tensor Processing Unit (TPU).These specialized silicon architectures and parallel engines are key to sustaining future gains in compute performance and combatting the slowing of Moore’s Law and the end of power scaling, Woo said. By rethinking the way processors are architected for certain markets, chipmakers can develop dedicated hardware capable of operating with 100 to 1,000 times greater energy efficiency than general purpose processors to overcome another big limiter to scaling compute performance – power.For its part, the memory industry can improve performance by signaling at higher data rates and using stacked architectures like HBM for greater power efficiency and performance, and by bringing compute closer to the data.Memory scaling for AIA key challenge is scaling memory for AI. Demand for better voice, gesture and facial recognition experiences and more immersive virtual reality and augmented reality interactions is tremendous, said Bill En, senior director at AMD, speaking at the symposium. These capabilities require more processing power across both high-performance computing (HPC) for big data analytics and machine learning as it relies on AI and machine intelligence to generate meaningful insights. Emerging machine learning applications include classification and security, medicine, advanced driver assistance, human-aided design, real-time analytics and industrial automation. And with 75 billion IoT-connected devices – all generating data – expected by 2025, there will be no shortage of data to analyze, En said. The wings alone of a new Airbus A380-1000 feature some 10,000 sensors.Mountains of this data are stored in massive data centers on magnetic hard drives, then transferred to DRAM before moving to SRAM within the CPU for the handoff to the compute hardware for analysis.With data growing at an exponential clip, the question is how to make sure all other memory systems can handle the flood of data. AMD’s answer is a chiplet architecture featuring eight smaller chips around the edge that drive the compute and a large chip in the center that doubles the IO interface and memory capability to in turn double chip bandwidth.AMD has also moved from a legacy GDDR5 memory chip configuration to HBM to bring memory bandwidth closer to the GPU for more efficient processing of AI applications. The HBM provides much higher bandwidth while reducing power consumption. Compared to DRAM, AMD’s HBM delivers a much faster data rate and far greater memory density, En said.Over the next decade, look for more performance improvements from multi-chip architectures, innovations in memory technology and integration, aggressive 3D stacking and streamlined system-level interconnects, he said. The industry will also continue to drive performance gains in devices, compute density and power through technology scaling.Michael Hall is a global marketing communications manager at SEMI.

This article is the fourth in a series highlighting the vital importance of SEMI Standards to commemorate the publication of the 1000th SEMI Standard in July 2019. Find the entire series here.Computer prices have plunged over the years even as desktop and laptop PC performance has skyrocketed thanks to the semiconductor industry, giving users much more bang for their buck. The chip industry stands in a stark contrast to healthcare and education with their exponentially rising costs.What distinguishes the semiconductor industry from healthcare and education in the capacity to deliver so much for so much less over time? After all, even in other parts of the technology sector that are heavily regulated, such as cable television, we have not witnessed the same price decreases as in microelectronics.Some pundits claim that the difference among sectors is tied to their degree of regulation. Does greater regulation somehow degrade product value? The reality is far more nuanced. But one thing is clear: Smart self-regulation (i.e. standards) in the semiconductor industry has contributed mightily to its success.The recipe for success has been simple. Standards have been rocket fuel for competition, which in turn has sparked innovation, driving down device prices while boosting performance. Computer prices fell dramatically between 1997-2015 while the cost of cable TV and internet services rose. Myth of unregulated competitionA semiconductor fab might actually be the most regulated place on earth. Fabs hew to a much higher standard of air quality and cleanliness than even uber-sterile hospital operating rooms. Manufacturing processes are voluntarily regulated not to millimeters, but to nanometers. While some standards are proprietary with limited reach, others span the supply chain. Regulation has worked so well in this sector that the semiconductor industry isn’t moving toward less standardization. It’s moving toward more. Secret is smart standards The gap between regulation and self-regulation is more like a chasm. We typically view regulation as a series of top-down directives that more often focus on the interests of the producer than the consumer. Healthcare regulation, for example, may improve quality of care, but it’s often insurers, big pharma and hospitals that benefit most from regulation, rather than consumers.The semiconductor industry, on the other hand, uses self-regulation to improve business operations and make better products for consumers. Falling prices and rising performance are natural byproducts.Semiconductor industry self-regulation is an ecosystem-wide effort, where input isn’t just top-down, but also bottom-up or even side-to-side. The first SEMI Standard, which specified wafer sizes, exemplifies this approach.The SEMI Standards Committee formed in 1973 to address silicon wafer dimensional specifications. At the time, wafer specifications proliferated. Numbering more than 2,000, the various specifications led to major inefficiencies just when the industry was just getting underway. Wafer suppliers banded together under SEMI to solve this problem and rapidly developed consensus specifications for 2- and 3-inch wafers. By the mid-1970s, over 80% of wafers conformed to these new standards.Standardized wafer sizes freed equipment companies to focus on innovations that reduced cost and increased performance. It also allowed manufacturers to focus on product differentiation without having to worry about device fabrication process and cost. Since that first SEMI Standard made possible the modern semiconductor equipment industry, original equipment manufacturers (OEMs) have competed to deliver amazing innovations. For example, lithography systems routinely use light to design chips with feature sizes smaller than the wavelength of light.SEMI’s 1000th standard on energetic materials demonstrates how smart standards are also pragmatic. This standard is not about banning materials or assigning blame when things go awry. It is about creating practical guidelines that companies will follow, enabling them to realize greater innovation. Guidelines that reduce accidents and risks will spur more, not less, energetic materials’ exploration. Industry suppliers will be the big winners.The 1st to the 1000th SEMI standard all represent examples of cooperation making more sense than competition.Standards for the real worldCreating a business-friendly standard that still gets the job done is a process. As SEMI Standards Task Force and Committee members, materials, equipment and manufacturing companies take part in defining best practice guidelines that support safe and practical use of materials and equipment. Task force and committee members assign particular responsibilities and associated costs to the most logical segments of the supply chain. They also develop information-sharing practices around competitive process recipes and purity standards.Andy McIntyre, CIH, a member of the energetic materials task force and an executive vice president and managing principal at BSI EHS Services and Solutions, summarized what makes SEMI standards smart.“SEMI standards are pragmatic,” said McIntyre. “They take into account the need for implementation in a real-world business environment. They embrace an engineering approach to problem-solving to create practical solutions, and they define specifications and performance goals in ways that allow engineers — in collaboration with EHS professionals — to identify practical solutions for reducing risk in R D, pilot line and manufacturing operations.“SEMI standards employ a holistic process that considers all the important points of view throughout the supply chain, from materials selection, installation, use, recycling and/or disposal,” said McIntyre. “The breadth of SEMI EHS Guidelines, for example, is also very comprehensive as the SEMI EHS Committee and task forces work to ensure that standards keep pace with dynamic technology developments. Energetic materials is a prime example where the industry recognized the need for a new safety guideline to document safe usage of pyrophoric, water-reactive and unstable reactive materials, which have become increasingly important in semiconductor and advanced materials R D and manufacturing.”This is the real secret to the success of the semiconductor industry. Smart self-regulation allows industry players to cooperate in the development and implementation of standards that are pragmatic, comprehensive and dynamic. Participants in SEMI Standards have a voice in the semiconductor industry because they are the voice of the semiconductor industry.While innovation in semiconductors may not always keep pace with Moore’s Law, we can depend on one truth: As long as collaboration and cooperation are the rule and not the exception, we will continue to advance technology in amazing and unprecedented ways. You, me and all other consumers will continue to reap the rewards of innovation. Use your voice to affect standardization in and around the semiconductor industry. Learn about SEMI Standards – and become part of the solution.Heidi Hoffman is senior director of technology communities marketing at SEMI. Hoffman and her team shine a spotlight on the work of the more than 20 technology communities under the SEMI electronics manufacturing supply chain collaboration platform. Actively engaging community members in marketing programs that showcase their unique value, Hoffman’s team helps companies to grow and prosper through the power of connection, collaboration and innovation.

AI vs. energy. Quantum for everyone. Biofabrication of human organs on a mass scale. Slowing advancements from Moore’s law.In the midst of a market dip, optimism reigned as keynote and AI Design Forum speakers addressed both looming challenges and explosive market opportunities during July 9-10 presentations at SEMICON West 2019 in San Francisco. SEMICON West again proved to be a magnet for visionaries who laid out the path to electronics innovation over the coming years.“The current business environment demands that the industry looks ahead toward issues that need attention sooner, not later – especially since we are approaching a once-in-a-generation inflection point that has the potential to be a $10 trillion opportunity,” observed SEMI Americas president Dave Anderson.Market forecasts punctuate the point: The microelectronics supply chain is on the verge of what has the potential to be the longest-lived electronics era.“Inflection points like this are rare, but not unprecedented,” Anderson added, citing 2007 as the inflection of the growth curve from new technologies that led to last year’s historic high semiconductor sales.SEMICON West squarely focused on the future, with a number of industry leaders noting that chip, tool and materials makers need to look beyond their immediate suppliers and customers in developing strategic partnerships. Dr. Cliff Young, data scientist with the Google Brain Team, for one, invited semiconductor and equipment firms to explore chip codesigning opportunities with his Google.The recently formed Quantum Economic Development Consortium – and its 50 members including Boeing, Google and IBM – debuted roadmapping activities devoted to the pursuit of U.S. leadership in the rapidly emerging global quantum computing industry. IBM’s Jeff Welser showcased the IBM Q Computer model built upon decades of semiconductor industry advances. Markets that could see staggering leaps from a quantum computational capacity include automotive, medical, financial and energy. Today, anyone can dabble with the future quantum computing capabilities by connecting online with IBM’s 16-qubit quantum computer. Dr. Aart de Geus, chairman and co-CEO of Synopsys, suggested that software and other programming tends to develop more quickly if it is open sourced. He recommends an open source model that allows semiconductor and equipment companies to work together in the cloud to speed chip development.Nate Baxter, TEL development and production group general manager, advocated sharing big data with competitors in pre-competitive spaces to ensure data quality, improve measurement and solve problems faster. The key is security. “Yes, we can share data while protecting it,” he said. “We’re quickly seeing opportunities that we didn’t know existed.”Gary Dickerson, Applied Materials president and CEO, said that embedding artificial intelligence (AI) in chips will drive significant long-term industry growth by processing far more big data computations much faster than humans can.That is, if there is enough electricity. Almost invisibly, AI-enabled machines already are crunching massive amounts of data while gulping power in the process. As AI use rapidly expands, current power grids will be stressed as never before. Dickerson added that speed of innovation, societal acceptance, security and safety will guide how well and quickly AI is adopted. A potential hurdle, however, is sustainability. He warned power constraints could be “very high” and a “barrier to AI adoption if we don’t drive innovation” in substantially reducing the power draw of power-hungry AI chips.Of the five members of a venture capitalist panel, four agreed that Moore’s Law as we knew it is dead. The promising news is that the average age of a first-time mobile phone user is 10, more than 40 percent of the world population is now under 25 and about to wield considerable market influence, and 5G is on the cusp of helping connect trillions of devices. AMD CEO Lisa Su noted “there’s a tremendous amount of innovation yet to come” from microarchitectural advances, chiplets and die stacking, and heterogenous platforms.And there’s nothing more innovative – or intriguing – than regenerating human organs in mass volume. Legendary inventor Dean Kamen laid out his well-funded plans to biofabricate the viscera of human existence but warned of two crucial missing pieces – scale and talent. “I’m here at SEMICON West to beg for high-tech’s help in getting artificial human organs out of labs and ramped up for volume manufacturing and widespread distribution,” Kamen said during his keynote. “The basic science already exists, but researchers can’t bring it to scale like Silicon Valley can.”The talent Kamen needs to fulfill his dream will come from the pool of skilled workers the microelectronics industry is feverishly working to recruit to make good on its own ambitions. As if on cue, SEMI endorsed Kamen’s FIRST Global program, establishing a united effort to encourage young people worldwide to pursue engineering careers. “Together, we can better help provide a path to success for generations to come,” SEMI’s Anderson said.Scott Stevens, SEMI

This year, SEMI ISS covered it all – from a high-level semiconductor market and global geopolitical overview down to the neuro morphic and quantum level. Here are key takeaways from the Day 1 keynote and Economic Trends and Market Perspectives presentations.In the opening keynote, Anne Kelleher from Intel pointed to the huge growth of data, with fabs collecting more than 5 billion sensor data points each day. The challenge, Kelleher noted, is to turn massive amounts of data into valuable information. Moore’s law is not dead. New models of computing benefit still from Moore’s law and advances in Si/CMOS technologies for conventional, deep learning, neuro morphic and quantum computing.With customers expecting continual improvements in applications, the question is whether the chip industry is moving fast enough to meet these expectations, Kelleher said. A broad supply chain, equipment and materials innovations, and attracting the “best of the best” college graduates to fuel innovation is key, she said.In the economic trends session, Nicholas Burns (ambassador ret.) from Harvard University pointed out that we will see a major shift in power. The U.S. will remain the major world power over the next 10 years, but we will see a major shift in power in the next coming decades as the gap with countries like China, Russia and India continues to narrow.Duncan Meldrum from Hilltop Economics said that we are passing the peak growth of economic cycle. He warns that a more likely outlook is that a global growth recession is developing. Although semiconductor MSI growth will see a noticeable slowdown in 2019 and 2020, the semiconductor industry is still healthy over the longer term.Bob Johnson from Gartner sees demand shifting from consumer to commercial applications with higher ROIs and budgets. AI, IoT and 5D are the major enablers. He sees structural changes in the semiconductor industry especially for memory but also for Moore’s law with increasing costs and fewer players.The DRAM markets shows volatility and NAND market may be negative in 2019 but non-memory are expected to accelerate mainly because of increasing content and some price hikes.Overall Gartner expects good long-term growth with a CAGR (2017 to 2022) of 5.1%, outpacing 2011 to 2016 CAGR of 2.6%. After a strong 2018 with 13.4% revenue, he forecasts a slower 2019 with 2.6% growth followed by a 8% growth in 2020 and negative growth rate in 2021.Andrea Lati of VLSI went “Back to fundamentals” in his presentation about the industry. VLSI sees a downside bias due to slowing global economy, tariffs, and trade wars. Future drivers are data economy, cloud, AI and automotive.As memory leads the 2019 slowdown, analog, power, logic and other sectors remain in positive territory. VLSI lowered its semiconductor equipment forecast for 2018 from 20% (Jan. 2018) to 14% (Dec. 2018) but increased its sales outlook from 8% to 15% in 2018. VLSI expects revenue to slow into the first half of 2019 but increase to over 4% in the second half of the year, resulting in total 2019 drop of 2.7%. Semiconductor equipment sales are expected to drop from 14% in 2018 to -10% in 2019.Michael Corbett of Linz Consulting, covering wafer fab materials in the years of 3D scaling, sees these as good times for the industry. His outlook for wafer fab materials is bullish based on strong MSI and because wafer fab materials suppliers are getting bigger because of M As.In the Market Perspective session, Sujeet Chand of Rockwell Automation pointed out that as more and more data is generated, the problem is how to get value of all the data collected. There is a need to create the right architecture for machine learning and AI and big data is increasingly being replaced by contextual/structured data. He expects Industry 4.0 to drive foundries to become smaller, more flexible and more productive.In the Technology and Manufacturing session, Aki Sekiguchi of TEL addressed process challenges in the age of co-optimization. The semiconductor industry continues to expand, driven by massive growth of interconnected devices, with heavy demand for processing power and storage. He expects an exponential increase of data from about 40ZB in 2018 to 50ZB in 2020 to 163 ZB in 2026.Major technologies such as DRAM, 3D NAND and logic are dealing with scaling challenges. The density of DRAM (Mb/chip) is plateauing according to 2015 to 2020 trend data, with DRAM is in need of EUV. Memory capacity demand is leading to increasing layers and higher aspect ratios that is concern for 3D NAND and mainly for plasma etch. With Logic already implementing 3D structures, it appears to be in a solid position. Buddy Nicoson of Micron talked about his 50 years in the industry and looked ahead to the next 50. The anchors – quality, cost, scale and speed – won’t change. It has been a great journey so far with unprecedented opportunities and challenges ahead of us. We are getting into a convergence (specialization, integration) and solution-based phase. We will see some inflection points in the coming years, with the best yet to come.Christian G. Dieseldorff is senior principal analyst in the Industry Research and Analysis group at SEMI in Milpitas, California.

Materials innovation has always been vital to the semiconductor industry. In the past, it was high-κ gate dielectrics. Today, Cobalt is seen as a replacement for Tungsten in middle-of-line (MOL) contacts.What materials innovation will the future bring?A likely answer is Graphene, the wonder material discovered in 2004.Graphene is one atomic layer of carbon, the thinnest and strongest material that has ever existed. It is 200 times stronger than steel and the lightest material known to man (1 square meter weighing around 0.77 mg). It is an excellent electrical and thermal conductor at room temperature with an electron mobility of ~ 200,000cm2.V-1.s-1. At one atomic layer, graphene is flexible and transparent. Other notable properties of Graphene are its uniform absorption of light across the visible and near infrared spectrum and its applicability towards spintronics-based devices.Graphene and Moore’s LawMoore’s Law scaling can be broken down into 4 key areas: Lithography FET Advanced Packaging (2.5D and 3D IC) Interconnect Material Solutions for upcoming nodes are starting to emerge in the first two areas (EUV and Nanowire- or Nanosheet-based FET respectively). Graphene play an important role in the latter two areas. For advanced packaging, Graphene can be used as a heat spreader (to lower overall thermal resistance), or as an EM shield (to lower crosstalk) as part of a 3D IC package.Active Graphene device layers can potentially be stacked on top of each other using a low-temperature transfer process ( 400°C) to allow for a dense heterogeneous “memory near compute” configuration. This is an area DARPA is actively researching as part of its new $1.5 billion Electronics Resurgence Initiative.Regarding interconnects, Copper interconnects are running out of steam and becoming a major IC bottleneck (projected 40% total delay for 7 nm node). Graphene’s high electron mobility and thermal conductivity make it an attractive interconnect material for MOL and back-end-of-line (BEOL), especially at line widths 30 nm.Graphene Device ApplicationsGraphene-based semiconductor applications are already starting to hit the market. A fully integrated optical transceiver (with a Graphene modulator and photodetector) operating at 25 Gb/s/channel was on display at the recent Mobile World Congress in Barcelona. San Diego-based Nanomedical Diagnostics is selling a medical device that uses a Graphene biosensor. Europe-based Emberion is building Graphene optoelectronic sensors that might find a home in LIDAR applications, where there is currently a focus on improving sensing in low-light conditions.What will the overall Graphene roadmap in the semiconductor industry look like? The history of ion implantation serves as a good example of how a fundamental scientific discovery moves from the lab to the foundry floor.The dominant view in the semiconductor industry at the time was that ion implantation would not work in practice (vs. thermal diffusion) and that, if it did, it would only marginally improve the manufacturing yields of existing products. There was nothing obvious about the transfer of ion bombardment techniques from nuclear physics research to semiconductor production.Varian (led by British physicist Peter Rose) built a new, advanced ion implant tool that Mostek (DRAM manufacturer based in Texas) was able to use to create MOS ICs with clear competitive advantages. The successful collaboration between Varian and Mostek was the turning point in the development of ion implantation as a major semiconductor manufacturing process. Over the next few years, semiconductor firms used ion implantation in a growing number of process steps and, by the late 1970s, it became one of the main processes used in semiconductor manufacturing.Likewise, the Graphene world needs to work closely with the semiconductor industry to develop the tools and techniques required to solve fundamental issues around Graphene growth (good uniformity over large area, low defect density) and Graphene transfer (high throughput, CMOS compatible). It is only then will we fully realize a future that includes 2D materials.The first step in this process is cross-industry education and initiating the dialogue between semiconductor industry and graphene companies. The National Graphene Association will be hosting the largest gathering of graphene companies and commercial stakeholders at the Global Graphene Expo Conference, October 15-17, 2018, in Austin, Texas.Learn more about graphene at the upcoming Global Graphene Expo Conference with dedicated panels of experts and investors, and roundtable discussions on how Graphene will impact the semiconductor industry. The event promo code is SEMINGA. About the AuthorAnand Chamarthy is the CEO and Co-Founder of Lab 91, an Austin-based startup that is working towards Graphene/CMOS integration at the foundry level. Anand can be reached at [email protected]. About the National Graphene AssociationThe National Graphene Association is the main organization and body in the U.S. promoting and advocating for commercialization of graphene and addressing critical issues such as standards and policy development.

Driven by the adoption of evermore electronic components in end products, the semiconductor industry is facing a new era in which device scaling and cost reduction will no longer continue on the path followed for the past few decades. Advanced nodes no longer bring the desired cost benefit, and R D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to satisfy market demands, the industry is looking for technology solutions to bridge the gap and improve cost/performance while at the same time adding more functionality through integration.More than-Moore devices (including MEMS and sensors, CMOS Image Sensors, power electronic, along with RF devices) represent this new functional diversification of technologies, combining performance, integration and cost not limited to CMOS scaling, and their importance will become more and more preponderant.In 2017, wafer demand for More than Moore devices1 reached almost 45 million 8-inch eq. wafers. This figure is expected to reach more than 66 million 8-inch eq wafers by 2023, showing an almost 10 percent growth during this period.This increase is supported by the famous megatrends detailed in the new analysis, Wafer Starts for More Than Moore Applications2, performed by Yole Développement (Yole). This analysis is relevant to the following markets: 5G with wireless infrastructure and mobile segments, mobile including additional functionalities, voice processing, smart automotive and electrification, AR/VR3, and AI4.For the first time, the market research and strategy consulting company presents a dedicated technology and market analysis focused on the overall wafer demand for More than Moore devices. The aim of this report is to give an overview of wafer shipments for More than Moore devices, from wafer size to semiconductor material substrate type including silicon, glass, SOI5, SiC6, SiGe7, GaN8, InP9, GaAs10, sapphire and ceramic, and thus identify business opportunities in the More than Moore industry.For over 20 years, Yole has been analyzing the industry evolution, discussing with leading companies to understand market challenges, and identifying technical breakthroughs. The Wafer Starts for More Than Moore Applications report is the result of this 20-year research. Yole’s analysts combine technical and market expertise to describe the More than Moore world. Market size (volume and value), substrate sizes and formats, value chain, technology processes and market drivers, business opportunities and competitive landscape are all part of Yole’s analysis.The various research teams at Yole, encompassing power electronics, imaging and sensing, RF and semiconductor manufacturing, collaborate to present an in-depth understanding of the current market evolution, taking into account innovations and emerging businesses. This methodology allows Yole to cover the overall megatrends and illustrate the links between wafer substrate, device, module, sub-system, system and high-end product.Under this dynamic ecosystem, the deployment of renewable energy sources and industrial motor drives as well as the electrification of the automotive industry are good examples of the impact of megatrends on the semiconductor industry development. They are directly impacting the power devices’ wafer market, resulting in an expected 13 percent CAGR between 2017 and 2023. Already in 2017, this market represented more than 60 percent of the overall wafer market for More than Moore devices, and is currently still dominating the More than Moore industry.5G is one megatrend driving wafer demand. 5G is leading the More than Moore evolution, bringing any service to any user, anywhere. Antennas and filtering functionalities are two of the key innovations of this evolution.Without doubt, the stringent requirements of 5G are driving increasing demand for RF components like RF filters, power amplifiers (PAs), and low-noise amplifiers (LNAs) to ensure access to tomorrow’s radio network.This year, Corning and Menlo Micro announced a major agreement to develop a DMS[11] product platform. Both partners propose an innovative approach based on TGV12 packaging technology. According to both partners, this technical choice allows them to cover operation of frequencies beyond 50GHz. Amongst the numerous megatrends, mobility is not far behind 5G. Demand for advanced mobile applications integrating more and more functionality is growing. In order to compete companies are developing smart combinations of devices such as fingerprint sensors, ambient light sensors, 3D sensing, microphones, and inertial MEMS devices. As an example, impressive developments focused on SOI-based NIR sensors have been released by SOITEC for front-side imager applications including advanced 3D image sensors. This technical evolution will clearly contribute, in the near future, to strong growth of the wafer market for MEMS and sensors. Additionally, the automotive industry, with the development of smart cars, has reached a new level of complexity requiring the development and integration of new sensors. In this context, many companies are aiming to extend their capabilities in ADAS13 and autonomous driving. Recently the leading company On Semiconductor acquired SensL Technologies, the leader in SPAD and LiDAR sensing products for automotive. This acquisition is one sign among many highlighting the evolution of this historic industry, searching for new expertise and welcoming new players, more aware of consumer habits and needs.Yole’s analysts expect smart automobiles to drive consistent growth of CIS14 and sensor wafer production over the next five years. It is fueled by the increasing integration of high-value sensing modules like RADAR, imaging, LiDAR and more. Although automotive will be mainly supported by these growth areas, historic MEMS and sensors such as MEMS pressure sensors and inertial MEMS will continue growing at a reasonable rate, supporting the standard automotive world.Yole Group of Companies including Yole, System Plus Consulting, KnowMade, PISEO and Blumorpho follows and analyzes the industry continuously. The Group has developed in-depth expertise and knowledge focused on the semiconductor manufacturing process and markets. Companies of the Group work together to understand the technical issues, identify business opportunities and propose valuable analyses.Yole invites you to an overview of the Wafer Starts for More Than Moore Applications report during the exclusive online event, titled “Wafer Starts for More than Moore Applications – Webcast”. This hourlong webcast takes place on June 28 at 5:00 PM CEST. The market research company will present key results of this report including megatrends, wafer market evolution and technical trends. Moderated by David Jourdan, Sales Coordination Customer Service at Yole, it welcomes the two leading companies, SPTS (an Orbotech Company) and Corning Precision Glass Solutions: "Trends in Wafer Processing Technologies for RF MEMS" – Speaker David Butler, Executive Vice President and General Manager at SPTS Technologies "Benefits of Through Glass Vias for RF applications" – Speaker: Ravij Parmar, New Product Development Manager for Corning Precision Glass Solutions These results will be also presented by the Semiconductor Software team at SEMICON West (Booth #1320), SEMICON Taiwan and SEMICON Europa (Booth #A-4667). Make sure to meet Yole’s analysts and get a valuable overview of the More than Moore industry. Agenda and more information are available on i-micronew.com. Stay tuned!About the authors:Amandine Pizzagalli is a Technology Market Analyst, Equipment Materials - Semiconductor Manufacturing - at Yole Développement (Yole). Amandine is part of the development of the Semiconductor Software division of Yole with the production of reports and custom consulting projects. She is in charge of comprehensive analyses focused on semiconductor equipment, materials and manufacturing processes. Emilie Jolivet is Director of the Semiconductor Software Division at Yole Développement, part of Yole Group of Companies, where her specific interests cover package assembly, semiconductor manufacturing, memory and software computing fields. 1 Including: MEMS sensors, CIS, and power, photonics and RF devices2 Yole Développement, March 20183 AR/VR : Augmented Reality/Virtual Reality4 AI : Artificial Intelligence.5 SOI : Silicon On Insulator6 SiC : Silicon Carbid7 SiGe: Silicon Germanium8 GaN: Gallium Nitride9 InP: Indium Phosphide10 GaAs : Gallium Arsenide111 DMS : Digital-Micro-Switch12 TGV : Through Glass Via13 ADAS : Autonomous Driving Assistance Service14 CIS : CMOS Image Sensor