EDA

Creating a custom Internet of Things (IoT) IC is challenging because it involves multiple design domains (digital, analog and RF). Creating a sensor-based IC that combines electronics that use the traditional CMOS IC design flow with a MEMS sensor on the same silicon die, however, can seem impossible. Couple the co-design and verification challenges with a lack of traditional process design kit (PDK) support for MEMS, and you have a tough road to travel to get your IoT designs to market.What can we do to make the sensor-based IoT design community successful?Understanding the ChallengesThe sensor-based IoT IC typically features a MEMS sensor (and optional actuator) that interact with the real world. Analog and digital circuitry processes the signals and sends them to a CPU. The CPU provides the “smarts” to process the data from the sensor and then sends processed data via a radio to the Internet; alternatively, the CPU could activate the actuator. A typical sensor-based IoT IC (Source: Mentor: A Siemens Business) Based on the complexity of the system, designers face many co-design challenges: Analog design requirements imposed by MEMS: MEMS devices often require high voltages and multiple power supplies; they emit small signals that need amplification and conditioning; and they are sensitive to the environment and require calibration. Design flow interactions: Parasitics from MEMS devices might affect circuits and vice versa. Circuit designers need MEMS models for impedance and timing. Integration: MEMS devices operate at different timescales than circuits, which adds a layer of complexity. Compounding the problem is a lack of MEMS PDKs and methods to tie together ICs and MEMS PDKs for integration and cross-verification. After conquering the co-design challenges, the design team has to address mixed-domain simulation challenges that include: Simulating the system: This requires verification of MEMS, digital, analog and RF circuitry with embedded software that runs on the CPU. Timescales: These vary widely, from a single deflection of the MEMS transducer in femtoseconds to a seconds-long simulation of the embedded software performing a measurement and transmitting data. Simulation time: Simulation of a behavioral digital design is extremely fast. However, the system simulation requires stand-in models that incorporate the behavior of the analog and MEMS block to simulate in an acceptable amount of time. The challenge of timescales for co-simulation. (Source: Mentor: A Siemens Business) MEMS is the KeyThe reality is that it’s the MEMS device that adds extra complexity to the sensor-based IC design and verification flow. To amplify the problem, the MEMS manufacturing process is not nearly as mature as the standardized IC process. For example, the standardized IC process includes ready-made PDKs that include everything designers need to move through design and verification flows. Foundries often provide soft and hard IP to quickly build-out design, and EDA tools provide high levels of automation enabled by abstraction and a standardized IC flow. How will MEMS-based design evolve?MEMS-based design must catch up to the standardized IC process. The first step is providing MEMS PDKs that include: Multi-physics domain design rules and material properties Packaging information Wafer and bonding information Fabrication information We must also tackle issues associated with these PDKs, including: Ownership, distribution and maintenance of the PDKs Consensus on the contents of the PDKs Merging of CMOS and MEMS PDKs The industry needs to move toward standardized MEMS manufacturing processes with available PDKs. Companies must provide IP and recommend structured design methods for co-design and verification of ICs that incorporate MEMS. How can EDA help with these flows?The EDA ContributionEDA companies must work with teams in the MEMS IC co-design space, collaborating with MEMS fabricators to help enable PDKs. By incorporating PDK support within their own tools, EDA companies can provide an integrated custom IC flow that allows teams to design and verify MEMS-based ICs. For details about this flow, click here to download the Mentor whitepaper: Fusing CMOS IC and MEMS Design for IoT Edge Devices.Greg Lebsack brings 25 years of executive and technical management experience — along with a proven track record of building strong teams and delivering predictable results — to his role as general manager of the ICDS division of Mentor, a Siemens Business. Lebsack joined Mentor in 2015 after that company acquired Tanner EDA, where he was president. Prior to Tanner EDA, he held management and technical positions in a number of different industries and companies, including Sprint, General Electric and McKinsey Co. Greg holds a bachelor’s degree in business administration from Northern Arizona University.Greg Lebsack recently presented on the topic of Integrated Co-design of MEMS/IC at the MEMS Sensors Technical congress, a technical conference organized by the MEMS Sensors Industry Group.

Constant coverage of an invigorating topic like machine intelligence in the media often urges us to consider its use in EDA technology. As is often the case, there are many myths and falsehoods that consume our time and effort when trying to apply machine intelligence to EDA. This article aims to uncover the myths and to provide helpful advice on applying machine intelligence to your EDA project or product.Value PropositionFirst, there needs to be a clear value proposition for adding machine intelligence to an EDA product. Using machine intelligence to create a me-too product adds no value. EDA customers are too busy to understand or care about an EDA tool’s underlying technology. They just want to use the tool and get results. If the tool delivers value, if it delivers tangible benefits, then they’ll use it. Otherwise, they won’t.Currently, EDA tool developers are already experimenting with AI and machine intelligence without considering this fundamental truth – without a higher-end objective. AI must deliver something better or new, whether a speed advantage, a performance advantage, new features, new insights, or perhaps even something pleasantly surprising. Before you write a single line of AI-enhanced code, you need to clearly understand how AI will enhance the product. What is the value proposition?Use ModelThere’s a major barrier to customer adoption of AI and machine intelligence technology for EDA tools: EDA users are averse to make decisions based on probabilistic results. Instead, half a century of EDA tool use has conditioned them to expect deterministic outcomes from their tools.Back in 2003, a prominent visionary and EDA investor was quoted in an interview, saying: “If I open my eyes five years from now, all static analysis in VLSI will be statistical.” Many EDA luminaries have been proven wrong over time for betting that EDA users will accept statistical results. As enthusiastic as I am about using machine intelligence to improve EDA tools, I must urge caution based on the history of EDA failures that employed a probabilistic use model. Decision-makers and EDA tool users want to see deterministic answers to questions about yield or slack, not probabilistic ones.Our experiences at Paripath in developing the PASER (Paripath Accelerated Simulation Environment) tool also bear this out. We discovered that delivering results 50x faster but with 92% accuracy was simply not good enough for end users. EDA users only started to use PASER when its answers became 98+% accurate. To be adopted in the production flow, the tool had to deliver 99% accuracy.Data EngineeringThere are specific ways to achieve these accuracy goals. The first is data engineering. Machine intelligence is a new approach to EDA tool development and it needs to be trained on a data set. If the data is poor or incomplete, training will create an inaccurate model. Fundamental software-development rules still apply. Garbage in, garbage out.Without good training data, there’s no way for you to build good neural-network models. If you train a model with garbage data, you’ll get a garbage model. You must cleanse the data before you use it for training. Otherwise, the model will draw inaccurate conclusions and customers will not use your tool. The model is not to blame here. The model’s not wrong. The problem lies in poor data engineering, poor data cleansing, and a lack of discipline to prepare input data.High DimensionalityNext, machine intelligence has a unique ability to quickly solve problems of high dimensionality. Pure EDA problems often have high dimensionality. Over the years, EDA developers have perfected the art of segmenting the problems into sequencing solutions with lower dimension. Machine intelligence technology can handle problems with thousands of dimensions, but you need to be careful when tackling problems that have high dimensionality. Too many dimensions can produce confused or inaccurate results with AI and deep-learning technology.It helps to visualize the problem and to analyze the data set before using the data to train an AI-enhanced EDA tool. Several visualization methods can help. For example, t-SNE (t-Distributed Stochastic Neighbor Embedding) lets you reduce a data set’s dimensionality from a very large number to a much lower number. Figure 1 shows a high-dimension dataset with a dimensionality of 2000, which has been reduced to a low dimensionality of 3. Figure 1: Visualizing the Data Set with Lower Dimensionality Reducing the dimensionality of a data set to 3 using t-SNE and visualization allows you to quickly see whether the data set defines an easy or a difficult problem. If the problem is difficult, you’ll likely need to lower the problem’s and the data set’s dimensionality before using the data to train a neural network.Technology SelectionOne factor that determines whether it will be easy or difficult to incorporate machine intelligence into your EDA tool is your choice of AI development tools. AI researchers have developed a long list of frameworks, libraries, and languages that they use to develop AI and machine-learning software. Frameworks and libraries such as TensorFlow, Caffe and MXNet are most popular for developing deep-learning models.However, these tools are not yet popular with the EDA development community. The languages of choice in the EDA community are traditionally C and C++ for development and Tcl for prototyping and creating user interfaces. The rest of the software world has moved on to newer development languages such as Python, Java, R, and such. Moreover, machine-learning development segments into two distinct processes: training (i.e. generating the model) and inference (i.e. using the model).Another question to consider is where to generate the model – at the vendor site or the customer site?Consequently, fitting AI and deep-learning development into EDA development environments can feel like fitting a square peg into a round hole. You may need to create corners in your hole.EDA is a very small player in the overall software market. Relatively few software developers are familiar with writing EDA tools. It’s best to select AI and deep-learning development tools that can provide some sort of interface that’s compatible with EDA’s development tools of choice. Some AI frameworks have lower-level C and C++ interface layers that provide a familiar entry point for experienced EDA developers.At Paripath, we chose TensorFlow for exactly this reason. TensorFlow has a lower-level C/C++ interface. Although the resulting development path becomes a longer one using this approach, it’s a more familiar path for EDA developers and therefore it’s a path that can ultimately lead your EDA development team to success. An elaborate study of comparing these frameworks has been published in the book Machine Intelligence in Design Automation.Integration into Legacy SystemsWhen you understand the value that you expect machine intelligence to add to your new EDA tool, when you’ve cleansed and then analyzed the data set, and when you have selected an appropriate set of development tools, you’re finally ready to add machine intelligence to your EDA development. There are two use models for AI-enhanced EDA tools. The first uses a trained model to guide the EDA tool’s decision-making. In this use case, the trained neural network doesn’t change. The software’s accuracy doesn’t improve with use unless the company that developed the EDA tool retrains the underlying neural network. This use case follows the familiar, existing use case associated with EDA tools developed using deterministic algorithms.For the second use case, the end user is able to retrain the underlying neural network, which allows the EDA tool to produce better, more accurate results over time. This use case produces a win/win situation because end users are able to hone their tools and improve them over time, without help from the EDA tool vendor’s application engineers. If the retrained models are also sent back to the EDA developer for incorporation into newer versions of the tool, all users benefit from other users’ training data.It’s not clear how you’d support this second use case in the current EDA business environment where most data sets are proprietary and are carefully guarded. Most large EDA tool customers want to keep their data in house under tight control. Even with this somewhat restrictive situation, however, EDA tools benefit from the incorporation of machine intelligence because each EDA tool customer can customize the tool and improve its results.Machine intelligence has much to add to EDA tools’ capabilities. Only time will tell if the customers want and will accept these new capabilities. Rohit Sharma, founder and CEO of Paripath Inc., is an engineer, author and entrepreneur. He has published many papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna - an advanced characterization software for modern nodes. Sharma has written a book titled “Machine Intelligence for Design Automation.” You can download code examples and other information here.Note from SEMI-ESD Alliance: ESD Alliance’s Interoperability Committee brings together the industry to discuss interoperability. By focusing the efforts of the electronic system design community onto key compute operating systems, the Interoperability Committee seeks to define a stable, interoperable environment for tools and streamline the resources required to support these environments. The EDA Industry OS Roadmap presents guidelines to EDA vendors and customers for compute platforms to target for design starts. Learn more and view the OS Roadmap overview at our website.

I really don’t know clouds at all. – Joni MitchellThe semiconductor industry is finally on the cusp of joining the cloud revolution. The cloud has offered the promise of greatly expanded resources for years, but adoption has been slow due to lingering concerns. The biggest contributing factor for the concern over moving from on-premise EDA servers to cloud-based servers is, surprisingly, the rise of third-party IP. In the old days, if you were developing 100 percent of your own IP, and if you put that IP on a public cloud, and it somehow leaked out, well shame on you. That would certainly be bad for business. It might hurt your reputation a bit. But these days, with so much third-party IP being embedded into chips, if that third-party IP leaks out, that’s a lawsuit-fest in the making.Consequently, semiconductor companies now have even more incentive to protect IP with advanced security. Surprisingly, cloud-based security is far, far better than on-premise security. Why? Because keeping customers’ data secure is the central mission of cloud service suppliers, so they’ve developed a rich set of security tools to protect the data that’s entrusted to them by their clients. In many ways, you can maintain much better security in the cloud than you can with on-premise tools. Image credit: Markus Spiske temporausch.com from Pexels Amazon Web Services: Exemplifying the benefits of cloud computingTake Amazon Web Services (AWS) as an example. (Note: AWS is not the only vendor in the cloud space, but it’s one I’m very familiar with.)AWS has developed the concept of security groups – firewalls that you throw up around any network interface to allow only specific traffic into that secured network. You can do that for just one server or for a fleet of servers, in just seconds. Most on-premise server networks won’t let you work that quickly, or as easily, or with such fine control because most such networks lack the security tools to do this.In addition, AWS allows you to encrypt every bit of data stored on and flowing through its cloud-based storage systems. You can encrypt data at rest in on-premise storage but it’s a lot harder to encrypt data flying through the on-premise network. Amazon’s Elastic File System (EFS), a managed NFS file service, offers the ability to easily encrypt NFS traffic on the wire, a difficult feat at best with an on-premise solution.AWS built-in encryption key-management service can rotate encryption keys automatically. The cloud also allows you to have key policies that are easy to implement and maintain.Internal corporate networks rely heavily on perimeter firewalls for security. Perimeter defense just cannot deliver sufficient security against determined hackers and everyone realizes this. We’ve built big, open, on-premise networks that are just not well-suited to implementing adequate security protocols. Trying to retrofit these network architectures with additional security is time-consuming and costly, and it hurts engineering productivity. Moving to the cloud gives you a greenfield opportunity to right some of the wrongs of the past.Continuing with AWS as an example, here are some additional advantages of EDA in the cloud: AWS provides physical security that’s far above and beyond on-premise security. It doesn’t publish the physical locations of its data centers. It also has professional security staff 24/7, keycard access, and additional security features that far exceed typical on-premise physical security. AWS automatically manages security patches and access controls for their managed services such as database services. AWS gives you plenty of security tools to automate security processes, audits, and so forth to protect your data. AWS gives you so much flexibility that you can get yourself in trouble in you are not careful. If you want, you can create the same sorts of security holes that already exist with on-premise networks. You shouldn’t of course, but you can if you’re not thoughtful about things. You just need to hire the right people to implement and maintain your cloud security.Here are five very big differences between AWS (cloud-based) and on-premise server networking: Elasticity: Cloud-based systems enable you to scale up in minutes. That ability has pluses and minuses depending on how disciplined you are. On the plus side, you can quickly grow your EDA infrastructure as big as you want and then shrink it back down when you no longer need the additional capacity. All you need to do is tell the cloud service that you need more capacity and it will bring that extra capacity online for you in minutes – and will charge you for it. (That’s the minus side.) When you’re done, you can turn off the extra capacity (and stop paying for it) with the same speed. If you want to provision more EDA capacity for your on-premise network, you’ll need to beg, borrow, or steal existing capacity from someone else on your network, or you can order more servers, get the vendor to build and ship them, install them in your server room, provision them, and bring them online. That will take months. Fault tolerance: On-premise networks rely on large, monolithic service architectures, which saddle EDA vendors with more than 30 years of technical debt. The cloud operates on a different model, one that’s based on containers and microservices. This is inherently a redundant, fault-tolerant computing model if you write your code correctly. The difference between redundancy in the cloud and in on-premise networks is night and day. There’s no comparison. No private networks can match the available and growing redundancy of cloud systems, which have redundant servers inside of a data center and redundant data centers in multiple, worldwide geographic locations, which protects your data from natural and man-made disasters. Network segmentation: Many semiconductor developers have several design centers distributed around the world and there may be IP in use on a project that cannot be shared with certain geographic locations either by law or by contract. Cloud networks are already set up with automated tools for network segmentation that can enforce geography-specific rules through VPCs (Virtual Private Clouds), which are easy to set up. VPCs allow you to set up subnets with restrictions based on routing tables so that IP management and control become highly automated. Removal of single points of failure: The typical EDA grid configuration has several built-in single points of failure. For example, a central job dispatcher generally runs on one single node. If that node dies, all EDA work halts. The same is true for EDA license servers and for configuration-management and version-control servers. Again, because cloud networks are based on the microservices concept, the cloud simply doesn’t need to have the same single-point-of-failure vulnerabilities that on-premise networks have. On-premise networksTo get these same advantages with on-premise networks, the grid architecture must fundamentally be changed, starting with the replacement of NFS. EDA systems need to replace huge, monolithic file systems specifically developed for EDA with object storage. That's a tall order – one that requires the rewriting of fundamental assumptions that serve as EDA software’s foundation.In the 1980s, 1990s, and early 2000s, small EDA startups appeared to fill gaps in the offerings of the large EDA players. If they succeeded and grew, they’d eventually be gobbled up by a larger EDA vendor. That flowering of EDA startups seems to have damped down. The market has really matured.Next wave of EDA startups to offer cloud-first toolsGoing forward, I expect the next wave of EDA startups will be offering cloud-first tools that are not burdened by three decades of technical debt. They’ll be able to architect their tools specifically for the cloud.We’re starting to see this happen. For example, Metrics, a Canadian EDA startup, offers a pay-by-the-minute, cloud-based simulator and verification manager. Although one job on one cloud server might run slower than a monolithic simulator running an on-premise server, Metrics has architected its tools so that you can throw more servers at the problem, allowing you to run all of your jobs at once. Here, multiple simulation jobs running concurrently on multiple servers will ultimately finish faster than running the jobs serially on one slightly faster on-premise simulator.That’s the kind of innovation that we’re going to see. That’s the future of EDA.Derek Magill is executive director and president at HPC Pros. Derek has 20 years of experience supporting semiconductor engineering functions. His main focus has been in system architecture and technical management, but over the years he has been involved with technologies such as EDA licensing, ClearCase, HPC architecture, IP management and engineering software support. Derek spent 15 years at Texas Instruments in various technical and managerial roles. He is currently a senior manager, IT at Qualcomm managing the Global License Infrastructure team as well as the lead technical architect for the company's engineering cloud activities. The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, is the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. As an international association of companies providing goods and services throughout the semiconductor design ecosystem, it provides a forum to address technical, marketing, economic and legislative issues affecting the entire industry. The ESD Alliance also stages events that promote networking, learning and collaboration among member companies. To learn more about the ESD Alliance and how to join the group, visit www.esd-alliance.org or contact Bob Smith at [email protected].

IC design has emerged as the largest semiconductor sector in China, with 2017 revenues of $31.9 billion generated by about 1,380 companies. At the same time, China’s fabless segment has risen to third in global rankings with about one-tenth of worldwide sales.Most of China’s fabless segment produces the logic chips that are key to defense, telecommunications, finance and other industries important to the region’s national security interests and its independence from U.S. and other international suppliers. Investment in fabless logic continues to be the top priority in China’s Phase 2 investment. In mobile, China made meaningful progress through HiSilicon and Spreadtrum, both fabless design houses.In 2017, HiSilicon and UNISOC (formerly Spreadtrum), China’s two largest domestic IC design companies, were ranked in the global top 10 of fabless companies, though most Chinese IC design companies are small, with revenues under $1 million. Working with domestic smartphone makers, both companies have carved out a strong presence in logic and, in particular, the communications and application processors that power data centers and Internet of Things (IoT).Despite their rapid rise, China’s AI accelerators and cryptocurrency ASIC suppliers have yet to appear in China’s top 10. However, we expect their aggressive roadmaps and early adoption of leading-edge process technologies to propel them into the top 10 in the near future. As illustrated in the figure below, an examination of the competitiveness of China’s semiconductor segments reveals that the close proximity of China’s fabless companies to the region’s electronic systems makers plays to their advantage, though access to IP and leading-edge process technologies is a barrier to their growth in the near term. A key barrier to China’s foundries is their limited ability to develop leading-edge process technologies and strategic relationships with top international fabless companies. Most leading international fabless companies rely on customer-owned tooling (COT) and design tools for design. As the approach takes time to develop, it will not support China’s aggressive goal and timeline to independently meet domestic IC demand. Instead, China has been disciplined in executing its strategy to acquire valuable IP and leading-edge technologies by aggressively partnering with international fabless design leaders and pursuing deals with market leaders and laggards. The initial entry point for Chinese fabless companies was the low-margin consumer applications dominated by Chinese suppliers, giving them considerable control over demand. In addition, Chinese companies have aggressively hired top talent from abroad and grown the skills of its engineering workforce to sustain innovation. China will likely free itself from its reliance on non-Chinese developed manufacturing process technology and EDA design tools.China’s semiconductor design growth, concentrated in the Pearl River Delta (see figure below), is fueled by national and local investment programs. SEMI August 2018 The Pearl River Delta, which includes Xiamen, Quanzhou and Shenzhen, is establishing itself as China’s IC design, system and application hub. Domestic and international companies are eligible for investment provided they are established or investing in one of the four regionshat are home to various sectors of the electronics and semiconductor supply chain. Access to large investment funds, coupled with China’s infrastructure build-out, is a strong supporting force to drive the growth of top-tier domestic fabless companies. For its part, the Phase 2 of China’s National Investment Fund targets investments of RMB 150 - 200 billion ($23 billion - $30 billion) in IC design. The growing domestic consumer base and infrastructure investment will drive opportunities for China’s fabless companies over the next decade.To learn more about the latest development on China IC Industry, and get a sample of the China IC Ecosystem Report, visit http://www.semi.org/en/china-ic-ecosystem-report.China IC Ecosystem Report covers the rise of China’s IC industry, national and local government policies, public and private funding, and their implications for China's IC supply chain. The report also compares key domestic companies and their international peers segment by segment.Eugenia Liu is a senior product marketing manager at SEMI. Shanshan Du is chief analyst and program director at SEMI China.

What’s next for smarter, more connected electronics manufacturing - Part 2The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.” Process complexity drives demand for feed-forward between silos with computational models ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized. “We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says. So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,” notes Niesing. Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 1What’s next for smarter, more connected electronics manufacturing - Part 3Paul Doe, SEMI