EDA

Electronic designers demand greater integration densities and faster data transfer rates to meet the growing performance requirements of AI/ML, 5G/6G networks and autonomous vehicles as these technologies have outpaced the capabilities of any single chip.

Anna Fontanelli, Monozukuri’s founder and CEO, is an expert in deep-submicron silicon technology and design tools shares her view on the state of Moore’s Law and challenges surrounding 2.5D integration, 3D chip stacking & advanced packaging, as well as the chip design industry’s startup environment.

SEMICON Europa, SEMICON West, SEMICON Japan, & SEMICON Taiwan welcome back exhibitors and visitors to show floors starting in mid-November as four of SEMI’s seven flagship events gather visionaries and industry leaders to explore the latest semiconductor trends and innovations by the end of 2021.

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at the technological forefront in incorporating ML techniques in its chip design products. I spoke with Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital Signoff Group, about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. Teng also offers advice on how engineering students can calibrate their education to prepare to work with this transformative technology and urges them to have fun in the process. Smith: How is ML changing the EDA industry? Teng: ML is changing EDA for the better in many ways. It’s more difficult than ever to design chips, and ML is helping by overcoming the complexity, size and technology interdependencies. At the same time, ML is helping our own engineers solve certain classes of EDA algorithm, tool, and flow/solution challenges so that we can deliver even better EDA tools to our user base. The benefits can include reducing runtime, increasing quality of results, and being better equipped to manage vast complexity and data. Also, and maybe even more significant, is the potential boost to user and team productivity, where engineers have more time to focus on high-value problems because they no longer need to spend time on managing overwhelming volumes of data and details that can be easily automated. Smith: What is the potential impact ML can have on semiconductor design? Teng: ML technology can be leveraged in several ways to improve EDA tool performance and engineering team productivity. For example, we initially applied ML to applications such as formal verification, simulation regressions, analog circuit design, and PCB design. We targeted ML toward specific algorithms that processed lots of data to sharpen and speed decision-making. Then we started to look at digital implementation flows that combine multiple steps with multiple decisions in a recipe, especially for chip implementation where the more efficient use of engineering knowledge can make a substantial difference in the chip’s resulting power, performance and area (PPA). These flows present more challenges and require different ML and optimization techniques since the data points are expensive to create and the volume of data is huge. But flow optimization offers the largest rewards for companies investing in data collection and analysis to improve their operations and product quality. By using ML to improve the implementation flow, our users are seeing up to 20% better PPA and 10x improved productivity in developing data center CPUs and AI engines, automotive sensor processing SoCs, and mobile devices. Smith: What is the cloud’s role in the evolution of ML in EDA? Teng: More ML usage means there will be an inevitable surge in compute demand resources, and engineers need the ability to scale in parallel. The cloud provides engineers with the best opportunity to scale computing resources without facing procurement limitations. The cloud also allows engineers to use task-specific compute and ML accelerators and capitalize on distributed computing innovations that leverage the cloud for greater design flexibility and availability. Smith: You have written that you see Moore’s Law accelerating. How does ML fit into this? Teng: We see the rapid adoption of new process technologies as the biggest trend surrounding Moore’s Law right now. ML technology in EDA will help speed tool certification processes, process design kit (PDK) development and other deliverables aimed at creating and improving customer support through all stages of the process lifecycle. This is a virtuous circle, and it’s expanding beyond hardware design and optimization to also include software. Today’s ML functionality works on the abstraction of register transfer level (RTL), optimizing the implementation and verification flows. ML will soon enable use of a higher abstraction of describing the target systems, exploring architectural options and optimizing across hardware and software partitioning. Smith: What advice would you give engineering students who are studying ML with the goal of becoming an electrical engineer? Teng: With the rapid pace of technology development, things are changing constantly. I’d absolutely encourage students to look at ML because ML isn’t going away — its growth is only going to accelerate from here. I’d also suggest that students look more broadly at computational mathematics because that’s foundational for ML. There are many, many opportunities to apply ML to real-world applications that will make a significant impact when it comes to optimizing computational software. Most important, students should explore and have fun while doing it. About Chin-Chi Teng Chin-Chi Teng has served as Senior Vice President and General Manager of the Digital and Signoff Group (DSG) since 2018. Prior to this role, Teng held senior leadership positions in research and development in digital implementation. Teng joined Cadence in 2002 via the acquisition of Silicon Perspective Corporation and subsequently led various research and development groups. He brought deep technical knowledge and more than 20 years of industry and academic experience to his role as leader of the IC Digital group. Teng holds a BS in electrical engineering from the National Taiwan University and an MS and Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He holds seven patents and has written many EDA papers, several deep learning papers, and the book Electrothermal Analysis of VLSI Systems. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Emerging applications powered by 5G and artificial intelligence (AI) are expected to be a boon to the semiconductor industry, but only once chipmakers overcome a key challenge: Architecting chips that meet the exacting performance, power consumption, size and cost requirements of devices for mid- to high-end applications. One technology – heterogeneous integration – promises to meet these demands and help drive future leaps in semiconductor innovation in the post-Moore era. To help the industry better grasp the technology challenges and business opportunities associated with deploying highly integrated chip and packaging technologies, SEMI and AI on Chip Taiwan Alliance recently gathered industry leaders from organizations including ASE, Unimicron, Dialog Semiconductor, Cadence and AITA to discuss technology trends and the vital importance of building a cross-industry exchange platform to advance next-generation manufacturing processes critical to heterogeneous integration. Following are key takeaways from the forum, Heterogeneous Integration Enables 5G and AI. Overcoming Heterogeneous Integration Technology Challenges Key to Advances in Taiwan High-End Semiconductor Manufacturing The introduction of the Heterogeneous Integration Roadmap (HIR) by the International Technology Roadmap for Semiconductors team in 2016 was an important first step, Dr. C.P. Hung, Vice President of ASE Group, noted in his opening remarks. The HIR is designed to stimulate pre-competitive collaboration to advance heterogeneous integration technology development and accelerate electronics innovation. The roadmap provides a long-term vision for the electronics industry, identifying future technology requirements and potential solutions. Today, the HIR working group focuses on high-performance computing (HPC), 5G and other leading-edge technologies.Dr. Hung predicted that heterogenous integration will reshape traditional collaborations between the semiconductor ecosystem and supply chain in order to clear I/O bottlenecks that hamstring high-performance applications. The retooled industry connections will also need to enable high I/O pin counts, ultra-thin devices, and high-frequency signal shields. In an important step forward, the chip industry today is developing a platform that enhances wafer-level advanced packaging services and deepens cooperation with Oversea Assembly and Testing (OSAT) and substrate supply chain partners. Overcoming the current limits of IC substrates – the connection between IC chips the PCB – is one key for heterogeneous integration technology to flourish, said Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron. He noted that the industry must tackle limits to PCB thickness, substrate density, fine pitch and automation to meet the needs of high-end packaging customers. Another barrier the industry must be surmounted is to make the currently inscrutable confidentiality requirements for patents of foreign materials – key to improving chip yields – easier to access and understand for substrate engineers. Chen said partnerships across the entire industry will be necessary to break through this and other technology breakthroughs. Supply Chain and Cross-Border Ecosystem to Strengthen Partnerships for Further DevelopmentTaiwan has long invested heavily in advancing semiconductor manufacturing and application engineering technologies to become a top global chipmaking hub and, in the process, has been behind significant leaps in optimizing chip functionality, said Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany). With its semiconductor manufacturing prowess, Taiwan can also play a central role in maturing advanced heterogeneous integration packaging technology while managing development costs by partnering with its international supply chain community to overcome technical challenges more effectively, Liu said. The region can also help forge partnerships, even among competitors, to build the ecosystem essential for heterogeneous integration technology to shine.EDA tools will be critical in understanding and resolving heterogeneous integration technical issues since IC substrate, packaging and chip design all pose interdisciplinary engineering challenges, said Julian Sun, Product Marketing Director at Cadence. To help the industry navigate these challenges, Cadence has launched intelligent system design products – solutions that address a wide range of design problems with semiconductor nanometers, micrometers on packaging and testing, and PCB level micro/millimeters to Pin/Pitch, I/O models, and thermals and electricity. By supporting various technical designs, Cadence helps customers shorten the design cycle to strengthen design quality and reduce costs.Sun also pointed to the vital importance of overcoming the significant challenge of designing silicon interposers for heterogeneous integration. Today’s EDA tools are capable of optimizing the design of complex structures including 5GAiP and HBM and are instrumental in aiding Taiwan’s semiconductor ecosystem players to quickly adapt to shifts in the evolving heterogeneous integration market.Heterogeneous Integration Enables 5G and AI speakers (L-R): Julian Sun, Product Marketing Director at Cadence, Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron, Dr. C.P. Hung, Vice President of ASE Group, Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany), Dr. Shih-Chieh Chang, AITA Executive Secretary Designing AI chips is particularly difficult as semiconductor makers struggle with high costs and low yields, said Dr. Shih-Chieh Chang, AITA’s Executive Secretary. That’s why the chip industry now uses FPGAs for small-volume production of AI chips, which makes it easier to improve manufacturing yield through redundant design. For its part, AITA has formed a special interest group (SIG) to help form connections among the chip industry, academia and research institutes. The association’s goal is to build a platform for mass production of AI chips.To get involved in SEMI Taiwan Heterogeneous Integration related events, please contact Ula Huang, outreach senior specialist, at [email protected] Fang is a coordinator and Ashley Huang is a specialist in marketing and public relations at SEMI Taiwan.

The microelectronics industry is entering the era of Cloud Engineering Simulation to slash the costs and risks of new technology development and speed time-to-market in spaces like semiconductors, MEMS sensors, RF front ends, biomedical and driverless cars. In the run-up to SEMICON Europa, 12-15 November, 2019, in Munich, Germany, SEMI spoke with Ian Campbell, CEO of OnScale, about the new paradigm of Cloud Engineering Simulation. Campbell shared his views ahead of the SMART Design Forum, 14 November, 2019, 14:30 to 17:00, in Hall B1, TechARENA 1 at SEMICON Europa. Registration is open. Join the forum to meet experts from OnScale and other key industry influencers. Attendance is free of charge for all SEMICON Europa visitors.SEMI: How did your adventure with OnScale start?Campbell: I’m an engineer. When I was still in high school, I took a night class at Nashville Tech to learn AutoCAD R14, and I’ve been designing and engineering things ever since. I was introduced to Desktop Simulation in my bachelors of mechanical engineering program and used many types of simulation tools for massive design studies at the Aerospace Systems Design Lab at Georgia Tech. I’m a simulation junkie.I started my first Silicon Valley high-tech company, NextInput, in 2012 with Dr. Ryan Diestelhorst (now VP of Strategy at OnScale), to commercialize new ForceTouch and 3D Touch technologies based on our patented MEMS force sensors. At NextInput, we bought hundreds of thousands of dollars of engineering software, but were always frustrated by slow, inaccurate engineering simulation results. We dreamed about running massive simulations on Cloud Supercomputers and creating true Digital Prototypes that could replace costly, time-consuming, and risky physical prototypes.When I got the chance to join the team that became OnScale in 2017, I jumped at the opportunity. At OnScale, we took engineering simulation solvers that had been developed for the U.S. military to run on U.S. Department of Defense and DARPA supercomputers and built a cloud supercomputer platform on Amazon Web Services to run the solvers. The net-net is the world’s first on-demand, infinitely scalable Cloud Engineering Simulation platform. Now, we routinely run massive multi-billion degree of freedom simulations for Fortune 100 companies, including many from the semiconductor and MEMS industries. Since our business model is to charge per core-hour for simulations, the incredible capability we built is cost-effective and available to small startups as well. SEMI: How is the semiconductor design ecosystem evolving? How is Cloud Engineering Simulation applied to semiconductor and design industries?Campbell: The entire industry is experiencing a massive acceleration in product launch cycles and increased competition. New markets like IoT and 5G are reducing semi/MEMS product cycles from years to months. That, in turn, puts enormous pressure on semiconductor and MEMS designers. Missing a key product introduction like a flagship smartphone launch can literally make or break a company.A reliance on traditional engineering methods – schematic capture and layout of a chip, taping out (physically prototyping the chip), performing engineering validation on an e-bench, qualifying the chip (or not qualifying it and going back to the drawing board), and finally launching mass production – is no longer sustainable from a competitive perspective.Instead, market-leading firms are turning to Cloud Engineering Simulation and Digital Prototypes to explore massive design spaces, find optimum designs that beat the competition in every KPI (size, power, performance), and digitally qualify designs before ever cutting silicon, ensuring that designs are robust over their intended operating environments and performance envelopes. Large thermal analysis of a chip on a circuit board executed quickly on the OnScale Cloud Simulation Platform SEMI: Can you give us an example? Campbell: A great example is thermal analysis. Thermal effects have always had huge impacts on MEMS device performance and, more recently, they are beginning to impact performance of next-gen semiconductors, especially GaN power electronics for electric vehicles (EVs).Conducting a full system-level thermal analysis of something like an EV power management system – a power IC in a package, on a board, in an enclosure, under various loading conditions – has been a challenge from a simulation complexity perspective (degrees of freedom) and from a parametric sweep perspective (running hundreds or thousands of simulations to optimize chip placement, routing, etc.). To run these sets of simulations using legacy desktop simulation would take weeks, perhaps even a month or more. To run these massive simulations in parallel on cloud supercomputers using OnScale takes days or even hours.Our customers routinely run very large simulation studies on OnScale Cloud for thermal simulations, RF filter simulations, MEMS simulations, packaging simulations (what we call Digital Qualification), and many more use cases.SEMI: What’s one of your strategic objectives for 2020? Campbell: For 2020, we’re doubling down on MEMS and semi simulation capabilities. We will be launching additional solver capabilities like EM that will be critical in our strategic markets like 5G. We will also be launching a Cloud API so that engineers can integrate OnScale directly into their existing engineering workflows (e.g. MATLAB or EDA/CAD tools) with just a few Python commands.SEMI: Can you share one prediction for the future of semiconductor design solutions? share?Campbell: I think we will continue to see MEMS and semi designers push the envelope and bring smaller, more performant, more cost-effective solutions to market. I’d like to see more highly cost-effective flexible semi/MEMS designs come to market to enable next-gen IoT and IIoT applications. I’d also like to see more biomedical applications – biomems, microfluidics, and labs on a chip for all sorts of life-enhancing applications.SEMI: What are your expectations regarding the SMART Design Forum at SEMICON Europa 2019 in Munich? Campbell: I’m looking forward to getting back to my roots in MEMS/semi design and chatting with other designers about the future of engineering and the future of semi! Ian Campbell is a twice venture-backed Silicon Valley CEO and expert in MEMS sensors, semiconductor technology, and engineering software. Most recently, Ian co-founded OnScale, a Cloud Engineering Simulation startup backed by Intel Capital and Google’s Gradient Ventures. OnScale is revolutionizing engineering by combining world-class multiphysics solvers with Cloud supercomputers, machine learning, and artificial intelligence. Prior to co-founding OnScale, Campbell served as founder and CEO of NextInput, where he led the startup through multiple rounds of funding – totaling $12 million and an additional $4 million in research contracts with government and industry partners – and built a world-class team of engineers and scientists who developed 3D Touch and ForceTouch technologies for smartphones, wearables, industrial, and automotive interface applications. He also secured the first major smartphone OEM design wins in Asia. Campbell earned his B.S. in mechanical engineering from Middle Tennessee State University, and his MSAE in aerospace engineering and MBA from Georgia Institute of Technology.Serena Brischetto is senior manager, marketing and communications, at SEMI Europe.

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West, co-located with SEMICON West, July 9-11 at the Moscone Center in San Francisco.ESD Alliance: For years now, the assumption is that each new chip design is more complex than the last. Why are the latest SoC designs even more complex than before?Taheri: New SoC devices for mobile phones, automobiles, intelligent edge nodes, big data compute and storage are adopting artificial intelligence and machine learning technologies. This is driving new compute, data flow, as well as memory architectures that are bandwidth-limited and some require photonic interfaces.One common denominator in present SoC design are the numerous blocks of IP. On average, over 85% of these blocks are reused. It’s cost-prohibitive to make these chips over and over again with new IP. According to some estimates, 90% of IP used in an SoC design by 2025 will be reused – only 10% is new technologies. That 10% is significant.ESD Alliance: How so?Taheri: Complex new technologies including flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs such as NVIDIA’s Xavier and Apple’s A12 use and reuse design IP at the architectural level.New technologies mean new materials and new processes. Single nanometer process nodes require specialized new IP that needs to be simulated and analyzed down to the nanometer and atomic levels.ESD Alliance: Does the atomic level changes the design equation?Taheri: Yes, it does. Designers need to be able to simulate at the atomic level and understand properties of these materials, and how they behave in at-process and at-device levels. They need be able to simulate the material's nanometer geometries, how molecules behave and how they interact for device operations. When they put together a process and a device, they need to know how the pieces behave and simulate before production.In other words, they run quite a few design experiments and quite a bit of simulation before they finalize the circuits and devices to silicon to save money.ESD Alliance: It’s obvious design automation will continue to have a vital role in design.Taheri: Yes, absolutely. Design technology co-optimization (DTCO) using TCAD solutions and proven design IP are needed to address the span from architecture to device and process physics. The importance of simulation, emulation and design technology co-optimization, along with fully verified and proven IP for SoC design, cannot be overstated. As designers generate devices and processors, they take that up to circuit-level simulation and high-level simulation, schematic capture, extractions and back annotation. They can go from atoms to simulating systems to the ability to do that under the same umbrella in order to get better chips, better yield and lower cost.Taheri’s talk Next Generation of SoC Design: From Atoms to Systems will be part of the Meet the Experts More than Moore session Tuesday, July 9, at 11:30 a.m. at the ES Design West SMART Design Pavilion. SEMICON West attendees are invited to Moscone Center’s South Hall to learn more about electronic system and semiconductor design and its links to the electronic product manufacturing and supply chain. Register for ES Design West or SEMICON West.Babak Taheri is Silvaco’s CTO and EVP of products, has more than 25 years of design experience. His current role managing Silvaco’s Technology CAD (TCAD), electronic design automation (EDA) and IP product divisions makes him an expert on what’s needed for the design of next-generation system-on-chips (SoCs). Previously, he was the CEO and president of IBT working with investors, private equity firms, and startups on M A, technology and business diligence. Babak received his Ph.D. in biomedical engineering from the University of California Davis with Bachelor of Science degrees in Electrical Engineering and Computer Science and Neurosciences. He has published more than 20 articles and holds 28 issued patents.Nanette Collins is a public relations representative for the Electronic System Design Alliance.

Would you buy your next hotdog in parts, from un-coordinated suppliers? For example: Get the bun from a baker, the sausage from a butcher, mustard and/or ketchup and veggies from the nearest supermarket? If yes, you may find the sausage being too small, the veggies too big for the bun, and, when you finally finished adding mustard/ketchup and start eating, you may “enjoy” a cold sausage on a soggy bun!This “hotdog example” is just a very simple way to highlight the advantages of a well-coordinated semiconductor supply chain. What may be a few dollars and cents wasted in this hotdog purchase, can become millions of dollars lost to delays and inefficiencies during the roll-out of a new electronic system.Complexity is Increasing the ChallengeThe very innovative semiconductor industry is continuing to develop more complete and complex building blocks for electronic system solutions, with the intent of making our customers’ lives easier. However, every new technology takes increasingly more time for technical and business interfaces to mature before all the semiconductor supply chain members can serve customers in a smooth, efficient and cost-effective manner. In particular, coordination between design and manufacturing has always turned out to be in the critical path.SEMI, the manufacturers’ trade organization, and the Electronic System Design (ESD) Alliance, representing electronic design automation (EDA) tools vendors, developers of intellectual property (IP = ready-made building blocks for ICs) and IC design service providers, both recognized these challenges. Late in 2018, these two industry organizations decided to jointly address this painful, costly and often a very frustrating, yet critical path and became Strategic Association Partners, The goal is to establish a well-coordinated semiconductor supply chain.To make the value propositions of this partnership highly visible and demonstrate the first joint accomplishments, SEMI’s well-known SEMICON West conference and, in its first year, ES Design West, will be conveniently co-located in San Francisco’s Moscone Center from July 9 to 11, 2019. The synchronized schedules and geographic proximity of these events not only outlines the multi-faceted interdependence of manufacturing and design but encourages and enables conference attendees to do, what previously would have been viewed as “forming cross-border relationships.” It’s a new word now — please join the path to success and expand your network!Navigating SEMICON West and ES Design WestJust in case you are not yet planning to come to San Francisco early July, please check the Agendas-at-a-Glance for SEMICON West and ES Design West, to see how broad and valuable these parallel conferences are for your business. In addition, every customer, partner and semiconductor industry supplier can, from July 9 –11, walk from one conference section to the other, arrange face-to-face meetings, in dedicated meeting rooms, with representatives from both camps and discuss, from the first project planning step to the final production ramp-up, the many topics that need to be coordinated across parts or the entire supply chain to minimize delays and/or cost over-runs.Who Will Lead the Discussions?Conference attendees can, in addition to meeting many important supply chain partners face-to-face, hear about the latest technologies and market trends from key executives in our industry. Featured speakers are: David Pellerin, Head of Global Business Development, Amazon Web Services Lisa Su, President, and CEO, AMD Gary Dickerson, President, and CEO, Applied Materials Laurent Le Faucheur, Principal Engineer, Digital Signal Processing and Machine Learning, Arm, Ltd. Renee St. Amant, Ph.D., Research Engineer in Emerging Technologies and US Innovator of the Year, ARM Dean Kamen, President DEKA Research Development, Founder First and First Global Jeffrey Welser, Ph.D., Vice President and Lab Director, IBM Research-Almaden Dean Drako, President and CEO, IC Manage, Inc. Oreste Donzella, Sr. VP Chief Marketing Officer, KLA Corporation Prakash Narain, President, and CEO, Real Intent, Inc. Aart de Geus, Chairman, and Co-CEO, Synopsys, Inc. Manish Pandy, Fellow, Synopsys, Inc. Nate Baxter, General Manager, Development and Production Group, TEL US Like in previous years, SEMICON West and ES Design West offer a range of special features, addressing Smart Manufacturing, Smart Transportation, Smart MedTech and Smart Workforce development in dedicated pavilions as well as an AI Design Forum. Also, the many exhibitors from both camps will give conference attendees convenient opportunities to get to know new supply chain partners and/or refresh long-term business relationships. Search for the exhibitors you want to meet early July here. Questions to Ask for a Well-Coordinated Semiconductor Supply ChainIf I may, I would like to ask my many friends in the manufacturing camp to spend some time in the ES Design West section and ask the exhibitors a few questions, like: What can you do to get me to profit faster? To reduce development and unit cost? To improve yield, product quality, and reliability? When can you visit my team to discuss how your company can contribute to our goals?Vice versa, I would like to encourage my friends in the design camp to spend time in the SEMICON West section and ask exhibitors what their companies offer. When talking to manufacturers of IC, passive components or circuit boards, assembly and test houses, please ask very specific questions like: How can we help you reduce iterations between you and your customers? How can we help to improve IC test programs? How can we increase the throughput of your manufacturing equipment? How can we apply machine learning (ML) and Artificial Intelligence (AI) to minimize equipment downtime, improve yields and/or shorten production ramp-up?I can assure you that you’ll not only win great friends “across the border” but will be very impressed by the expertise you’ll find in the other camp and the willingness for and benefits of cross-border cooperation.I look forward to meeting you at SEMICON West and ES Design West. Also, if your schedule allows, mark your calendars for the June 12 MEPTEC Luncheon at SEMI in Milpitas, June 18 for the GSA’s Silicon Summit in Santa Clara and June 25 to 27 for the IMAPS SiP Conference in Monterey, CA. Hope to see you at one or all of these important events!Article originally published in 3D InCites. Herb Reiter is president of eda 2 asic Consulting.

New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require.Yet MEMS design also presents some specialized challenges, such as a strong coupling between fabrication technology and design. Complex physical structures that exhibit non-linear behavior, custom packaging requirements, and a final product that requires integration with surrounding CMOS circuitry are just a few examples. What’s more, there is a lack of standardized processes and process validation in MEMS design ecosystems. Pressure Sensor (Courtesy: X-FAB) As with other products based on MEMS technology, designers must increasingly customize pressure sensors for higher performance – sensitivity and linearity, in this case – while decreasing their package size. Designers can accomplish the task by studying sensor performance and manufacturability using computer models prior to fabrication. This can ensure that the sensor meets its required specifications while simultaneously reducing manufacturing cycles and cost.The Power of CollaborationThis is where strong collaboration among EDA providers, MEMS technologists and designers delivers tangible benefits. EDA providers and MEMS foundries can collectively help MEMS designers to incorporate foundry process constraints into their designs.In the semiconductor industry, first-pass successful silicon relies on standardized manufacturing processes, thorough technology characterization, accurate model generation, established simulation and verification, and extensive reuse of proven design blocks. In the MEMS world, where processes and products are developed concurrently, and processes change with every product, is it possible to adopt standardized processes, design methodologies, and tools that enable efficient reuse of existing technology and design knowledge? The challenge lies in maintaining the flexibility to optimize products for a diverse array of requirements. The ideal design platform should ease sharing of technology and design data between the foundry and its customers, enabling two-way collaborative development and allowing foundry technologists to easily perform a feasibility assessment of a customer’s project. This approach offers important benefits, allowing designers to explore and evaluate the suitability of a foundry’s process technology in their unique application. It also supports accurate prediction of device performance prior to fabrication and reduces costly build-and-test cycles. Combining standardized manufacturing processes, MEMS process design kits (PDKs), and a proven design flow are the starting point for development of manufacturing-ready designs.A Real-Life Example using Pressure SensorsAn EDA company, Coventor (a Lam Research company), along with MEMS foundry partner X-FAB, collaborated to develop a PDK that would ensure that manufacturing constraints are automatically considered early in their design process. The design flow is based upon an X-FAB fabrication platform that supports multiple process options for the manufacturing of absolute and relative MEMS pressure sensors. The PDK is a “golden container” for all the process and material characteristics of the silicon membrane and substrate, glass, passivation layers, and piezoresistive components. It enforces material properties and guarantees their correct implementation during the simulation. It also includes a component library containing ready-to-use, 3D parameterized devices (such as membranes and resistors), all pre-designed with foundry-supported materials to support their respective design rules. The components are readily partitioned for optimized meshing and simulation, saving design and simulation time. Figure 1: The elements and design flow of the PDK designed by Coventor and X-FAB. (Courtesy: Coventor)Designers can use components from the library to create a custom design — which might include different membrane shapes and sizes, and resistors of varying shape, size and position — to simulate the impact of different technology variants (such as resistor doping profiles, membrane and substrate thickness, glass material properties, and passivation schemes). This allows them to anticipate the effect of these design changes on sensor sensitivity for varying pressure and temperature regimes.Extensive validation of the pressure sensor design platform is currently underway. So far, the simulations have exhibited very good correlation to actual device measurements across a range of pressure and temperature conditions, including predictions of non-linear behavior for various pressure sensor designs. At the same time, the simulation accounts for mechanical membrane properties and piezoresistivity. With this type of design platform, a foundry can provide guidelines to help customers select both the fab technology and design features that lead to an optimal design solution. Figure 2: Simulation results depicting mechanical displacement in a pressure sensor design (Courtesy: X-FAB) Let’s Face the Next Challenges…A complete design platform for MEMS must eventually include not only MEMS device design, but system integration functions, such as the application-specific integrated circuit (ASIC) design and packaging/assembly of the product. In addition to the design verification that the PDK provides, additional partnerships among foundries, integrated device manufacturers (IDMs), research centers, equipment suppliers, and EDA vendors will help to define requirements and solutions that address every level of design and production. These might include tasks such as describing standardized material properties and process specifications, creating accurate foundry-proven design models, and defining requirements for system-level simulation. In the future, PDK simulations might even include up to tape-out and physical verification. To learn more about this collaborative PDK development work, please click here for the whitepaper.Christine Dufour, MEMS PDK Program Manager, CoventorChristine Dufour is the MEMS PDK program manager at Coventor. She has more than 20 years of experience in the semiconductor industry, leading process design kit development for BiCMOS and CMOS processes at several major semiconductor companies. Ms. Dufour has also worked as a product manager in the RF design environment area. In addition to her extensive experience in MEMS PDK development, she is an expert in all aspects of MEMS design flow and design tool development. Ms. Dufour received an engineering degree at Technological University of Compiegne.For more information on Coventor, a Lam Research Company, visit: https://www.coventor.com/ Viraja Sharma, Development Engineer, MEMS Simulation Design, X-FABViraja Sharma is a development engineer for MEMS Simulation Design at X-FAB. Her work involves the design and simulation of MEMS inertial and pressure sensors. Prior to her tenure at X-FAB, Ms. Sharma performed similar duties for other semiconductor companies. She received her Master of Science degree in Micro and Nano Systems from TU Chemnitz, where she studied MEMS and micro technologies.For more information on X-FAB, visit: https://www.xfab.comCoventor and X-FAB are members of SEMI-MEMS Sensors Industry Group that connects the MEMS and sensors supply network, enabling members to address common industry challenges and explore new markets. 1 Market research firm Yole Développement predicts that MEMS pressure sensors alone will become a $2 billion market by 2023. See: https://yole-i-micronews-com.osu.eu-west 2.outscale.com/uploads/2019/01/YD18018_MEMS_Pressure_Sensor_Market_Yole_Developpement_2018_Sample.pdf