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The future of the semiconductor industry began to blossom recently in Seoul, South Korea as young, innovative minds teased out secrets to electronics manufacturing and their path to enter the industry one day. Twenty-seven middle schoolers gathered in early August at Yonsei University for SEMI High Tech U (HTU), the worldwide SEMI program that introduces students to science, engineering, technology and math (STEM) careers over three days of hands-on activities and experiential learning. Since 2001, HTU has reached some 8,000 students in nine countries.Semiconductor giants including Applied Materials, KLA, Lam Research and Dongjin Semichem were key teachers as representatives from the companies gave theoretical and practical lectures to pique the students’ interest in STEM educations and careers. The speakers, all experts in microelectronics, surveyed microchips and solar cells, mathematical and scientific experimentation, engineering design and the inner workings of semiconductor manufacturing before the students broke off into teams for lessons largely of their own making. Fine-tuning a wooden contraption – a Statapult – to hurl a ball as far as possible might not sound like the stuff of microelectronics, but it drew on the type of problem-solving skills and creativity the students will need to thrive in the semiconductor industry. Student teams made adjustments to the levers of miniature catapults, then tested the throwing power of the devices. After the ball tosses, they reconvened as a class to share lessons in how they calibrated their catapults for a longer tossing distance and ways they could improve the devices’ performance. Students also took tours of two very different semiconductor manufacturing settings – one virtual and the other real. The young learners donned virtual reality headsets for a simulated walk-through of Applied Materials (the tour was sponsored by the company), then slipped on bunny suits for a tour of Yonsei University's BIT micro fab and a close-up look of how semiconductors are made.But it was the ever-popular Human Calculator game that inspired the greatest thrill as students dove deep into technology. During the exercise, they converted numbers into binary and then traced the digits through a series of gates in an electronic circuit, an exercise requiring careful team communication and concentration to generate the right outputs. The students surprised SEMI Korea employees and instructors, and themselves, by completing the exercise with record speed. Their time: less than two seconds.Human resources managers from sponsor companies were on hand to give the middle school students a head start in their careers with lessons in resume writing and career management. In mock interviews, the students honed their interviewing skills. And in meetings with SEMI High Tech U alumni they learned how their predecessors worked their way into semiconductor industry and their focus of study in college.To be sure, the day was rich in details about working in the microelectronics industry. But did it meet the students’ expectations? In a survey before the event, the more than two dozen students, on average, rated their knowledge of microelectronics at 4.5 on a scale of 1 to 10, a score that jumped to 7.7 after completing HTU. Their favorite module? No surprise: Engineering Design. In this exercise, the students designed a carrier for six 12-ounce beverage cans using only decidedly low-tech materials such as strings, rubber bands and wooden boards. Their innovations were studies in high creativity and ingenuity – just the type of imaginations the semiconductor industry needs. SEMI Korea has offered SEMI HTU since 2011. This year, various other career development programs such as semiconductor manufacturing tutorials and mentoring are planned as SEMI Korea continues to sow the seeds of the next generation of industry workers. Jaegwan Shim is a marketing specialist at SEMI Korea.
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Post-Conference Report: SEMI Heterogeneous Integration SummitDemand for high-performance computing (HPC) chips is exploding. These super-speedy chips are critical for data centers and cloud computing infrastructures to support new performance-hungry technologies such as artificial intelligence (AI) and 5G. The challenge is for the devices and their multi-core architectures to couple high bandwidth density with low latency and high energy efficiency. Heterogenous integration offers a potential answer as an advanced packaging technology designed to meet these skyrocketing performance demands on HPC chips and open the door to a whole new world of 3D integrated circuits (ICs).So important are 3D ICs that Intel and TSMC representatives speaking at the recent Heterogeneous Integration Summit hosted by SEMI Taiwan in Taipei declared that the packaging technology will all but dictate the future of the industry. All told, 12 speakers from government, academia and a broad range of leading international companies from sectors including advanced packaging, design, manufacturing, silicon photonics, equipment and materials shared forward-looking strategies, the latest technologies and potential heterogeneous integration market opportunities. Koushik Banerjee, vice president, TMG, Assembly, and Test Technology Integration, at Intel pointed out that using heterogeneous integration for a single SiP (system-in-package) will deliver what the industry has long wanted by enabling multiple process nodes, more diverse silicon IP (intellectual property) and chip functionality, and chips that pair low energy with high frequency. Intel plans to announce its first Forveros 3D packaging product combining a 10nm HPC chiplet with a low-energy 22nm base die and stacked with memory on top. When asked about the future of advanced packaging technology, Banerjee said it will be very much about the combination of Foveros and its very own Embedded Multi-Die Interconnect Bridge (EMIB).For its part, TSMC, will continue to upgrade its CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated Fan-out) and other 2.5D IC production solutions while developing 3D chip stacking technology such as SoIC and WoW (wafer-on-wafer). TSMC is ushering in a new age of 3D IC packaging, said Marvin Liao, Vice President, Backend Technology and Service Division, at TSMC. The company’s SoIC is based on Chip-on-Wafer concept, with the flexibility to support one-to-many or different process nodes, whereas its WoW integrates two wafers with solid yields that could be used for products of the same size or manufactured with mature process technology.Speakers also included representatives from ATOTECH, Lam Research, SPIL, Sigurd, Cadence, Grand Process Technology, ITRI (Industrial Technology Research Institute), Industrial Development Bureau, and Lee San-Liang, Distinguished Professor, Department of Electronic and Computer Engineering at National Taiwan University of Science and Technology all shared their perspectives on equipment, materials, and testing and how different industry value chains might contribute to the development of heterogeneous integration technology.Expected to be a key driver of the next wave of semiconductors, heterogeneous integration and related technologies – including 3D IC, FOWLP (Fan-out wafer-level packaging) / FOPLP (Fan-out panel-level packaging), silicon photonics, Micro LED, compound semiconductor, automated optical inspection and SLT (system level testing) – will be a key focus at SEMICON Taiwan 2019, September 18 to 20 in Taipei. The Heterogeneous Integration Innovation Zone – along with featured international programs such as SiP Global Summit, Strategic Materials Conference, the Smart Data Summit and the Smart Automotive Summit – will gather key industry players to reveal the latest technology breakthroughs and market trends.Emmy Yi is a senior marketing specialist at SEMI Taiwan.
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According to market research and strategy consulting firm Yole Développement (Yole), the total market size of MEMS, sensors and actuators will double from $48 billion in 2018 to $93 billion in 2024.[i] The consumer market will continue to drive volume, with applications such as smartphones making up for in volume what they lack in average selling price (ASP). Stronger demand in automotive, biomedical/health, industrial, and voice-first applications (such as smart speakers) will support this upward trajectory. With so much growth ahead of us, how will the design and manufacture of MEMS keep pace with industry demand for higher levels of innovation and integration, lower cost and lower power, smaller footprints, and faster design cycles — all while meeting acceptable price points?We turned to a handful of MEMS manufacturing experts from SEMI-MSIG who will join us at SEMICON West 2019, July 9-11 at the Moscone Center in San Francisco, to explore the complexities of keeping pace with market demand for MEMS over the next decade.Address the Design GapMentor GM, ICDS Division Greg Lebsack and SoftMEMS President Mary Ann Maher see tremendous progress in the manufacturing supply chain for MEMS. At the same time, they acknowledge the significant gap that still exists in design capability for creating the billions of interconnected sensors required for future applications. Greg and Mary Ann will dive into the standards, ecosystem requirements and collaborative design solutions that will allow the micro-sensors industry to meet demand for next-generation wearables, Internet of Things (IoT) products and medical devices.Get Collaborative with Greg and Mary Ann: Addressing the Design Gap to Enable Next Generation Sensor-Based Products, SEMICON West, TechTALKS South, Thursday, July 11, 2019, 10:35-11:00 a.m. Register today.Get to a Really Big NumberFrom thousands of sensors and actuators in a single airplane to hundreds in a single car or a piece of factory equipment to the twenty-plus that ship in each of the hundreds of millions of the world’s smartphones, we aren’t even close to reaching the saturation point for these intelligent devices. SPTS Technologies EVP GM David Butler isn’t living on the Spaceship Enterprise (or the Millenium Falcon, come to think of it) when he says that we are going to get to a trillion sensors. It is going to happen. The questions are: how and when?Connect with David: Enabling the Age of a Trillion Sensors, SEMICON West, TechTALKS South, Thursday, July 11, 2019, 11:00-11:25 a.m. Register today.Shift to Automotive-GradeDemand for optical sensing technologies such as LIDAR is shifting sensor manufacturing requirements from consumer- to automotive-grade, with its enhanced lifetimes, temperature cycling and higher performance specifications. To meet demand, manufacturers are turning to wafer-level processing, since it complies with the hermetic sealing and dew-point control required for the more rigorous automotive-grade applications. EV Group Business Development Director Thomas Uhrmann, Ph.D., will provide an overview of the steps for manufacturing optical elements, including integration with CMOS circuitry, as he offers a window into the future of automotive packaging for sensors.Tune in with Thomas: Future Manufacturing Requirements for Automotive and Photonics Sensing, SEMICON West, TechTALKS South, Thursday, July 11, 2019, 11:25-11:50 a.m. Register today. Measure Twice, Cut OnceFaster time-to-market, improved device yield, and greater productivity in high-volume manufacturing are increasingly critical requirements for MEMS manufacturers. When a single manufacturing error can cost hundreds of thousands if not a million or more dollars — as well as months of development time — designers can save both time and cost by employing an integrated approach to MEMS design. Lam Research Sr. Director of Strategic Marketing David Haynes will explain how simulation, verification and process modeling can address MEMS-specific engineering challenges such as multi-physics interactions, process variations, MEMS + IC integration, and MEMS + package interaction. Using the right tools before committing to actual fabrication can make or break a project.Get Conceptual (and Practical) with David: Enabling Better MEMS from Concept to High-Volume Production, SEMICON West, TechTALKS South, Thursday, July 11, 2019, 11:50 a.m.-12:15 p.m. Register today.Navigate a Dynamic Foundry LandscapeWe’re still living in a one product-one process world when it comes to MEMS manufacturing. This makes bringing a new device to market both time-consuming and expensive. These challenges aside, the functional capabilities of MEMS, combined with small-footprint and low-power options, have made MEMS increasingly popular. How are market dynamics in MEMS manufacturing evolving to accommodate both demand for high-volume, lower-cost products such as MEMS microphones as well as high-value, lower-volume products such as biomedical devices, IoT products and industrial sensors? Rogue Valley Microdevices Founder CEO Jessica Gomez will explain how foundry consolidation through acquisition, collaboration with other ecosystem players, and specialization in vertical markets such as biomedical or optical are some of the approaches that are transforming the MEMS foundry landscape.Join the Evolution with Jessica: Consolidation, Collaboration, Specialization: How Will MEMS Fabs Manage Changing Dynamics, TechTALKS Stage South, Thursday, July 11, 2019, 12:15-12:40 p.m. Register today.i“Status of the MEMS Industry report,” Yole Développement (Yole), 2019 Edition.Maria Vetrano is a public relations consultant at SEMI.
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New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require.Yet MEMS design also presents some specialized challenges, such as a strong coupling between fabrication technology and design. Complex physical structures that exhibit non-linear behavior, custom packaging requirements, and a final product that requires integration with surrounding CMOS circuitry are just a few examples. What’s more, there is a lack of standardized processes and process validation in MEMS design ecosystems. Pressure Sensor (Courtesy: X-FAB) As with other products based on MEMS technology, designers must increasingly customize pressure sensors for higher performance – sensitivity and linearity, in this case – while decreasing their package size. Designers can accomplish the task by studying sensor performance and manufacturability using computer models prior to fabrication. This can ensure that the sensor meets its required specifications while simultaneously reducing manufacturing cycles and cost.The Power of CollaborationThis is where strong collaboration among EDA providers, MEMS technologists and designers delivers tangible benefits. EDA providers and MEMS foundries can collectively help MEMS designers to incorporate foundry process constraints into their designs.In the semiconductor industry, first-pass successful silicon relies on standardized manufacturing processes, thorough technology characterization, accurate model generation, established simulation and verification, and extensive reuse of proven design blocks. In the MEMS world, where processes and products are developed concurrently, and processes change with every product, is it possible to adopt standardized processes, design methodologies, and tools that enable efficient reuse of existing technology and design knowledge? The challenge lies in maintaining the flexibility to optimize products for a diverse array of requirements. The ideal design platform should ease sharing of technology and design data between the foundry and its customers, enabling two-way collaborative development and allowing foundry technologists to easily perform a feasibility assessment of a customer’s project. This approach offers important benefits, allowing designers to explore and evaluate the suitability of a foundry’s process technology in their unique application. It also supports accurate prediction of device performance prior to fabrication and reduces costly build-and-test cycles. Combining standardized manufacturing processes, MEMS process design kits (PDKs), and a proven design flow are the starting point for development of manufacturing-ready designs.A Real-Life Example using Pressure SensorsAn EDA company, Coventor (a Lam Research company), along with MEMS foundry partner X-FAB, collaborated to develop a PDK that would ensure that manufacturing constraints are automatically considered early in their design process. The design flow is based upon an X-FAB fabrication platform that supports multiple process options for the manufacturing of absolute and relative MEMS pressure sensors. The PDK is a “golden container” for all the process and material characteristics of the silicon membrane and substrate, glass, passivation layers, and piezoresistive components. It enforces material properties and guarantees their correct implementation during the simulation. It also includes a component library containing ready-to-use, 3D parameterized devices (such as membranes and resistors), all pre-designed with foundry-supported materials to support their respective design rules. The components are readily partitioned for optimized meshing and simulation, saving design and simulation time. Figure 1: The elements and design flow of the PDK designed by Coventor and X-FAB. (Courtesy: Coventor)Designers can use components from the library to create a custom design — which might include different membrane shapes and sizes, and resistors of varying shape, size and position — to simulate the impact of different technology variants (such as resistor doping profiles, membrane and substrate thickness, glass material properties, and passivation schemes). This allows them to anticipate the effect of these design changes on sensor sensitivity for varying pressure and temperature regimes.Extensive validation of the pressure sensor design platform is currently underway. So far, the simulations have exhibited very good correlation to actual device measurements across a range of pressure and temperature conditions, including predictions of non-linear behavior for various pressure sensor designs. At the same time, the simulation accounts for mechanical membrane properties and piezoresistivity. With this type of design platform, a foundry can provide guidelines to help customers select both the fab technology and design features that lead to an optimal design solution. Figure 2: Simulation results depicting mechanical displacement in a pressure sensor design (Courtesy: X-FAB) Let’s Face the Next Challenges…A complete design platform for MEMS must eventually include not only MEMS device design, but system integration functions, such as the application-specific integrated circuit (ASIC) design and packaging/assembly of the product. In addition to the design verification that the PDK provides, additional partnerships among foundries, integrated device manufacturers (IDMs), research centers, equipment suppliers, and EDA vendors will help to define requirements and solutions that address every level of design and production. These might include tasks such as describing standardized material properties and process specifications, creating accurate foundry-proven design models, and defining requirements for system-level simulation. In the future, PDK simulations might even include up to tape-out and physical verification. To learn more about this collaborative PDK development work, please click here for the whitepaper.Christine Dufour, MEMS PDK Program Manager, CoventorChristine Dufour is the MEMS PDK program manager at Coventor. She has more than 20 years of experience in the semiconductor industry, leading process design kit development for BiCMOS and CMOS processes at several major semiconductor companies. Ms. Dufour has also worked as a product manager in the RF design environment area. In addition to her extensive experience in MEMS PDK development, she is an expert in all aspects of MEMS design flow and design tool development. Ms. Dufour received an engineering degree at Technological University of Compiegne.For more information on Coventor, a Lam Research Company, visit: https://www.coventor.com/ Viraja Sharma, Development Engineer, MEMS Simulation Design, X-FABViraja Sharma is a development engineer for MEMS Simulation Design at X-FAB. Her work involves the design and simulation of MEMS inertial and pressure sensors. Prior to her tenure at X-FAB, Ms. Sharma performed similar duties for other semiconductor companies. She received her Master of Science degree in Micro and Nano Systems from TU Chemnitz, where she studied MEMS and micro technologies.For more information on X-FAB, visit: https://www.xfab.comCoventor and X-FAB are members of SEMI-MEMS Sensors Industry Group that connects the MEMS and sensors supply network, enabling members to address common industry challenges and explore new markets. 1 Market research firm Yole Développement predicts that MEMS pressure sensors alone will become a $2 billion market by 2023. See: https://yole-i-micronews-com.osu.eu-west 2.outscale.com/uploads/2019/01/YD18018_MEMS_Pressure_Sensor_Market_Yole_Developpement_2018_Sample.pdf
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SEMI has long promoted the industry collaboration that has contributed to the rise of the smart digital world we live in today. A world where data is being generated continuously by systems, gadgets, and sensors around us – often referred to as the Internet of Things (IoT). In our personal lives, most of us have smartphones, smart watches, smart TVs and smart cars, and we live in smart homes and smart cities generating huge amounts of data.In the work world, data and analytics are now influencing almost every industry including healthcare, government, financial services, construction and transportation. This data has the potential to transform our lives and make our world even smarter – if we can communicate and process this data, and use it to come up with actionable recommendations or actions. Artificial Intelligence (AI) and Machine Learning (ML) techniques have generated much excitement precisely because they offer us ways to realize the full value of data by harnessing it and transforming it into active intelligence.Data-intensive technologies are required to store, communicate and analyze data. And it all starts with innovation in microelectronics chips and systems spanning processors, memory, sensors, radios and other devices, presenting a huge opportunity to producers of these technologies. However, with Moore's Law beginning to slow, technology paths and innovation options are diverging. Companies must swiftly assess these options in order to develop competitive offerings. But the technological complexity and divergence makes it increasingly expensive or even unaffordable for many companies to track and pursue these options.The good news is that cost-effective early assessment is possible through pre-competitive collaboration that can produce new and often unexpected cross-disciplinary insights by overcoming traditional silos in industry and academia. Unfortunately, important collaborative industry platforms, such as the International Technology Roadmap for Semiconductors (ITRS), have folded, opening a collaboration gap in the global microelectronics ecosystem.As part of its mission to help companies connect, collaborate, and innovate, SEMI has built a collaborative, cross-supply-chain platform – the Strategic Innovation Platform (SIP). The goal is to provide early and comprehensive assessment of future technologies that are five to eight years away from commercialization. The assessment identifies not just technical barriers but also manufacturing and supply-chain constraints to implementing new technologies. SIP brings together the entire microelectronics ecosystem including strategic technology thought leaders, subject matter experts, technology and application developers, academia, researchers, start-ups and government. With more than 2,100-member companies spread across the global electronics manufacturing supply chain, SEMI is uniquely positioned to enable this critical collaboration. Award-Winning First ProjectThe inaugural SIP project assessed key drivers of future technologies. A key finding was that fast, efficient interconnects between devices and components are critical to the system performance important to customers and users, implying that system-level optimization is required. For data-intensive applications, interconnects have emerged as a key bottleneck for both performance and power in various circuits and systems in part because the slowing of Moore’s Law has decelerated advances in individual device performance, and in part because systems are becoming more complex, requiring heterogeneous integration.To address this challenge, SIP brought together industry experts from ASE Inc., Dow Chemical, Lam Research, Qualcomm and Xilinx to assess the future impact of interconnects for data-intensive applications. SEMI also involved Stanford University professors to collaborate on modeling and simulation. Through this unique cross-disciplinary collaboration, SIP developed a realistic model to evaluate the system-level performance of single-chip systems, as well as multi-chip systems – including traditional 2D packages, high-performance 2.5D systems that use interposers, and futuristic 3D systems. SIP also explored supply chain challenges in business continuity, manufacturability, Environment, Health and Safety (EHS) and the regulatory environment. SEMI worked with a broad range of industry partners to ensure that the model parameters accurately reflected realities on the design and factory floors to ensure usable results. Experimentation has become ever more expensive, with one industry player reporting that “it costs us $100 million to do a good experimental evaluation.” Accurate models can go a long way toward reducing the cost of technology assessment. The SIP collaboration produced key quantifiable insights including comparisons that highlight the benefits and limitations of various materials being explored for future interconnects, and of architectures under consideration for future data-intensive applications. For example, the current workhorse for artificial intelligence (AI) platforms – 2.5D technology – delivers a 4X improvement over 2D packaging but falls short of providing the orders-of-magnitude improvement that future AI/ML applications may require. These findings enable the industry to begin to identify ways to optimize 2.5D architectures, transition to 3D heterogeneous integration for performance-critical applications in the medium term, and to eventually evaluate new paradigms such as neuromorphic and quantum. The project findings were presented late last year in the form of two research papers at Electronics System-Integration Technology Conferences (ESTC) and International Microelectronics Assembly and Packaging Society (IMAPS) recently. One received the “Best Paper of the Session” award at IMAPS – a recognition that affirms the power of a collaborative platform such as SIP to produce valuable insights to address the growing technology complexity within the microelectronics industry. The microelectronics industry is on the cusp of a historic inflection point, where it could fuel the rise of emerging applications in AI/ML and IoT, and can grow into a trillion dollar industry over the next several years. More importantly, the industry is poised to help solve some of society’s most complex problems in areas including healthy living, climate change and transportation. No company can do this alone, and pre-competitive platforms such as SIP are key both to accelerating innovation through cross-disciplinary collaboration, and to reducing costs for individual companies. Please contact Tom Salmon at [email protected] or Pushkar Apte at [email protected] for more details and to get involved in future projects.Tom Salmon is vice president of Collaborative Technology Platforms. Pushkar Apte is a strategic technology advisor at SEMI.
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SEMI-MEMS Sensors Industry Group (MSIG) welcomed a global group of industry executives to its 14th annual MEMS Sensors Executive Congress (MSEC), October 29-30, 2018 in Napa, Calif. MEMS and sensors represent a robust sector of the electronic industry. Analyst firm Yole Développement expects the global market for MEMS and sensors to double in the next five years, reaching $100B by 2023, spurred by growth of autonomous mobility products such as Internet of Things (IoT) devices, autonomous cars, fitness and healthcare wearables, and agricultural sensors.“From drones that navigate any terrain in all lighting conditions, robo-taxis that ‘smell’ cigarette smoke, and sensors that monitor animal welfare and food safety, MSEC speakers shared inventive use cases representing new opportunities for MEMS and sensors suppliers,” said Carmelo Sansone, director, MEMS Sensors Industry Group. “Our keynote speakers spurred attendees to collaborate for the greater good. MITRE Corp. cybersecurity expert Cynthia Wright exhorted attendees to proactively address cybersecurity. DARPA Microsystems Technology Office (MTO) program manager Ron Polcawich invited participation in a rapid innovation and production concept that could dramatically speed design cycles for new MEMS. They exemplify the cross-pollination among commercial industry, government and academia that will continue to advance MEMS and sensors.”Getting serious about cybersecurityMITRE cybersecurity expert Cynthia Wright opened MSEC 2018 with a keynote on cybersecurity, alerting attendees to a topic that few in the industry have explored in-depth — but to which they need to pay attention.“Billions of connected mobile devices democratize knowledge, diversity and boost economies, and accelerate innovation by connecting humans to one another and to our environments,” said Wright. “At the same time, they easily create huge networks that carry operationally and personally sensitive data.”Because MEMS and sensors are deeply embedded into this vast array of connected devices, industry needs to get involved now or risk potentially grave consequences, claimed Wright. “From the destruction of critical infrastructure, cyberattacks on life-critical medical devices such as insulin pumps and heart monitors, and intrusions on autonomous vehicle safety systems, MEMS and sensors suppliers have a responsibility to help improve cybersecurity of connected devices,” she added.Allaying the potential fears of a roomful of suppliers envisioning complete redesigns of their products, Wright said that not every device requires the same level of security, and suppliers can make a difference with even “minor tweaks.” Wright suggested encryption at the edge and process authentication. She also gave MSEC attendees a list of design precepts: Build it in. Don’t bolt it on — Design your device with security in mind instead of retrofitting it after-the-fact to realize the most elegant design. Beware of shadow IT — You can’t protect what you don’t know about. Consider physical asset security; software/sensor-guided decision-making; personal or operational data collection; and key process control. Realize your points of vulnerability — because MEMS and sensors are susceptible to spoofing. Learn from cyberattacks of the past — even if they have not been tied directly to MEMS/sensors. Understand IoT software — Realizing that IoT software acts on what the hardware tells it, pay attention to altered sensor data that can lead to altered system performance. When asked about the role of US government regulation on the security of connected devices, Wright acknowledged that Europe has more restrictive cybersecurity guidelines than the US.“At the same time, it does not make sense to have two different approaches to cybersecurity of devices. US suppliers who implement more security measures can sell to both markets and to other parts of the world.”If she could leave MSEC attendees with a closing thought, it might be that companies “don’t need to put a firewall on a toaster.”“Not every chip has to be secure-foundry secure, but it would be nice if even 10% could hit that mark,” added Wright.Rapid Innovation through CollaborationIC designers typically enjoy three to four design cycles in a calendar year, leading to swift advancement of electronics over subsequent years.Designers in the MEMS community, however, generally have access to one design cycle or less per year, and typical time-to-market is four years for a new product. That slow fabrication pace has hindered deployment of innovative MEMS designs — and it’s something that MSEC closing keynote speaker, Ron Polcawich, program manager, DARPA MTO, would like to change.Polcawich’s vision of government collaboration with industry and academia spawned the investigational Rapid Innovation through Production MEMS (RIPM) Workshop, which Polcawich and his team held in May 2018. During his keynote, Polcawich shared lessons learned from the workshop while inviting MSEC attendees to get involved.Before RIPM can become a program, Polcawich knows it will require definition. What would a program concept look like? What is the best way to articulate the potential benefits to the MEMS community, and what additional inputs would be needed?“This is a daunting challenge from a program planning perspective,” said Polcawich. “In developing RIPM, we realized that we needed representatives from the entire MEMS ecosystem – integrated device manufacturers, or IDMs, equipment suppliers, foundries, and materials’ providers — to literally come to the table to tackle a common goal. Given the potential for the MEMS industry at large to benefit from rapid innovation and production, we hoped that competitors would realize that leveraging established MEMS processes could deliver significant benefits over the historically entrenched approach: one product, one process.”Polcawich believes that MEMS suppliers might relinquish the one product, one process paradigm if they knew that their IP were secure.“While technical challenges to realizing RIPM abound, we knew that we could tap the MEMS industry’s vast knowledge base to address them,” he said. “IP protection is an equally complex issue, and one that may bear a range of approaches. One model could ensure that each IDM owns their IP while the foundry owns the process technology, which it licenses to other companies through process development kits. In addition to speeding innovation, it also provides new revenue sources for the industry.”Polcawich sees RIPM as a win-win for both commercial industry and for the DoD. Speeding design-to-deployment of new MEMS devices could open new and larger markets to MEMS suppliers. It could also support greater product-line diversification and new revenue streams for foundries and other ecosystem members. The DoD could tap new MEMS devices for strategically important applications like tactical radios, unmanned aircraft systems such as drones, and image autofocus for cameras. Polcawich encouraged SEMI-MSIG members to get involved by emailing his group: [email protected] Hall of Fame MembersThree new industry leaders joined the SEMI-MSIG Hall of Fame, first established in 2011 as a means of honoring those who have made a substantial contribution to SEMI-MSIG. Selected by members of the Governing Council, 2018 Hall of Fame inductees include: Michelle Bourke, strategic marketing director, Customer Support Business Group, Lam Research Eric Pabo, business development manager, MEMS, EV Group Yoshio Sekiguchi, senior strategic advisor, TDK InvenSense Technology Showcase WinnerMSEC recognizes the latest advancements in applications enabled by MEMS and sensors — including those demonstrated by entrepreneurs competing in the Technology Showcase. Selected by a committee of industry experts, five finalists did their best to impress attendees with their technical approach and go-to-market strategies. The 2018 Technology Showcase winner, Alertgy, presented a biosensor-based wristband device that provides non-invasive, real-time blood glucose monitoring for people with type 2 diabetes, which affects more than 20 million Americans and hundreds of millions more worldwide. MSEC 2018 Sponsors MSEC 2019 Location and DatesMSEC 2019 will take place October 22-24, 2019, at the Coronado Island Marriott Resort Spa in Coronado, Calif., just minutes from downtown San Diego.For more information on MSEC 2019 and other SEMI-MSIG events and programs, please follow @MEMSgroup on Twitter, visit MSIG at SEMI and subscribe to SEMI’s weekly newsletter, SEMI Global Update.Maria Vetrano is a public relations consultant at SEMI.
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U.S.-China Trade War Heats UpThe U.S. Trade Representative (USTR) yesterday released a 25 percent tariff on $16 billion in imports from China, including 29 tariff lines that represent the heart of the semiconductor industry. These tariff lines include semiconductor products such as machines and spare parts used to make, wafers, flat panel displays, masks and chips, and will cost SEMI’s 400 U.S. members an estimated more than $500 million annually in additional duties.SEMI, along with hundreds of companies, including Lam Research and KLA-Tencor, submitted written comments, requesting the removal of tariff lines from the proposed list. SEMI also testified on behalf of the semiconductor industry, joining more than 80 other companies, including Applied Materials, in opposing the duties before an U.S. government interagency panel in late July.This trade action is on top of the already imposed $34 billion U.S. tariff list, which will cost SEMI’s U.S. members tens of millions of dollars annually. In the coming days, USTR will publish details on how U.S. companies can request the exclusion of products from the $16 billion tariff list, much as it did for the first round of $34 billion.In a swift retaliation, China announced a 25 percent tariff on $16 billion in U.S. exports, including products vital to semiconductor manufacturing such as chemicals, test equipment and other parts. Both U.S. and China tariffs will take effect on August 23.The new tariffs come as China considers tariffs on $60 billion of U.S. imports, and the U.S. weighs additional duties on $200 billion of Chinese imports – a wave that would inflict even deeper damage on the U.S. semiconductor industry. This latest round of U.S. tariffs would cover goods used in microelectronics manufacturing, including chemicals, glass products and spare parts. SEMI will testify against the $200 billion tariff list later this month. If your company expects to be impacted by the proposed tariffs on $200 billion worth of goods, please contact SEMI staff.SEMI stands firm in its belief that none of the tariffs address U.S. concerns over China’s trade practices. Instead, they harm companies in the semiconductor supply chain by increasing business costs, introducing uncertainty and stifling innovation. SEMI will continue to engage with policymakers as both the U.S. and China $16 billion tariff lists are implemented. We will also be evaluating the products covered by the $200 billion U.S. list and the $60 billion Chinese list as both are further considered. We encourage members to review these lists to determine impact on their companies. For more information, please contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].
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Did you miss the SEMI International Standards Reception at SEMICON West 2018? Not to worry, here are the highlights.SEMI honored two Standards industry leaders for their outstanding accomplishments in developing Standards for the electronics and related industries.Two awards were given recognizing the efforts of each member. The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.James Amano, Sr. Dr. International Standards, opened the reception with a few words. He noted that the total number of published SEMI Standards is nearing 1000, and that these documents serve as the backbone of modern day semiconductor manufacturing. SEMI president and CEO Ajit Manocha, speaking at the SEMI International Standards Reception at SEMICON West. Ajit Manocha, President and CEO of SEMI, reminisced how he was an active Standards Member, and how much he got out of SEMI Standards as a young engineer at Bell Labs. He passionately emphasized that SEMI Standards remain critical in this era of new materials and disruptive architectures and processes, calling them the "oxygen of the industry."Laura Nguyen is coordinator, International Standards, at SEMI.
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What’s next for smarter, more connected electronics manufacturing - Part 3 The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco. While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development. “People don’t think of research and development as the first place to automate, but it’s where applying our digitization and simulation has first had impact,” says David Fried, Coventor vice president of Computational Products. He noted that insertion is easier in the lab than in the fab. Technology at 10nm and beyond is now so complex that companies at the leading edge must use process modeling to understand the effect of process variation on their designs. Learning cycles can now be accelerated during development by simulating 10,000 digital wafers instead of running 25 actual wafers during screening, Fried says. Applying structured analysis and machine learning to the data simplifies optimization across the 500 or more interrelated process steps. Coventor has recently introduced a statistical analysis package that aids the design and analysis of process variation experiments by using large volumes of data from its models. Fried says these models are next being used to accelerate the yield ramp in manufacturing. Digital simulation also could speed development of high-mix, lower value products While digital twins are best known for their use in complex, high value products like jet engines, the simulation technology could also enable the electronic manufacturing services (EMS) sector to reduce the time, cost and risk of developing its high mix of products. “The EMS sector’s use of digital twins will be vital for it to smooth the move of CAD/CAM digital design data for so many different products into manufacturing, and to accelerate validation testing of designs and products by doing more of it in the virtual world,” says Dan Gamota, vice president of Engineering and Technical Services at Jabil. Gamota also highlights the push for traceability from the automotive and healthcare markets, where the digital models could be used to quickly assure that the design was built exactly as specified. “In the past year, traceability has evolved from just ‘nice to have’ to ‘how to achieve,’” he adds. “Companies are expecting it, but aren’t willing to accept the cost and risk of doing it alone. We need the community to discuss realistic implementations, identify the most critical elements and bring together the ecosystem partners to build baseline reference architectures for key digital building blocks. The community also needs to assure the reliable flow of data among the electronic manufacturing segments from semiconductor to OSAT to EMS.” Predictive maintenance and virtual metrology applications could mature in next few years While predictive maintenance initially seemed a likely early application of machine learning in factories, it remains a challenge for the electronics sector. “The difficulty is that it’s not clear where to get the most bang for the buck,” says Tom Ho, president of BISTel America, noting that it may make the most sense to track the failure performance of a single expensive part, like an electrostatic chuck, since predicting the failure performance of a whole complex system like an etcher is much harder. “Collecting enough data from all failure types, including especially the rare events, is difficult unless you have a long history of a lot of tools,” adds Doug Suerich, PEER Group product evangelist. “The gain from collecting performance information from many tools across the industry could be big, but many companies still need to overcome concerns around exposing their IP.” Another big opportunity for prediction is virtual metrology – predicting the wafer outcome from the process or sensor data with enough accuracy to replace the physical metrology. “Virtual metrology is improving, and since metrology can be slow and expensive, any reduction could mean a huge potential savings,” says Suerich. “But it is still seen as too scary for many companies. Two to three years from now, companies will expand the practice from lower risk areas into processes that require more confidence in the results.” Moving beyond prediction to automated control needs digital models Once the results are predicted, the model can be used to control or automatically optimize a process and enable the system to learn by itself, usually by reinforcement learning on a digital model. The model can then independently make adjustments to optimize the manufacturing process. “Automated process development is getting close now. Instead of smart guys turning the knobs, deep learning is automating the smart tuning,” says Suerich, suggesting the industry could see widespread adoption in as little as two to three years. This type of machine learning needs a good digital model, and masses of data for learning. One approach uses human experts to build a physics-based model of the clearly understood parts of the process, then turns to deep machine learning to optimize the lesser-understood variables. The alternative, the data-first approach, runs a computer algorithm to suggest the solution purely from data, without human input, and then relies on the human to evaluate the usefulness of the results. Modeling digital twins of wafers could enable automated process control, chamber matching, and fleet matching, says Fried. If every wafer had its own virtual twin with all the upstream metrology and structural information needed to make equipment control decisions, it could feed forward that information to enable the seamless transition from one step in the process to another based on understanding their complex interrelationships. This could potentially improve uniformity across wafers and equipment, and reduce the need for metrology, he argues. Moving metrology sensors into the chamber will also require model-based algorithms to enable dynamic process control in close to real time, says Fried. These algorithms will be needed to acquire, parse, and process the data at high speed, and then to choose how to adjust the controls. “There will be a model behind collecting and interpreting the metrology data,” he notes. “That’s a really rich vein for improvements in process control.” “The end goal is to collect equipment data in real time, analyze it with AI, and send back controls to optimize manufacturing processes,” Jabil’s Gamota says. “This requires a robust architecture for communication between equipment and consistent formats for data collection and analysis. But the cost and complexity of this heavy lifting is too great for any one company to do alone. We need a consensus-based architecture for ingesting, analyzing and acting on the data.” SEMI tests data transfer protocols, benchmarks best practices SEMI is launching a smart data project to identify the various data transfer protocols needed for inter-company communications. The project will feature a proof-of-concept model in a development fab to produce verifiable results so SEMI can better understand how different approaches meet member needs. SEMI’s smart manufacturing technology communities and the Fab Owners Alliance are also benchmarking current smart manufacturing practices in the microelectronics industry to help SEMI members better understand the path forward and potential return on investment. Speakers over all three days at SEMICON West addressing these issues include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org. What’s next for smarter, more connected electronics manufacturing - Part 1 What’s next for smarter, more connected electronics manufacturing - Part 2 Paula Doe, SEMI
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With artificial intelligence (AI) rapidly evolving, look for applications like voice recognition and image recognition to get more efficient, more affordable, and far more common in a variety of products over the next few years. This growth in applications will drive demand for new architectures that deliver the higher performance and lower power consumption required for widespread AI adoption. “The challenge for AI at the edge is to optimize the whole system-on-a-chip architecture and its components, all the way to semiconductor technology IP blocks, to process complex AI workloads quickly and at low power,” says Qualcomm Technologies Senior Director of Engineering Evgeni Gousev, who will provide an update on the progress of AI at the edge in a Data and AI program at SEMICON West, July 10-12 in San Francisco. Qualcomm Snapdragon 845 uses heterogeneous computing across the CPU, GPU, and DSP for power-efficient processing for constantly evolving AI models. Source: QualcommA system approach that optimizes across hardware, software, and algorithms is necessary to deliver the ultra-low power – to a sub 1-milliwatt level, low enough to enable always-on machine vision processing – for the usually energy-intensive AI computing. From the chip architecture perspective, processing AI workloads with the most appropriate engine, such as the CPU, GPU, and DSP with dedicated hardware acceleration, provides the best power efficiency – and flexibility for dealing with rapidly changing AI models and growing diversity of applications.“So far it’s been largely a brute force approach using conventional architectures and cloud-based infrastructure,” says Evgeni. “But we’re going to run out of brute force options, so future opportunities lie in developing innovative architectures, dedicated hardware, new algorithms, and new software. Innovation will be especially important for AI at the edge and applications requiring always-on functionality. Training is mostly in the cloud now, but in the near future it will start migrating to the device as the algorithms and hardware improve. AI at the edge will also remove some privacy concerns, an increasingly important issue for data collection and management.”Practical AI applications at the edge where resources are constrained run the gamut, spanning smartphones, drones, autonomous vehicles, virtual reality, augmented reality and smart home solutions such as connected cameras. “More AI on the edge will create a huge opportunity for the whole ecosystem – chip designers, semiconductor and device manufacturers, applications developers, and data and service providers. And it’s going to make a significant impact on the way we work, live, and interact with the world around us,” Evgeni said.Future generations of chips may need more disruptive systems-level change to handle high data volumes with low power A next-generation solution for handling the massive proliferation of AI data could be a nanotechnology system, such as the collaborative N3XT (Nano-Engineered Computing Systems Technology) project, led by H.S. Philip Wong and Subhasish Mitra at Stanford. “Even with next-generation scaling of transistors and new memory chips, the bottlenecks in moving data in and out of memory for processing will remain,” says Mitra, another speaker in the SEMICON West program. “The true benefits of nanotechnology will only come from new architectures enabled by nanosystems. One thing we are certain of is that massively more capable and more energy-efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.” Major improvement in handling high volumes of data with low high energy use will require system-level improvements, such as monolithic 3D integration of carbon nanotube transistors in the multi-campus N3XT chip research effort. Source: Stanford UniversityThat means carbon nanotube transistors for logic, high density non-volatile MRAM and ReRAM for memory, fine-grained monolithic 3D for integration, new architectures for computation immersed in memory, and new materials for heat removal. “The N3XT approach is key for the 1000X energy efficiency needed,” says Mitra.Researchers have demonstrated improvements in all these areas, including multiple hardware nanosystem prototypes targeting AI applications. The researchers have transferred multiple layers of as-grown carbon nanotubes to the target wafer to significantly improve CNT density and have also developed a low-power TiN/HfOx/Pt ReRAM. The low-temperature CNT and ReRAM processes enable multiple vertical layers to be grown on top of one another for ultra-dense and fine-grained monolithic 3D integration. Other speakers at the Data and AI TechXpot include Fram Akiki, VP Electronics, Siemens; Hariharan Ananthanarayanan, motion planning engineer, Osaro; and David Haynes, Sr. director, strategic marketing, Lam Research. See SEMICONWest.org.Paula Doe, SEMI
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