IoT

Terry Tsao, Global Chief Marketing Officer at SEMI and President of SEMI Taiwan, recently discussed technology trends with Young Liu, Chairman of Hon Hai Technology Group (Foxconn), as a prelude to SEMICON Taiwan’s five online forums.

A 500,000 ft2 (~47,000 m2) state-of-the-art cleanroom facility still towers as the largest U.S. high-technology investment in Vietnam 10 years after starting operations in Saigon High Tech Park in District 9, Ho Chi Minh City. The structure built by Intel Products Vietnam (IPV) on the back of a $1 billion investment is the largest assembly and test manufacturing facility (ATM) in the Intel assembly and test network. IPV turns out products that are helping power cutting-edge applications along with the next wave of semiconductor industry growth as it homes in on 5G, Internet of Things (IoT), desktop and mobile. And it has been a boon to the local economy, generating more than 5,000 high-skill jobs across a number of assembly and test disciplines since launching operations in 2010. It has also contributed to over US$37 billion in exports from 2010 to 2019, accounting for over 60% of Saigon High-Tech Park’s annual export values in 2019. With its vision “to create the future of Intel and Vietnam,” Intel continues to be a strong long-term partner in Vietnam. I recently spoke with Kim Huat (KH) Ooi, vice president of Manufacturing and Operations and General Manager at Intel Products Vietnam (IPV), about the facility’s vital role in Intel’s overall manufacturing operations, its support for the E E ecosystem in Ho Chi Minh City, and measures it has implemented to reduce the impact of the COVID-19 pandemic on the facility and protect employees. Ooi leads and manages the site to support Intel’s business in Vietnam. His responsibilities include overseeing factory operations and employee relations; enriching the Intel image and brand; building strategic relationships with communities, media, governments, and local authorities; and working with the industry ecosystem and government. IPV employees celebrate Intel’s 50th anniversary in 2018. Ng: How does IPV campus complement the rest of Intel manufacturing sites and be nearer your customers and supplier base?Ooi: Intel Vietnam is an important part of Intel’s manufacturing presence worldwide. IPV has been operating for nearly 14 years in Vietnam and has celebrated multiple milestones along the way. As a site, we have matured and grown over the years. In March this year, we celebrated a proud milestone – the rollout our 2 billionth unit – that reflects the value of IPV to Intel Corporation as these Made in Vietnam products support its customers worldwide. One of our philosophies is to work with and grow local ecosystems in countries where we operate. In Vietnam, Intel has been offering technical and managerial expertise to many local suppliers in Vietnam to help them expand their business and services to other foreign direct investment (FDI) customers in the industry. Over the past 10 years, Intel’s supplier list has grown 10-fold from 20 in 2010 to about 180 suppliers in 2020.In today’s world of fast-changing consumer preferences and expectations, we need to help drive development of the latest products and technologies to support strong customer demand and new product portfolios such as 5G. To support evolving customer requirements, our workforce frequently upgrades its skills to work on new products and technologies.Intel as a company is also evolving as it transforms from a PC-centric to a data-centric organization, a shift behind the more than US$70 billion in record revenue Intel posted in 2019. Intel’s data-centric business accounted for more than half of that revenue. IPV plays a key role in Intel’s expansion into new market segments.Ng: What are the key differentiating elements (talent, tax, technology, trade, EHS) in Vietnam that have been instrumental in supporting the E E ecosystem in Ho Chi Minh City?Ooi: Vietnam’s stable political environment and increasingly liberalized trade and investment policies are great for businesses. The region’s young, talented workforce is also one of many competitive advantages that enables it to attract foreign investment. Intel’s announcement to invest in Vietnam in 2006 has played a large part in helping put Vietnam on the map of the global IT and semiconductor industry. The news helped attract industry suppliers and service providers, bolstering Vietnam’s economy and creating jobs. The Vietnam government also figured prominently in sparking the boon by establishing the right policies and incentives to attract foreign investment. Since starting operations, we have seen significant improvements in infrastructure such as roads, ports, airports, broadband and power supply. Vietnam’s standing in the global business community is even stronger today after the government successfully combatted the COVID-19 pandemic early on and introduced policies to help businesses restart operations. We expect all these factors to continue to make Vietnam an attractive relocation target for companies around the world. Ho Chi Minh City People’s Committee Vice Chairman Mr. Duong Anh Duc (center) visited Intel Vietnam to tour the state-of-the-art facility. Ng: What measures have you implemented to reduce the impact of the COVID-19 pandemic and protect employees? Ooi: COVID-19 has taken the world by storm and changed the way we work and live in many ways. It has unquestionably pushed the world to build stronger partnerships among individuals, organizations, businesses and communities. Intel’s manufacturing operations have continued to run at full capacity. Since the outbreak emerged, we have strictly followed required Intel safety measures as well as the Vietnam’s health guidelines. We have also implemented a number of other safety initiatives and protocols to ensure our business runs smoothly. We’re doing everything possible to ensure the well-being of our employees and help them better respond to the pandemic.In coordination with our strategic partners, we have been donating thousands of Personal Protective Equipment (PPE) to the Fatherland Front and Department of Health (DoH) since early March. Recently, in partnership with AmCham Vietnam, Intel donated an imported ambulance with built-in essential equipment to the Ho Chi Minh City 115 Emergency Center. Intel has also teamed with Saigon Hi-Tech Park management to donate two ventilators and N95 masks to DoH.Our employees are also helping out by donating to Vietnam’s Coronavirus Donation Matching campaign. We collected US$13,000 from Intel employees and included matching funds from Intel Foundation to support three non-profit organizations (NPOs) – Saigon Children’s Charity, Kidspire Vietnam and Teach for Vietnam. All told, Intel Products Vietnam has donated US$200,000 to COVID-19 relief efforts, demonstrating our long-term commitment to communities where we operate. Intel Products Vietnam teamed with AmCham Vietnam to donate a fully equipped ambulance to Ho Chi Minh City’s 115 Emergency Center, demonstrating IPV’s long-term corporate social responsibility commitment. In early May, Intel unveiled our 2030 Corporate Strategy and goals to accelerate progress against the world’s critical challenges and help drive positive global outcomes. Part of our 2030 goals, our RISE (Responsible, Inclusive, Sustainable, Enabling) strategy focuses on the company’s commitment to its corporate social responsibility (CSR) initiatives to create a more responsible, inclusive, safe and sustainable world through technology and collective action. IPV has also committed to implementing the RISE strategy in Vietnam with local community initiatives and technology interventions. Bee Bee Ng is president of SEMI Southeast Asia.

Teck Khiong, WOI, senior manager of Factory Integration at Infineon Technologies Asia Pacific Pte Ltd, recently shared with me how the Infineon backend plant in Singapore has benefited from its journey to qualify for the lighthouse certification.WOI is driving Infinion smart manufacturing projects with a strong focus in the area of connect and control using IoT (Internet of Things) and analytics technologies. Ng: How did the Infineon backend plant in Singapore distinguish itself to qualify for lighthouse certification? WOI: The Infineon Singapore backend manufacturing plant is proud to be a Lighthouse Certified Smart Manufacturing site as part of the World Economic Forum’s (WEF) Fourth Industrial Revolution platform. Our Industry 4.0 (I4.0) implementation reduces labor costs by 30% and improves capital efficiency by 15%. We drove this successful digital transformation continuously investing in our people development and digital backbone.Of the many initiatives under our I4.0 Smart Factory platform, five were selected for WEF Lighthouse submission and certification. Digital foundation with integrated connectivity and workflow execution We implemented an Internet of Things (IoT) framework to connect machines to manufacturing system more than two years ago. The digitization of our Work-in-Progress (WIP) management systems provides full traceability and gives us better control of the four Ms (Man-Machine-Method-Material). Material handling and process automation We progressively deployed automated solutions starting six years ago using autonomous transport, robotic material management systems and automation of packing processes. This eliminated non-value touches in areas of WIP storage and retrieval. Advanced algorithms enabled WIP scheduling and dispatching As our product mix and volume grew in complexity, our advanced algorithms has enabled us to increase our machine uptime, thus reducing idle and set-up time. Manufacturing control tower Our control tower provides a real-time pulse of the entire manufacturing process, from machine efficiency to quality. The tower also improves data integrity and collaborative information sharing while issuing early-warning alerts that enable exception management and timely decisions. Running a global virtual factory Our Global Production Network deployments allows us to connect and manage a growing contract-manufacturing network in real time, with the same transparency, traceability and control as if the manufacturers are our internal sites.About Teck Khiong, WOITeck Khiong, WOI graduated from Loughborough University in the UK with a Master of Science degree in Computer Integrated Manufacturing (CIM). For more than 20 years he has delivered manufacturing IT solutions to global backend (assembly and test) semiconductor manufacturing, ranging from equipment, factory, process control, material handling automation and manufacturing execution systems (MES).

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).

SOI News spoke with Philippe Berger, CEO of chip silicon IP design / power management specialist Dolphin Design. Here’s what he told us about the work they’re doing on FD-SOI.SOI News (SN): Dolphin Design has been offering IP solutions for bulk technologies since 1995. What is your specialty, and why are you expanding your offering to FD-SOI? Philippe Berger (PB): Low power is part of Dolphin’s DNA since its inception and we work hand-in-hand with our customers to offer IPs that enable design of Energy Efficient SoCs while allowing our customers to focus their design activity on their core competencies. Technology scaling is no longer the only answer for the next generation of Energy Efficient SoCs. FD-SOI is one of the attractive technologies to address the upcoming energy efficiency challenges of next SoC generations, be it for IoT or automotive among several other applications. FD-SOI offers the opportunity to deal with a complex SoC architecture, made of multiple power domains, including RF, including digital processing with AI, and sensor interfaces, all together with a complete power management on a single chip. [caption id="attachment_33090" align="alignright" width="175"] Philippe Berger, CEO, Dolphin Design.[/caption] This is a great opportunity for Dolphin Design. Adding the deep expertise of our engineers in this technology and our turnkey design platforms, we can really help companies targeting FD-SOI implement easily, quickly and safely an energy-efficient SoC. We have two complementary offerings for companies that want to leverage FD-SOI: A sensor-centric MCU subsystem as a configurable RTL design platform. This design platform, named Chameleon, allows achieving the best energy efficiency by turning the CPU off whenever possible and by eliminating latency and congestions on the memory bus. A power management design platform as a total solution to implement fast and safely a power management network that leverages low power techniques to meet the energy efficiency targets. This design platform, named Spider, combines a library of configurable power management IPs, including adaptive body biasing, with a scalable power controller enabling to control power and clock activity autonomously, even with the CPU off. We can intervene at a very early stage of our customers’ design cycles thanks to our system-level utilities rather than just IP bits and pieces. The figure below describes the components of our Spider power management design platform which is a key turnkey solution to leverage some unique capabilities of FD-SOI, such as the capability to operate at a very low voltage with a decent speed or the capability to support as high as 5V input voltage. ASN: What’s driving that business? PB: The emergence of new IoT and automotive markets is driving the business forcing IC design teams to pursue tough objectives: zero power consumption in off modes while maximizing the performance in active modes at minimal power consumptions. Unfortunately, scaling down to the next technology node makes it even harder to reduce power in off modes and is an expensive choice - too expensive - for many applications to achieve the energy efficiency targets in active modes. As a result, design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the stringent requirements of the new IoT markets. This is particularly tricky in advanced IoT where near-sensor processing must be efficiently combined with RF connectivity, together with advanced power management. In addition, designers must confront the complexity of supporting high input voltage for interfacing with 4.2V/4.4V Li-Ion batteries or 5V USB charging mode that rely on 1.8V IO transistors. The need for solutions that enable to select fast and to implement safely the power management network which allows a seamless system-level integration while meeting power consumption targets in each SoC power mode -- that drives our business. SN: What do you see as the biggest benefits – and challenges – for designers moving to FD-SOI? PB: Its biggest benefit is its high integration capability. One of its key challenge is the ”so-far” relatively more complex design methodology that is required to take advantage of all FD-SOI characteristics, namely for example the biasing of the bulk to either reduce leakage or improve energy efficiency depending on working mode and technology centering. And ultimately, assuming the FD-SOI design flow is no longer a point of discussion, we need to get all designers “Thinking FD-SOI”. By that I mean to be aware of the breadth of FD-SOI advantages, so they are using it at every possible opportunity: in RF, in switches, in A/D converters (ADC) – in everything! FD-SOI’s double gate lets you think about more than decreasing noise and energy consumption. There are many opportunities for many blocks – especially analog. [bctt tweet="We need to get all designers “Thinking FD-SOI” so they’re using it at every possible opportunity: in RF, switches, ADC – in everything! Body biasing is usually thought of in the digital context, but it is also very useful in analog. – DolphinDesign CEO" username="soiconsortium"] SN: What does Dolphin Design offer designers moving to FD-SOI? PB: In order to ease these tasks, we developed the turnkey Spider platform based on power management IPs and system-level utilities. It speeds-up the design of energy efficient power management systems to weeks instead of months. Spider obviously exists in FD-SOI technology. It enables chip-architects to explore many power architectures and to select the best one to match the targeted PPA. It bridges the complexity gaps of designing fast and safely a power controller that can deal with numerous power domains and several operation modes for each domain and that can operate even when the CPU is off. Then, it bridges the gap between standard RTL and GDS flow, as it is able to generate the UPF backbone of the SoC. It offers a standardized and predictable power management flow, securing first silicon success. As an example, one of our key customers doing a ULP MCU shared that they have been able to design a complete power controller in less than one week instead of a couple of months. SN: You announced design kits with Adaptive Body Bias (ABB) solutions for GlobalFoundries’ 22FDX technology at the end of 2019. What challenges is that solving? PB: In the race for higher energy efficiency, digital designers face the impact of process variations. Chip designers have added margins all along their design to ensure the future chip will work fine whatever the technology centering after fabrication. Performance or size tradeoffs are necessary to cope with extreme variation cases (the so-called “corners”). At low voltage, SoC designers often use compensation techniques to limit the impact on the SoC energy efficiency. Through the control of transistor threshold voltage in FD-SOI technology, body biasing acts as a fantastic and automated control method to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the PPA trade-off up to 10x at low voltage. We have been cooperating with GlobalFoundries over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop. From standard-cell library to sign-off verification, our customers will continue to use their usual standard flow. For IoT on GF 22FDX, the design kits are available for production. For automotive, it will be in the next months. SN: Looking to the future, will there be a need for more application-specific FD-SOI IP? Where are the growth opportunities? Which ones will you be working on? PB: We anticipate new needs along the time as new applications will emerge in FD-SOI. We have a roadmap to enrich the catalog of power management IPs for addressing each market vertical with the most complete offering. But where we see the biggest growth for us is the growing adoption of power management IPs even by companies that were used to make voltage regulators on their own. Power management is no longer an issue of designing some good voltage regulators, like LDOs. Fabless companies face the challenge of dealing with the growing complexity of SoC power management network. It absorbs a significant portion of their design “energy”, in logic and in analog domains. They need to customize voltage regulators for each SoC and to maintain their design to keep them competitive. They also face the challenge of complex and sensitive power controller design. Finding the right design expertise to make such complex SoCs is a challenge in itself and in many cases power management complexity is the cause of a design respin. With the emergence of solutions such as Spider, that streamline and secure the selection and the implementation of the power management network, fabless companies start to question whether their core competency is power management IP design or if they can focus their design resources where they are the best at. The addition of body biasing into this picture makes it even more obvious for fabless companies that relying on a solid IP partner is a strong option. For Dolphin Design another opportunity for growth will mainly come from our capability to expand our offering for complementary design platforms for various FD flavors. We will communicate a lot in the coming months on our design platforms. We are also looking for diversification to other SoC functionalities. Processing is definitely an area in which we are significantly investing (MCU sub-systems and their associated DSPs), but energy harvesting and RF could also be good candidates in the future. SN: Dolphin Design is a member of the SOI Consortium. What do you see as the advantages of membership? PB: The 2019 Silicon Valley SOI Symposium was my first participation in an SOI Consortium event. [Note: you can get his full presentation here.] My first impression was good! I was positively surprised by the wide diversity of material shown. But really the key advantage was the opportunity to meet with so many different companies, all involved, from near or from far, with an FD-SOI tape out. It really helped me understand what I needed to put my teams to work on next!

The Compact Model Coalition (CMC) has selected Leti’s L-UTSOI as a standard model for FD-SOI in the industry. The CMC is a working group composed of the major semiconductor companies and is part of the Silicon Integration Initiative (Si2). The Si2 Compact Model Coalition announcement covers the approval and financial support of L-UTSOI. L-UTSOI is derived from the Leti-UTSOI compact model, which has been implemented in circuit-simulation software and used in industrial process design-kits for several years. Thierry Poiroux, head of CEA-Leti’s Simulation and Compact Model Laboratory, said the selection of L-UTSOI as a Si2-CMC standard model ensures that it will be supported as long CMC industry members use it. “This is of paramount importance for large chip makers who will use this model in the future,” he continued. “With a standard model, they are assured that a team of model developers is able to take care of the model improvements and/or bug fixes they need during the whole lifetime of their technology. It also positions CEA-Leti among the few compact-model developer teams able to develop and support a standard model.” The role of compact models Once a new or enhanced chip is designed, it must be simulated prior to entering the expensive manufacturing phase. This proof-of-concept step relies on compact models that are expressed through a set of equations implemented in a form ensuring accuracy, robustness and numerical efficiency. Such compact models are approved and supported by the standard-setting arm of Si2, the CMC, which is an international working group focused on standardizing SPICE device models. “As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer requests for model support as we continue to add value to their membership.” Standard models are developed by the world’s leading SPICE-model experts. They are used by designers working at the most advanced fabless semiconductor companies, foundries, and IDMs. Implemented in the industry’s top versions of circuit-simulation software and duly qualified, standard models give designers the assurance that their integrated circuits will perform according to the design specifications. Industry proven L-UTSOI was extensively proven by the industry and its standardization will ensure long-term access and maintenance in EDA tools for FD-SOI designers. Available to coalition members now, it will soon be implemented in major versions of circuit-simulation software, and its source code will be released publicly in June 2021. “CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.” As noted in Leti’s announcement (read the whole thing here), the FD-SOI transistor’s back-gate allows tuning of the device in a low-leakage and low-power operating regime or higher-performance operating regime. This unique capability offered by FD-SOI enables the fabrication of smaller, faster and denser chips than standard bulk CMOS technology. FD-SOI devices are widely used in wearable electronics, automobiles and IoT. Leti pioneered FD-SOI in 1992. Here at ASN we’ve been covering their FD-SOI compact model work for over a decade.

GlobalFoundries recently announced that its embedded magnetoresistive non-volatile memory (eMRAM) has entered production on the company’s 22nm FD-SOI (22FDX®) platform. (See the full press release here.) The company says this advanced embedded non-volatile memory on its FDX™ platform provides a cost-effective solution for low-power, non-volatile code and data storage applications. It is now working with several clients with multiple production tape-outs scheduled in 2020. GF heralds the announcement as a significant industry milestone, demonstrating the scalability of eMRAM as a cost-effective option at advanced process nodes for IoT, general-purpose microcontrollers, automotive, edge-AI, and other low-power applications. [caption id="attachment_31334" align="alignright" width="485"] (Courtesy: GlobalFoundries. Click to enlarge.)[/caption] “We continue our commitment to differentiate our FDX platform with robust, feature rich solutions that allow our clients to build innovative products for high performance and low power applications,” said Mike Hogan, senior vice president and general manager of Automotive and Industrial Multi-market at GlobalFoundries. “Our differentiated eMRAM, deployed on the industry’s most advanced FDX platform, delivers a unique combination of high performance RF, low power logic and integrated power management in an easy-to-integrate eMRAM solution that enables our clients to deliver a new generation of ultra-low power MCUs and connected IoT applications.”[bctt tweet="In production! @GlobalFoundries’ eMRAM on #22FDX FD-SOI replaces #eFlash for #IoT genpurpose #microcontrollers #automotive #edgeAI more. #lowpower #chipdesign #FDSOI" username="@soiconsortium"] [caption id="attachment_31330" align="alignleft" width="467"] (Courtesy: GlobalFoundries. Click to enlarge.)[/caption] Designed as a replacement for high-volume embedded NOR flash (eFlash), GF’s eMRAM allows designers to extend their existing IoT and microcontroller unit architectures to access the power and density benefits of technology nodes below 28nm. It is a highly versatile and robust embedded non-volatile memory (eNVM) that has passed five rigorous real-world solder reflow tests, and has demonstrated 100,000-cycle endurance and 10-year data retention across the -40°C to 125°C temperature range. The FDX eMRAM solution supports AEC-Q100 quality grade 2 designs, with development in process to support an AEC-Q100 quality grade 1 solution next year. [caption id="attachment_31331" align="alignright" width="280"] GF’s state-of-the-art 300mm production line at Fab 1 in Dresden, Germany, will support volume production of 22FDX with MRAM. (Courtesy: GlobalFoundries)[/caption] Custom design kits featuring drop-in, silicon validated MRAM macros ranging from 4 to 48 mega-bits, along with the option of MRAM built-in-self-test support is available today from GF and their design partners. eMRAM is a scalable feature that is expected to be available on both FinFET and future FDX platforms as a part of the company’s advanced eNVM roadmap. GF’s state-of-the-art 300mm production line at Fab 1 in Dresden, Germany, will support volume production of 22FDX with MRAM. Prior to this announcement, an excellent GF blog by David Lammers recapped GF's 2019 IEDM presentation of their eMRAM reliability data. You can read that here. It also provides a lot of interesting background information.

The chip design ecosystem finally has the book it’s been clamoring for: The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems. [bctt tweet="The FD-SOI Chip Design Book: Yes, It’s Finally Here!" username="@soiconsortium"] The editors (who have also contributed chapters) are Andreia Cathelin, Sylvain Clerc and Thierry DiGilio, all world experts from STMicroelectronics. As Cathelin and Clerc note in the introduction: “The aim of this book is to introduce to the design community the straightforward design solutions in any modern FD-SOI planar CMOS technologies, by taking full advantage of body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode. All design techniques are based on the classical pillar of regular planar CMOS devices. As the first fully industrial solution has been the 28nm FD-SOI CMOS technology from STMicroelectronics, all the design examples in this book have been demonstrated within this process integration frame.” [bctt tweet="The Fourth Terminal...taking full advantage of (FDSOI) body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode" username="@soiconsortium"] The folks at ST were really the first to get into FD-SOI in a big way – in fact they’ve been at it for over two decades (!) so you’d be hard pressed to find experts at a company with deeper expertise. [caption id="attachment_29610" align="alignnone" width="535"] The Fourth Terminal team friends sporting Tour de Fourth Terminal t-shirts at ISSCC 2020. From left to right: MIT Prof. (and Series Editor for Springer's Integrated Circuits and Systems) Anantha Chandrakasan; Charles Glaser, Springer Editorial Director; Laurent Le Pailleur, ST; Andreia Cathelin, ST Fellow; Sylvain Clerc, ST; Stanford Prof. Boris Murmann (Photo courtesy Springer STMicroelectronics)[/caption] The Fourth Terminal is structured to cover three major areas: a technology overview (including body biasing for digital, analog and SRAM); a selection of circuits that illustrate body biasing in various fields; body bias deployment in mixed-signal and digital SoCs. The initial response has been tremendous. Editor Andreia Cathelin reports that posts she's made about it on LinkedIn were quickly viewed 10k times and more. Then came the book review by the eminent Stanford Professor Boris Murmann, who heralded its tour de force status in a clever turn of phrase: “With the help of a renowned international team of experts from industry and academia, the editors have distilled everything you need to know about FD-SOI circuit design into a 16-chapter "tour de fourth terminal". (Read his complete review here).[bctt tweet="Stanford Professor Boris Murmann calls this book a #Tour_de_Fourth_Terminal. #FDSOI #lowpower #chipdesign" username="@soiconsortium"] EETimes journalist Junko Yoshida blogged about it as Body Bias Gets Its Own Book (read that here), which generated lively discussions on LinkedIn (and underscored just how necessary this book is!). The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems is part of the Springer Integrated Circuits Systems Series -- considered by many to be the most prestigious in the industry. Weighing in at 431 pages, The Fourth Terminal is available in both e-book and hardcover versions. See the Springer website to order this must-have addition to your library.

The GAP9, GreenWaves Technologies latest IoT application processor -- which is being fabbed on GlobalFoundries 22FDX (FD-SOI) technology -- will be sampling in the first half of 2020, according to EETimes (read the whole article here). Mass production is slated for 2021. Greenwaves (which has been an SOI Consortium member for several years now) is a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for AI processing in sensing devices at the very edge. GreenWaves marketing director Martin Croome told EETimes, “We are using the body biasing ability in FD-SOI to allow us to achieve even lower power consumption.” Compared to GreenWaves’ currently shipping product, GAP8 (which is on a 55nm bulk process), GAP9 reduces energy consumption by 5 times while enabling inference on neural networks 10 times larger. This is thanks to architectural enhancements and the move to GF's 22FDX semiconductor process. The new chip delivers a peak cluster memory bandwidth of 41.6 GB/sec and up to 50 GOPS combined compute power at an overall power consumption of 50mW. It enables customers to embed machine learning and signal processing capabilities into battery operated or energy harvesting devices such as IoT sensors in smart building, consumer and industrial markets and consumer and medical wearable devices. GAP9 was showcased at the last RISC-V Summit in San Jose (read the full press release here). [caption id="attachment_29061" align="alignnone" width="400"] GAP9 Block diagram (Courtesy: GreenWaves)[/caption] Some of the (many!) features include: 10 identical high performance, extended ISA, RISC-V ISA cores (cluster of 9 cores for compute-intensive tasks and a fabric controller core for control and communication) Dynamic voltage frequency scaling and automatic body biasing Multiple power states: deep sleep, deep sleep with retentive RAM, low activity, SOC on, SOC on cluster on Click here for a full GAP9 product brief.