AI

With edge AI emerging as a clear driver of smart manufacturing, SEMI hosted a two-day workshop detailing the future of this technology. The workshop, Smarter Sensors, Smarter Fabs: AI at the Edge in Semiconductor Manufacturing, was held in-person from March 18-19 in Milpitas, California. It convened industry professionals to explore how AI-driven sensors and edge intelligence are fostering scalable and resilient solutions for the next generation of semiconductor manufacturing. The workshop took place across four sessions, with each highlighting a unique edge-AI implementation area – including process control, yield enhancement, tool coordination, and predictive maintenance – and featured keynotes from leaders at Lam Research and KUKA. Didn’t get a chance to attend in person? View this workshop on demand. Session 1 - Smart Sensors and Edge Intelligence for Advanced Process Control​The semiconductor industry has always been defined by precision. However, as device architectures shrink to angstrom-scale dimensions, and as wafers become thinner and more fragile, traditional process control tools are reaching their limits. Sampled, low-frequency, univariate monitoring systems were built for an era where deviations were visible, failures were catchable later, and a handful of sensors per tool were enough to keep yield in check. Session 1 explored the latest sensor technologies, discussing how data collection at the point of production, with AI embedded directly into the tool, is becoming paramount for success. Advanced in-situ sensors were brought up as an example of this in practice. Although these sensors are generating richer signals than in the past, reaching lower latency requires AI models deployed at the edge.In addition, AI is extending into the physical world through robots that can handle various tasks autonomously. These robots are enabled by digital twins that provide simulation environments for training and validation before they ever see the fab floor. The common thread across Session 1 was the growing need for data and knowledge integration in fabs. Smart sensors must be built into AI systems, and those systems must be scalable across tools without sacrificing speed or reliability. Finally, the insights they generate must flow back into maintenance optimization and equipment health monitoring to promote a continuous cycle of learning. Session 2 - Yield Enhancement Through Edge-Driven Defect Detection and Classification​ Session 2 focused on how edge AI models, process sensors, and image data can identify yield-impacting defects earlier in the manufacturing process. As semiconductor devices lean into 3D architectures, the complexity and volume of data have outpaced the capabilities of traditional monitoring tools. Today's fabs are required to evaluate terabytes of inspection images per hour, as well as tool sensor traces that require analysis across dozens of parameters simultaneously. Each speaker approached this challenge from a different angle, yet the solutions fit together into a coherent architecture. One introduced Gaussian Process Regression, a model for assessing both predictions and uncertainties, as a statistically rigorous, data-efficient method for learning "golden trajectory" baselines for tool sensor signals. This generates actionable scores and maintenance guidance beyond standard anomaly alerts. Another speaker demonstrated the ability of deep learning models to triage multi-gigabit-per-second image streams in milliseconds. AI-based defect classification was shown to compress root cause analysis timelines from days to hours, with demonstrated gains of a 0.3% die yield recovery and 0.5–1% yield exposure prevention. Predictive metrology for RF filter frequency also assessed device performance using upstream process data, with less than 0.02% error.Lastly, a software-defined automation framework built on open standards and vendor-neutral architecture demonstrated effective workload consolidation onto a single edge platform. It was shown to be scalable across fabs without replacing legacy infrastructure.These presentations stressed the importance of measurement and action in real-time at the tool level. Gathering information as early as possible, using AI to triage and classify, and feeding insights back into process control and maintenance workflows, allows for a continuous cycle of improvement.Session 3 - Autonomous Work in Process Movement: Robots, Sensors, and Edge AI Coordination​The "lights out" factory is shifting from an aspiration to a concrete, engineering roadmap. To fully realize this, each presentation in Session 3 highlighted the importance of supplementing human-dependent workflows with AI systems that can act in real-time. This shift will require a mix of deep reinforcement learning and AI-based perception approaches. Currently, deep reinforcement learning is training agents to discover new routing strategies that optimize yield, equipment effectiveness, cycle time, and queue-time compliance – including joint front and back-end-of-line coordination for advanced packaging. AI-based perception is also on its way to replacing manual, pre-shipment inspection checklists, demonstrating inspection time reduction by as much as 78%. To enable these improvements, presenters suggested private 5G as the foundational connectivity infrastructure. Currently, private 5G is helping eliminate dead zones and bandwidth issues that are preventing real-time machine data and connected robotics from reaching their full potential.Based on these presentations, the prevailing formula is to integrate intelligence at every level. This includes precise in-situ sensing to eliminate manual setup and measurement, edge AI models that act on data immediately, platforms that coordinate across tools without humans, and lastly, a reliable connectivity infrastructure.Session 4 - Predictive Maintenance at the Edge: From Vibration to VisionSemiconductor fabs have long operated in a state of crisis management. Fab managers spend between 40% and 70% of their time firefighting unexpected equipment failures, rather than executing planned maintenance strategies. Unplanned downtime in semiconductor manufacturing can cost up to $1 million per hour, yet the maintenance industry has been slow to move beyond reactive repairs. Fab managers need faster ways to determine issues and act on that knowledge before wafers are lost. Session 4 outlined a framework for how this transformation will happen. At the foundation, smarter sensors (vibration, acoustic, thermal, spectral, and vision) are generating the high-fidelity, multi-modal data streams that make predictive models possible. In addition, "ultra edge" AI accelerators are enabling machine learning inference to happen directly inside MEMS sensors and on-device hardware without cloud dependency. Fabs require low-latency, data-sovereign, real-time decisions that the cloud is unable to support, and the path forward requires an integrated chain of sensing, edge inference, health scoring, and maintenance scheduling. This session also made the case that irrelevant correlations and confounding variables make purely statistical AI unreliable for root cause analysis, and that causal AI models are required to give fabs actionable information. It concluded that cybersecurity concerns, soaring cloud infrastructure costs (datacenter GPU prices reaching $25,000–$50,000 each in 2025–2026), and latency requirements have made distributed, machine-local intelligence the only viable path to achieving autonomous fabs. SummaryThis workshop highlighted how edge AI, smart sensors, and advanced connectivity are transforming semiconductor manufacturing by enabling real-time process control, faster defect detection, and more autonomous operations. Across sessions, experts emphasized that integrating AI directly at the source of data is essential for improving yield, reducing downtime, and building scalable, resilient “smart fabs.”Learn more by registering for this workshop on demand, or view the recap videos on LinkedIn. Day 1 recap Day 2 recap The SEMI Manufacturing Coalitions include Smart Manufacturing, Fab Owners Alliance (FOA), MEMS and Sensors Industry Group (MSIG), Advanced Packaging Heterogeneous Integration (APHI) and Semiconductor Components, Instruments, and Subsystems (SCIS).Anshu Bahadur leads the Smart Manufacturing Initiative, Karim Somani leads the Fab Owners Alliance (FOA), and Paul Carey leads the MEMS and Sensors Industry Group (MSIG), all of which are part of the Technology Coalitions at SEMI.

Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits; but the growth comes with an escalating demand for power, and energy has emerged as a major challenge.SEMI, as the global semiconductor and electronics association connecting over 4,000 companies, continues to unite the entire ecosystem to “bend the curve” – to maximize AI performance while minimizing power consumption. In a series of successful, sold-out workshops that the SEMI Smart Data-AI Initiative held on this topic, a resonant theme has emerged: sustaining AI progress requires energy-efficient computing with holistic co-design and co-optimization across materials, devices, systems, data transmission, data centers, emerging architectures and software. While this dialog is an important starting point, the ultimate goal is to drive concrete action through collaborative innovation.The AI Energy ChallengeAI training compute for frontier models is growing at an estimated 4–5x per year, driving unprecedented demand for hardware capability and infrastructure capacity. That trajectory has resulted in a global “data center gold rush” and is testing energy availability limits. As model sizes scale exponentially, so too does the energy required to train and deploy them; and power consumption has become a significant limiter to performance gains. Further, this increases heat dissipation, and requires innovations like direct liquid cooling.Modern AI and high-performance computing systems now operate at levels comparable to small cities, with tens of megawatts per installation and a trajectory toward gigawatt-scale data center campuses. Grid capacity—both in the U.S. and globally—may be challenged to keep pace with projected demand. Thus, AI infrastructure is no longer just a technical challenge, but it is an energy, systems, and policy challenge.System-Technology Co-OptimizationContinuous advances in chip and inference efficiency have delivered orders-of-magnitude improvements over many decades. These gains must now be expanded by holistic co-optimization of the entire compute system from silicon technologies to data center to the grid.For example, processors can be made more efficient by customizing them for specific workloads. However, only part of total data center power is consumed by the processor itself. A significant portion is used by data movement, power conversion and cooling. The energy required to move data increases dramatically with distance. Moving bits across packages, boards, and networks can consume far more energy than the compute operations themselves. This makes locality a critical design principle. The opportunity—and necessity—therefore lies in cross-layer optimization: efficient compute, efficient communication, and intelligent power management across the entire system. Not surprisingly, advanced packaging and integration are becoming central to performance. These technologies can enable architectures that tightly couple compute, memory, and I/O—using 2.5D and 3D integration techniques—reducing energy per bit and increasing bandwidth. Photonic interconnects and low-power materials can further lower the cost of processing and moving data.The bottom line is that incremental chip-level gains alone will not be sufficient and energy optimization cannot be siloed—system-technology co-optimization is needed.Hardware-Software Co-optimizationKeeping data as localized as possible depends as much on software algorithms as it does on hardware architectures. The challenge is that the development cycles are mismatched: new software models can be developed in months, while designing and fabricating new hardware can take years. While this cycle mismatch is fundamental, closer coordination between hardware and software developers can significantly improve efficiency. For example, offloading selected functions in the algorithm, including distributed DPUs, and reducing the level of data precision can reduce energy use. Partitioning workloads logically across the hardware/software stack between cloud services and compute-on-edge can also reduce energy appreciably. Further, risk mitigation techniques—for example, building in strategic redundancy—can make future designs more resilient to shifts in software algorithms and models.Diverse Computing ModalitiesWhile AI dominates current infrastructure investment, the future of computing will likely include multiple, diverse computational modalities such as quantum, neuromorphic, photonic and analog computing.Different computational paradigms will be applied where they are most effective. For example, quantum computing is likely to complement—not replace—classical systems; especially for specific classes of problems where it offers exponential advantages. However, progress in quantum computing is tightly coupled to advances in semiconductor infrastructure. Error correction, orchestration, and hybrid algorithms all depend on high-performance classical systems operating with low latency alongside quantum processors. While there is no single silver bullet, system-level design can ensure that multiple computing modalities work together within unified workflows spanning edge, cloud, and exascale environments.Why It Matters What to WatchEnergy will now be a key constraint for AI performance and infrastructure expansion.The evolution of gigawatt-scale AI campuses and their interaction with public energy grids will accelerate – or slow down – AI growth.Data movement, memory bandwidth, interconnect efficiency, advanced packaging and heterogeneous integration will be strategic levers. Enhanced system-technology co-optimization and integration of advanced technologies like 3D ICs and photonics will be critical.Co-optimization across hardware, software, and systems will be required.Future architectures will blend classical and emerging compute modalities like quantum, photonic and neuromorphic.In conclusion, AI has become a defining global force with much promise, but its trajectory will be shaped by technology, energy and infrastructure economics working together. This is a formidable challenge because it requires many diverse players with divergent priorities to collaborate effectively.We invite you to join the SEMI Smart Data-AI initiative to collaboratively address this challenge and help realize AI’s full potential sustainably. Our next workshop in this series will be on September 9 in Silicon Valley – please join us for this exciting event.SourcesSEMI Smart Data-AI Initiative – Future of ComputingEnergy-Efficient Computing for AI and Beyond, SEMICON West, October 2025Sustainable AI Systems, SEMI HQ, March 2026About the AuthorsDr. Pushkar P. Apte is the Strategic Technology Advisor for SEMI Global Lead for the Smart Data-AI Initiative Dr. Melissa Grupen-Shemansky is Senior VP and CTO of SEMI

The artificial intelligence revolution has a dirty little secret: for all its "brain" power, AI and autonomy are hopeless without the hardware that connects them to the physical world. Today’s semiconductor-related blockbuster tech topics like autonomous humanoid robots, Edge AI, self-driving cars, and lights-out fabs all depend on a variety of sensing modalities and enabling technologies (from MEMS to photonic and others). The 2026 MEMS Sensors Executive Congress (MSEC) gathered industry leaders to discuss how sensors continue to evolve from simple sensing components to the essential “eyes and ears” of a global, AI-driven transformation.The Sensor Industry is ShiftingMarcellino Gemelli of Bosch Sensortec took a retrospective approach during the Leadership Roundtable starting with the statement “to understand where we are going, we have to look at where we’ve been.” While logic and memory chips scaled rapidly, sensors faced a different reality:Commoditization: Rapid price erosion in high-volume markets like mobile.The "One Process, One Product" Curse: Unlike standard CMOS, every new MEMS device historically required a unique manufacturing flow which results in high development costs.Hard to fill MEMS Fabs: Geometries are shrinking resulting in more devices per waferPackaging: A challenge because it directly impacts device performanceSensor Fusion: Integrating sensor components with ASICs and MCUs to create smart sensorsAccording to Maximize Market Research, the global sensor market is predicted to have an 8.7% CAGR from 2024 through 2030. There is a fundamental realization about sensors: the next stage of autonomous manufacturing and intelligent systems cannot exist without high-fidelity, real-time sensor data from the edge. This was a common theme throughout MSEC. Data presented at MSEC by Pierre-Marie Visse of Yole Group shows the global MEMS market is projected to grow more slowly with a 3.7% CAGR over the same time frame, with higher growth predicted for automotive, industrial, and medical applications.The Leadership Roundtable, featuring executives from Bosch, Infineon, STMicroelectronics, and Rogue Valley Microdevices, highlighted the strategic roadmaps that will define the next decade, echoed by others during other technical presentations:The Edge of Perception: AI is pushing sensing technologies to process data within the sensor itself and not in the cloud, reducing latency and power consumption while improving privacy.Autonomous Manufacturing: Leaders like John Behnke (INFICON) and Edvard Kälvesten (Silex) mapped out the path toward “Autonomous Fabs,” where sensors allow tools to communicate and self-optimize with minimal human intervention.Emerging Modalities: Beyond traditional motion and pressure sensing, MSEC spotlighted the rise of Quantum sensors for resilient navigation and Photonics combined with MEMS for ultra-precise inertial sensing.From “Parts” to “Interfaces”A recurring theme throughout the congress was the death of the "sensor as a part" mentality. In his keynote, Kurt Busch (Syntiant) argued that sensors plus AI models are becoming the default interface layer for products.“The next-generation interface is not a screen. It is the physical world, captured by sensors, interpreted by models, and delivered through natural interactions,” said Busch.This shift is visible in the rapid adoption of Edge AI integration, the development of humanoid robots, autonomous drones and vehicles, and AI enabled smart glasses—rewriting what the human machine interface looks like.Conclusion: Sensorizing the FutureWe are no longer just building devices; we are building an “industrial AI operating system” that connects the digital and physical world. This all starts with sensors. By 2030, the most valuable AI won't just be the one with the biggest brain, it will be the one with the best senses.If you are a leader in the field of MEMS Sensors, let your voice move the industry needle by becoming a SEMI and MEMS Sensors Industry Group (MSIG) member company and getting involved with MSIG. MSIG will be hosting the MEMS Sensors Technical Congress (MSTC) on September 16-17 at SEMI HQ in Milpitas, CA. Engineers and technical executives will dive deep into new technology and processes that advance the sensor industry. To learn more or to be a part of the fascinating world of MEMS Sensors visit the SEMI MSIG website.Paul Carey is Director, MSIG at SEMI. Rafael Tudela is Senior Technical Marketing Manager at SEMI.

The rapid growth of AI has created a surge in the global energy consumption at a rate never seen before. Today, data centers account for approximately 415 terawatt-hours (TWh) of electricity globally. To put this into perspective, the annual energy consumption of the United Kingdom in 2023 measured at 309 TWh. The International Energy Agency (IEA) projects data centers’ energy consumption will more than double to nearly 945 TWh by 2030 [1]. A single generative AI query can consume up to ten times the power of a traditional search [1]. Meanwhile, data center energy usage in the U.S. is projected to leap from 4.4% to as much as 12% of the national grid by 2028 [2]. This creates a stark reality for the semiconductor industry. Traditional monolithic scaling has hit its physical and economic limits, leaving advanced packaging and heterogeneous integration to define the industry’s trajectory [3].To meet these escalating compute demands, the industry is rapidly shifting toward multi-die architectures, chiplets, and 3D stacking to decrease the amount of energy needed for advanced computing. This transition is fueling explosive growth in the advanced packaging market, which the Yole Group projects will reach $79.4 billion by 2030 [4]. However, stacking chiplets to bypass Moore’s Law exposes massive systemic bottlenecks. Engineers are now fighting interconnect parasitics, navigating complex power delivery architectures, and battling extreme thermal density.In a 3D-stacked architecture, pulling heat away from vertically integrated dies is one of the most pressing engineering challenges of our time. As compute density rises, issues like die warpage and localized thermal hotspots threaten both reliability and yield. The shift toward sustainable AI systems for energy-efficient computing requires breakthroughs in everything from hybrid bonding process flows to advanced thermal interface material (TIM) strategies and liquid cooling integration [6].These are not challenges that any single company can solve in isolation. Whether you are a foundry, OSAT, material supplier, or equipment provider, overcoming these bottlenecks requires pre-competitive, industry-wide collaboration. Foundational capabilities must be built collectively before competitive differentiation occurs.This is the core mission of the SEMI Advanced Packaging and Heterogeneous Integration (APHI) Technology Coalition. By collaborating on common standards, shared research frameworks, cross-vendor interoperability models, and collective technology roadmap congruency, APHI is actively dismantling the barriers to next-generation computing.The APHI community is already tackling these issues head-on. Monthly chapter meetings identify and address these and other issues facing heterogeneous integration. The most recent chapter meetings showcased in depth review of these challenges. Jonathan Abdilla from BESI detailed the technical challenges and collaborative research required for global hybrid bonding process flows. Similarly, Dr. Jie Geng from Indium Corporation led a deep dive into crucial TIM strategies for AI and HPC, exploring hybrid stacking evaluation methods and liquid cooling options to combat GPU die warpage.The future of advanced manufacturing will be defined by how effectively we manage power and heat in heterogeneous systems. We invite you to join this critical conversation at the upcoming SEMIEXPO Heartland (April 29-30 in Detroit, MI) Day 2 will feature dedicated sessions on Thermal Management Power Delivery in Advanced Packaging: From TIMs to Warpage Control, as well as strategies for securing the advanced packaging supply chain.To help shape the standards and shared roadmaps that will power the AI revolution, explore our initiatives and get involved with SEMI Advanced Packaging and Heterogeneous Integration (APHI) Technology Coalition.Rafael Tudela is Senior Technical Marketing Manager at SEMI References[1] International Energy Agency (IEA). (2024). Energy and AI Report. [2] U.S. Department of Energy (DOE) Lawrence Berkeley National Laboratory (LBNL). (2024). Report on U.S. Data Center Electricity Demand and Grid Impact.[3] Semiconductor Packaging News. Advanced Packaging and Heterogeneous Integration. Retrieved from: https://www.semiconductorpackagingnews.com/articles/92402.html [4] Yole Group. (2025). Status of the Advanced Packaging Industry 2025.

As the global semiconductor industry enters a decisive new phase shaped by artificial intelligence, SEMICON Korea 2026 convened the ecosystem from February 11–13 in Seoul, bringing together the companies, technologies, and talent required to sustain momentum on both sides of the AI equation: using AI to transform semiconductor operations, and advancing semiconductor innovation to enable the next generation of AI systems.At the SEMICON Korea press conference, Hyun Cha, President, SEMI Korea stated that with nearly 550 exhibiting companies and over 2,400 booths, the event underscored how progress now depends on a virtuous cycle of collaboration across the entire value chain—from materials and equipment to design, manufacturing, packaging, and systems integration.Opening Perspectives: Collaboration as the Catalyst In the opening ceremony, Ajit Manocha, President and CEO of SEMI, framed the opportunity and challenge ahead: AI is accelerating the industry’s trajectory toward a trillion-dollar market, but sustaining that growth will require deeper collaboration across an increasingly complex ecosystem.That message was reinforced by YH Lee, Chairman of Wonik, who emphasized the need for alignment across the value chain, “looking side to side, not only forward,” as scaling semiconductor technologies grows more difficult. From a policy perspective, Shinhak Moon, Vice Minister of Korea’s Ministry of Trade, Industry Resources (MOTIR), highlighted the importance of the full ecosystem, including parts, materials, and equipment, while cautioning that resilience will be critical amid economic cycles. Together, these perspectives set the stage for a keynote program focused on how AI and semiconductors are now co-evolving.Opening Keynote: Samsung Electronics on Architecting the Future of AI SystemsThe keynote program opened with Jaihyuk Song, Corporate President and CTO of Samsung Electronics, who examined what comes next for AI systems as compute and memory demands rise exponentially. He described a widening gap between compute performance and memory bandwidth, positioning advanced packaging and architectural innovation as central to closing that gap.Song outlined Samsung’s focus on next-generation memory technologies, including high-bandwidth memory and compute-in-memory approaches, as well as the transition beyond traditional Moore’s Law scaling toward planar, vertical, and stacked architectures. His message was clear: sustaining AI performance gains will depend on tight integration across design, process technology, packaging, and system architecture, reinforcing the need for ecosystem-wide coordination. ASE: From Chip Integration to System OptimizationTien Wu, CEO of ASE, expanded the discussion from devices to systems, arguing that advanced packaging has become a primary driver of system-level performance and efficiency. As AI workloads push power, thermal, and bandwidth limits, Wu described a shift from single-chip packages toward heterogeneous integration, 2.5D and 3D architectures, and co-packaged optics.Wu emphasized that productivity, yield, and throughput will increasingly determine competitiveness as packages grow larger and more complex. His perspective reinforced a central theme of SEMICON Korea 2026: AI-driven demand is forcing tighter coupling between design, manufacturing, and packaging, making collaboration not optional, but essential.Cadence: AI-Enabled Design Across the Value ChainBoyd Phelps, Senior Vice President and General Manager of Silicon Solutions at Cadence Design Systems, highlighted how AI is already reshaping semiconductor design and development. As process scaling slows and cost per transistor rises, Phelps described disaggregation and chiplets as a new abstraction layer that enables continued innovation through customization and configurability.He also pointed to the growing role of AI-driven design automation, noting that a significant portion of recent designs leveraged AI-enabled tools. Cadence’s end-to-end portfolio—from IP and tools to packaging and test—illustrated how AI is becoming both a design accelerant and a necessary response to rising system complexity, reinforcing the industry’s virtuous cycle.Lam Research: Velocity Through AI and AutomationThe theme of operational transformation took center stage with Tim Archer, President and CEO of Lam Research, who introduced “velocity” as the defining imperative of the AI era. As AI-driven demand accelerates product cycles and increases complexity, Archer argued that speed must be matched with direction—enabled by AI, automation, and digital twins.Archer detailed Lam’s progress toward autonomous fabs, equipment intelligence, and collaborative virtual development environments that reduce variability and accelerate process development. These capabilities, he explained, allow the industry to respond faster while preserving quality and resilience—another example of AI improving semiconductor operations even as semiconductor innovation enables AI growth.SK hynix: AI as a Tool for Memory InnovationLooking further into the future, Sunghoon Lee, Senior Vice President and Head of R D Process at SK hynix, addressed the mounting difficulty of sustaining memory technology cadence. As stacking, bonding, and material challenges intensify, Lee described a shift toward AI-based R D models that dramatically accelerate material discovery and optimization.By integrating AI into material exploration and process development, SK hynix is shortening development cycles and enabling new memory architectures. Lee emphasized that realizing the full potential of AI-driven R D will require greater data sharing and collaboration across partners—reinforcing the ecosystem-wide virtuous cycle.NVIDIA: From Chips to AI InfrastructureThe final keynote, delivered by Soyoung Jeong, Head of Korea Business at NVIDIA, framed the transformation of NVIDIA from a GPU company into an AI infrastructure provider. He described how accelerated computing and AI factories are reshaping chip design, manufacturing, packaging, and system integration.From AI-assisted design and simulation to system-level optimization and physical AI, NVIDIA’s approach illustrated how semiconductors and AI are now inseparable, each advancing through the other. Partnerships across memory, equipment, and software ecosystems were highlighted as critical to sustaining this momentum.A Program Aligned Around the Same ThemeBeyond the keynotes, SEMICON Korea 2026 reinforced these messages through technology symposia, AI and smart manufacturing forums, cybersecurity discussions, and workforce development initiatives—all focused on enabling AI-powered innovation across the semiconductor lifecycle.Additional Program Highlights: Extending the Virtuous Cycle Across the EcosystemBeyond the keynote stage, SEMICON Korea 2026 reinforced the same virtuous cycle of AI and semiconductor innovation through a wide range of technical, business, and workforce programs designed to engage every layer of the value chain.AI Summit: Translating Strategy into Industrial ImpactThe AI Summit, co‑hosted by SEMI and KAIST, served as a focal point for aligning academic research, device manufacturers, and equipment leaders around AI-powered industrial innovation. Featuring faculty from KAIST alongside representatives from Samsung Electronics, SK hynix, and global equipment companies, the summit explored technology strategies and future roadmaps aimed at accelerating AI adoption across semiconductor manufacturing and design.The discussions reinforced a central theme of SEMICON Korea 2026: AI is no longer an isolated software layer, but a system-level capability that must be embedded across processes, tools, and infrastructure to unlock its full value.Smart Manufacturing Forum: Advancing the Autonomous FabThe Smart Manufacturing Forum highlighted how AI, digital twins, and real-time data are transforming semiconductor fabs toward more autonomous, resilient operations. Speakers shared trends and success cases demonstrating how advanced analytics and AI-driven decision-making are improving yield, productivity, and operational agility.This forum echoed themes raised by equipment and manufacturing leaders in the keynote program, underscoring how AI-driven manufacturing excellence is becoming a prerequisite for meeting the speed, scale, and quality demands of next-generation AI chips.Startup Summit: Fueling Innovation from the Ground UpThe Startup Summit showcased emerging semiconductor and display startups focused on applying AI to improve chip performance, energy efficiency, and manufacturing processes. By connecting startups with industry leaders and venture capital firms—including Applied Ventures, Intel Capital, Samsung Ventures, and SK hynix—the summit emphasized the importance of nurturing innovation across the ecosystem.These early-stage technologies represent the next wave of ideas feeding into the virtuous cycle, where AI-enabled innovation at the startup level can scale rapidly through collaboration with established players.Cybersecurity Forum: Securing the AI-Driven Semiconductor FutureAs AI becomes deeply embedded in semiconductor operations and data flows, the Cybersecurity Forum addressed the growing need for digital trust across the ecosystem. Global experts examined cybersecurity challenges related to compliance, fab security, and AI data governance, highlighting the importance of collaboration to protect sensitive data and intellectual property.The forum reinforced that secure, trusted infrastructure is a foundational requirement for the AI-driven transformation discussed throughout SEMICON Korea 2026.Conclusion: Advancing TogetherSEMICON Korea 2026 made clear that the next phase of industry growth will not be driven by isolated breakthroughs, but by a virtuous cycle of alignment across the full semiconductor value chain. By integrating AI into design, manufacturing, and operations—and by advancing semiconductor technologies that power AI—the industry is building a foundation for sustained innovation. As the event demonstrated, progress will be fastest when the ecosystem moves forward together.Samer Bahou is Director, Corporate Communications at SEMI. Jaegwan Shim is Senior Specialist, Marketing at SEMI Korea.

The semiconductor industry is hitting a structural inflection point: explosive AI‑driven demand, rapidly rising manufacturing complexity, and stringent sustainability expectations are converging at once. In this context, edge AI deployed directly on tools, sensors, and local controllers, is shifting from experimental to essential, particularly in fabs where milliseconds matter. SEMI’s timely workshop, Smarter Sensors, Smarter Fabs: AI at the Edge in Semiconductor Manufacturing, taking place March 18–19, 2026 in Milpitas, CA, will address this important topic.From sparse sensing to dense instrumentationTwo decades ago, most process tools relied on dozens of sensors per chamber. Today, leading etch, deposition, CMP, and lithography systems routinely integrate hundreds of sensing channels spanning pressure, flow, RF power, optical endpoint, vibration, and chemistry. At 3 nm and 2 nm, process windows are so tight that yield hinges on multivariate understanding of chamber conditions and tool state rather than a few independent alarms. Sensor proliferation has turned fabs into rich data environments—but also exposed the limits of traditional, centrally managed control.Why edge AI is displacing cloud‑only controlConventional architectures push heavy analytics to centralized servers or the cloud, with supervisory systems periodically updating recipes, setpoints, or dispatch rules. Across manufacturing, measured cloud round‑trip times commonly range from 800 to 2,400 ms, whereas edge systems co-located with equipment can respond in 15–45 ms, roughly 50–160× faster. For safety‑ and yield‑critical loops in semiconductor manufacturing, that latency gap is often unacceptable.At the same time, new generations of low‑power neural processing units (NPUs) and edge accelerators deliver tens of trillions of operations per second (TOPS) at single‑digit watt budgets, making always‑on inference viable inside tools, cameras, and controllers. The result is a decisive move toward edge‑native architectures: models execute where data is produced, while cloud resources are reserved for retraining and fleet‑wide learning.Edge AI on the line: control, inspection, and maintenanceIn process control, edge AI is enabling a shift from univariate threshold checks to multivariate models that understand the joint dynamics of sensor streams. Platforms today embed deep‑learning and statistical models directly at or near the tool, performing real‑time endpoint prediction and anomaly detection from high‑dimensional time series. Similar approaches are emerging in lithography and CMP, where local inference helps keep focus, overlay, and removal rate within spec before wafers drift out of control.Inspection and logistics are undergoing a similar transformation. Vision systems with embedded NPUs classify defects at line speed, often above 100 parts per minute, eliminating the need to ship large image volumes to a central cluster. Robots and autonomous mobile robots (AMRs) use local intelligence for short‑horizon planning and collision avoidance, while higher‑level systems focus on global scheduling and optimization.Predictive maintenance is one of the most mature applications: vibration, acoustic, temperature, and pressure data are analyzed locally to detect anomaly signatures hours or days before conventional thresholds trip. Reported benefits include reductions in unplanned downtime, longer component life, and lower maintenance costs when these models are integrated into manufacturing execution systems (MES) and maintenance workflows.Digital twins and agentic AI on top of edge dataDigital twins build on this sensing and edge‑analytics foundation. By maintaining virtual, live‑updated models of tools, lines, and entire fabs, they enable scenario testing, debottlenecking, and root‑cause analysis without putting WIP at risk. Vendors and early adopters report that such twins can shorten process‑node ramps and facility bring‑up by enabling thousands of “what‑if” experiments before physical changes are made.​Agentic AI is now emerging as the orchestration layer above these twins. In semiconductor case studies, agents connected to MES, advanced process control (APC), and planning systems have delivered double‑digit improvements in throughput, cycle time, and tool utilization by autonomously adjusting routing, batch sizes, and scheduling in response to live fab conditions. Other agents mine unstructured engineering notes and fault reports to accelerate root‑cause analysis, turning hard‑won lessons into repeatable, codified behavior.Sustainability as a first‑class requirementSustainability pressures are reinforcing this stack. Semiconductor manufacturing is energy‑ and resource‑intensive, and regulators and customers alike are demanding more transparency and improvement. Edge‑connected monitoring of energy, utilities, and emissions has already helped some fabs cut energy‑related costs by around 20 percent through tighter control of HVAC, process gases, and idle modes. Research initiatives such as imec’s Sustainable Semiconductor Technologies and Systems (SSTS) program are using virtual fab methods and detailed life‑cycle assessment to guide process and equipment choices for lower environmental impact.Strategic takeaways and where to learn moreThe trajectory is clear: fabs that combine dense sensing, edge AI, digital twins, and agentic AI are building toward continuously learning, self‑optimizing operations. Architectures will need to be edge‑first rather than cloud‑only. Simply adding sensors without local intelligence will not deliver competitive advantage, and environmental KPIs are likely to be optimized with the same rigor as yield and cycle time.For practitioners who want to translate these trends into roadmaps, the Smarter Sensors, Smarter Fabs: AI at the Edge in Semiconductor Manufacturing” workshop (March 18–19, 2026, Milpitas, CA) spearheaded by the SEMI Manufacturing Coalitions* will bring together experts in sensing, edge architectures, digital twins, and agentic AI to share concrete deployments and architectures tailored to semiconductor fabs.*The SEMI Manufacturing Coalitions include Smart Manufacturing, Fab Owners Alliance (FOA) MEMS and Sensors Industry Group (MSIG), Advanced Packaging Heterogenous Integration (APHI) and Semiconductor Components, Instruments, and Subsystems (SCIS). Anshu Bahadur is Senior Program Manager, Technology Communities at SEMI. Mark da Silva is Senior Director, Manufacturing Coalitions at SEMI.

Aki Fujimura has been at the forefront of chip design innovations from the beginning of his career and his technology leadership continues today. He serves as Chairman and CEO of D2S, co-founder of the eBeam Initiative, President of BACUS, and a Governing Council member of the ESD Alliance, a SEMI Technology Community. At Tangent (now Cadence), Fujimura and Steve Teig (a chip designer for the last 20 years and now Vice President and Distinguished Engineer at Amazon) built the first commercial over-the-cell routing system dedicated to fully synchronous designs with timing assurance and automated test-scan insertion. Fujimura and Tom Kronmiller developed LEF/DEF for efficient representation of Manhattan routing, both used as standards in the automated place and route (P R) flow to this day. He again teamed with Teig and Kronmiller to develop the X Architecture, an interconnect architecture based on the pervasive use of 45o diagonal routing. I was thinking about his background as I called him to chat about his evolution from chip design before focusing on chip manufacturing via eBeam technology at D2S.Smith: Let’s talk about your journey from focusing on how to do physical design of chips to chip manufacturing. How did this happen?Fujimura: GPUs weren’t a thing until late 1990s. With CPUs, Manhattan design was the obvious choice for computational efficiency. Largely gridded metal n that went up and down, and metal n+1 that went left and right with vias to connect the line segments were how all automated layout worked. PCB routing and packaging (even back then) used diagonal routing and even curved routing. But chip P R was all Manhattan. That was still true when we worked on the X Architecture at Simplex Solutions (now Cadence). ATi (now inside AMD), NVIDIA and several other GPU companies started in the late 1980s to 1990s, but they were targeting video and gaming more than scientific computing at the time. It’s when Teig came up with the idea for the X Architecture that he wanted to know if 60-degree routing was possible “because a hexagon tessellates a plane.” A good question. I set out to try to find out what the actual limits were in manufacturing that create the limitation to Manhattan shapes. I got introduced to the late Bill Arnold of ASML, who then introduced me to a lot of people in manufacturing who helped me get the answer. Naoya Hayashi of DNP was instrumental in helping me understand that mask making is where the limit exists. Hayashi-san kindly explained to me about the two mask writers. I had to dig around a lot more to make sure that that was the only barrier, but that’s how I came to understand that before masks, everything is data, and after masks, everything is physical. Mask making is the key that enables 45 degrees, but not 60 degrees. The lessons I learned then are still very important to me today. That’s when I saw and appreciated the opportunity there is for software for semiconductor manufacturing.Smith: But you still couldn’t use GPUs for the X Architecture work?Fujimura: Right. Way too early. The idea that GPU-accelerated gaming machines can be connected together to do video editing, or that large scientific simulations can be done on a connected set of gaming machines, was being explored in the 1990s already. It was only 20 years ago (2006) when Jensen Huang announced his bet with the CUDA software stack for general purpose GPUs (GP GPUs) for nodes in racks of CPUs, GPUs, memory and communication to create the modern scientific computer. Six years later in 2012, AlexNet won the ImageNet Large Scale Visual Recognition Challenge (ILSVRC) with CUDA, and the rest is history. But no, we didn’t use GPUs at Simplex. But we did help design GPUs, including with the X Architecture.Editor’s Note: ILSVRC evaluates algorithms for object detection and image classification at large scale. Smith: Now, everything you do at D2S is with GPU acceleration. When and how did that change come about?Fujimura: It was back in 2009, two years after D2S was founded. An extraordinary engineer, Harold Zable, noticed that simulation-based manipulation (rather than rules-based manipulation) of mask shapes, both for wafer manufacturing and for mask manufacturing, would be the ideal application for GPU acceleration. Fast-Fourier Transforms (needed for lithography simulation and optical proximity correction (OPC)/inverse lithography technology (ILT)) and Gaussian manipulations (needed for eBeam mask simulation and mask process correction (MPC) are nearly “free” in terms of compute time on GPUs. You still have to get the data in and out efficiently, but you can do pretty sophisticated computing without much overhead. At the same time, multi-beam based eBeam writing was getting momentum, first in wafer direct write applications. In 2007, at the BACUS conference in Monterey, Calif., IMS—then a well-respected research organization in Vienna—published a paper saying that multi-beam for mask writing is what they’d like to do. The wafer market is much bigger, but this technology is more suited for mask writing, where write times are measured in hours per mask. “Wafers Per Hour” is the measure in wafer manufacturing, so mask writing gets to flip the division. We were looking at a mask design and mask manufacturing world that should be doing simulation-based manipulation rather than rule-based. That’s better with GPUs. On top of that, maybe the world is going to go to multi-beam writing, going away from four decades of variable-shaped beam (VSB) writing. And I knew from the X Architecture experience that VSB was the only thing in the eco-structure that restricted mask shapes to be Manhattan or 45 degrees. In fact, with multi-beam, any curvilinear shape within the limits of resolution of a given pixel size can be freely written on the mask. The only barrier then to having curvilinear masks would be the software stack and trying to compute it with CPUs only. We knew GPU acceleration was the answer. Smith: Was it just totally an accident that multi-beam and GP GPUs happened at the same time?Fujimura: Yeah, it was. However, just as when multiple people simultaneously invent the same thing without knowing about each other, the environment and times in which we live have a lot to do with this. So, I guess, it’s not really just “luck.” But GP GPUs in 2006 and IMS Multibeam in 2007, I think that’s luck.Anyway, D2S became the GPU-acceleration partner for the semiconductor manufacturing industry and decided to work only on things that can be accelerated by GPUs in 2012.Smith: What trends do you see going forward in the next three to five years?Fujimura: A move toward curvilinear mask features, as well as an increased interest in curvilinear wafer targets as designers become aware that the manufacturing side has established a solid path for curvilinear mask shapes. We’re leaving a lot of margin on the table to accommodate gridded Manhattan assumptions, and that’s really no longer necessary from a manufacturing standpoint. I think electronic design automation (EDA) should be working on enabling curvilinear designs, because the door is open for the design world to explore curvilinear chip design and to reap compelling benefits in terms of power/performance and reliability.Editor’s Note: While Manhattan geometries are rectilinear shapes aligned to vertical and horizontal axes, curvilinear design introduces smooth, continuous curves into layouts and masks, leveraging advanced computational lithography and mask-writing technologies. This improves pattern fidelity, electrical performance and manufacturability at advanced technology nodes.About Aki FujimuraAki Fujimura is chairman and CEO of D2S, Inc., and managing company sponsor of the eBeam Initiative. Previously, Fujimura was CTO at Cadence Design Systems, President/COO and inside board member of Simplex Solutions, and VP and inside board member at Pure Software. He co-founded Tangent Systems (acquired by Cadence).Fujimura, made a SPIE fellow in 2023, serves as President of the SPIE BACUS Technical Group. He serves on the governing council of the ESD Alliance, a SEMI Technology Community. Fujimura was on the board of HLDS, RTime, Bristol, S7, and Coverity, Inc.Fujimura received his BSEE and MSEE degrees from MIT.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Presentations from SEMICON West’s “The Convergence of Semiconductor Manufacturing and Design” offer great insights into the collaboration between the two, as I was recently reminded by presenter Sutirtha Kabir, R D Engineering, Executive Director at Synopsys.Reviewing his talk “Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” was a good kick-off for our discussion that covered the continuous need for collaboration and where AI fits. Kabir, as I quickly learned, is a technical innovator and articulate communicator passionate about ongoing collaborations between design and manufacturing. Today’s blog post is the second in a four-part series featuring presentations from the SEMICON West design program, organized by the ESD Alliance, a SEMI Technology Community. The first blog, with Dave Kelf, CEO of Breker Verification Systems, appeared on January 6 (“Circular Collaboration Leverages EDA Advances”).Smith: How do you define collaboration between design and manufacturing?Kabir: Multi-die design and advanced packaging are a big focus of high-performance computing (HPC) and AI chips. Engineers are trailblazing and foundries are coming up with new stacking combinations. For this reason, design and manufacturing teams need to be closer than ever. Solutions must be made available to give ample visibility to manufacturing from the very start of the design process. Single die design has been done for 15 to 20 years with a continuity of power, area, and performance (PPA). Design flows, methodologies and the ecosystem between design houses, EDA vendors and foundries are mature and stable. The conundrum is that it's a different situation with multi-die designs. Not only is multi-die emerging rapidly, but the types of design innovations are different.We have been working closely with our foundry partners to move multi-die innovation forward by enabling more advanced process and packaging technologies. I don't see this slowing down as they are coming up with different ways of doing designs. Design teams are collaborating closely with the foundries to take advantage of the benefits of these new multi-die designs.Smith: You mentioned new stacking combinations and collaboration with the foundries. What about collaboration with the OSATs? Kabir: Generally, it’s both silicon foundries and OSATs. With advanced packaging, both play a significant role depending on the types of applications being targeted. Design house targets may shift from the traditional silicon foundry to several OSATs. For example, if an organic interposer is required, the collaboration could be with an OSAT in conjunction with the silicon foundry. There are many possible collaborations that may be required. The point I’m trying to make is that there is a strong need for collaboration between EDA and the foundries during design that continues through manufacturing and test.Smith: What trends in general are driving the need for this collaboration?Kabir: The trends are performance and scalability and the need for high-performance compute. Look at some of the mega-chip systems coming out today compared to the bigger systems from five years ago. HPC was not driving that much in 2.5D. The big interposers used to be on silicon, maybe 1.2 to somewhere around less than three reticle sizes. Today, the reticle limit is more than 5X. Leapfrog to today, and the configuration has changed where the state of the art is to use an organic interposer with multiple embedded bridges (up to 20 or more) buried inside the interposer to support high-speed interconnect. The organic interposer with multiple layers on the front side and back side communicates with bridges and the SoC and HBM that sit on top of that interposer.3D architectures stack dies with GPUs and a large amount of HBM such as an HBM4 memory stack. The memory stacks may be 8 or 16 high. All of this memory needs to be as close as possible to compute for scalability. In terms of the high-power demand, the designer needs to make sure that the voltage that is pushed from the bottom of the stack can feed the power hungry SoC blocks on top of the 3D stack. At the end of the day, EDA is all about giving design and manufacturing houses the capability to predict how a design is going to perform in all different kinds of scenarios. EDA must keep up with this trend and that requires collaboration.Smith: What about the verification side, specifically system verification? Kabir: Let’s say I am using a spreadsheet and doing back-of-the-napkin calculations, a technique that used to work well for single die or design blocks. Multi-die doesn't scale since multiple heterogeneous dies in a single package must be considered. Design planning must include directional changes to measure the effects with key performance indicators. The challenge is to correlate signoff and verification. Signoff engineers can no longer just verify at the end of the design cycle. Instead, it has become a continuous process that transcends the flow from design planning through implementation and signoff and release to manufacturing.The industry is repeating a pattern from about 20 years ago, when single-die design evolved from relatively naive approaches to much more sophisticated EDA-flow-driven methodologies.Smith: As you drive the tools forward, who are your counterparts on the manufacturing side? Kabir: It depends on the different stages of design—design planning, implementation or signoff. It starts at the architecture stage from the left when architects and physical design engineers are doing floorplanning. The term design technological co-optimization (DTCO) has evolved into S (system)TCO now because we are trying to co-optimize system design and technology. I'll give you a simple example. A working chip manufactured in a certain technology node is going to be used in a multi-die design. Is the existing chip technology good enough to support the design or will it require a new chip at a different node? In either case, how does an engineer work with the manufacturing house to make sure it has the right metal layers or a different number of metal layers or a different metal width or some other property on the technology side? Designers need to make data-driven decisions based on the configuration and technology numbers to meet power budgets.In the past, what was once managed through designer-ASIC house-manufacturing interactions are now increasingly being handled by EDA flows as part of design implementation.Smith: Ultimately, it's driven by business. The hard work and decisions are made by two teams of knowledgeable technical people who must come together.Kabir: And then of course it has to be rolled into program management, business development and all this needs to be supported by data. We all recognize that the design window is not increasing. It’s always about trying to get more out in less time with less people. That doesn't help the equation.Bob Smith: How does AI fit into this and how is it best leveraged? Kabir: I’m hearing, learning, and reading about the tremendous advantages AI could bring. AI has a huge role to play, but it won’t eliminate the need for savvy design and verification engineers.Multi-die design brings together different users from different tool backgrounds. Even the language between a packaging person and a silicon person is different. The terminologies they use are different, as are the ways they have done design over the last 15-20 years. The same applies to thermal, power or signal integrity engineering. Bringing them together requires that EDA will provide platforms where the whole system design, including chip design, is managed. That’s a tall ask for people from all different backgrounds to come in, learn different technologies and tools within a short time. This is where ChatGPT or Microsoft’s Co-Pilot can be applied in the EDA world today to quickly find solutions by reading through manuals, application notes, forums and the like to find solutions. This use of AI agents can save tremendous amounts of time for designers. Another aspect that can be positively impacted are roles. We have customers coming to us and brainstorming on the use of workflows and methodologies, instead of the design aspect. Scalability from the human perspective has become difficult because of the need to closely guide engineers to get them up to speed on new technologies and workflows. This is where Agentic AI can deliver a huge productivity boost. It's not replacing anyone. It's getting them to decisions and end results faster.Smith: Can Agentic AI play a big role? Kabir: Current AI is like the person who, when asked a question, has to give an answer even if it’s the wrong answer. The same thing is going to happen when we bring in all these EDA technologies with AI capabilities.The point I'm trying to make is how do we verify that AI is doing the right thing? In EDA, one of the biggest questions and concerns is if a result or outcome or design can be verified. If it can't be verified accurately, verification engineers will not trust what AI is telling them no matter how fantastic the algorithm is. The verifiability of AI solutions is important for EDA. The key question is: Why would I trust what your tool is telling me to do?EDA flows that are more mature rely on decades of expertise, thorough documentation, and various scenarios to train AI algorithms. Those are the AI-powered EDA flows that I trust the most. About Sutirtha KabirSutirtha Kabir, an Executive Director of R D for Synopsys’ 3DIC Compiler, has over 20 years of product engineering experience, driving, building, and inspiring teams across companies in the EDA industry. In his role at Synopsys, he supports construction and analysis of multi-die systems including stacked ICs plus Interposer configurations. Prior to joining Synopsys, Kabir was a Group Director of Engineering at Cadence. Kabir has a Master of Science degree in Electrical Engineering. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

On December 13, SEMI submitted its response to a Request for Information (RFI) from the U.S. Department of Commerce (the Department) regarding the newly launched American Artificial Intelligence (AI) Exports Program. The intent of this program is to position U.S. firms as global leaders in AI by connecting them with international buyers, leveraging the Department's export promotion tools and supporting industry-led consortia through targeted government backing. By issuing this RFI, the Department intends to solicit input on the development of industry-led consortia capable of delivering full-stack American AI export packages under the American AI Exports Program. Working with member companies, the SEMI Public Policy and Advocacy (PP A) team developed a response highlighting the importance of the semiconductor supply chain to the AI ecosystem, and offering various recommendations for consortium formation, federal support, strategic objectives, and proposal evaluation. The response was informed by direct discussions between SEMI PP A and Department officials implementing the program. Some of the key aspects of SEMI's response include the following:Broader AI Tech Stack Definition: The Department should recognize semiconductor manufacturing technologies, mature node semiconductors, and energy/environmental control systems as foundational elements of the AI technology stack. Evaluation Framework: Evaluation criteria for consortium proposals should align with CHIPS for America requirements and guardrails, focusing on national security, economic competitiveness, and commercial viability, as well as infrastructure needs.Consortia Governance: Consortia should be industry-led and feature: honest brokers capable of coordinating commercial actors while advancing national interest objectives; modularity to ensure that the various technology layers function as distinct yet interoperable units; and clear frameworks for intellectual property protections and regulatory compliance. Foreign Participation: Vetted foreign entities should be allowed to participate in the program in order to reflect the global nature of the AI ecosystem and to strengthen allied and partner nation supply chain resilience.Federal Support Mechanisms: The Department should leverage the unique capabilities of the National Institute for Standards and Technology, Center for AI Standards and Innovation, Bureau of Industry and Security, Export-Import Bank, Development Finance Corporation, and others, including expedited licensing, financing tools, tax incentives, and interagency liaisons to accelerate exports. National Security Compliance: SEMI's comments emphasize robust compliance programs, cybersecurity, supply chain security, and risk-based licensing to prevent misuse or diversion of AI technologies. Global Competitiveness and Standards: SEMI urges rapid implementation, international promotion of U.S. AI technologies, and leadership in global standards to ensure interoperability and trusted adoption worldwide.SEMI is grateful for the feedback provided by our member companies in developing this comprehensive response to the Department's RFI. Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Ben Kallen is Sr. Manager, Public Policy Advocacy at SEMI.

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]