semiconductors

Executive Advisor Jeff Lewis held the position of Vice President of Marketing and Business Development for Artisan Components, one of the early companies developing blocks of intellectual property. Lewis, who worked at Artisan from 1996-2000, and his colleagues were members of an elite group who built the mega-successful IP market, estimated today at $7.48 billion. Arm acquired Artisan Components in 2004 for $913 million.In my role as Executive Director of ESD Alliance and publisher of the quarterly Electronic Design Market Data (EDMD) report that includes IP, I recently talked with Lewis about what he remembers from the early days of IP.Smith: You were part of the IP revolution. What were the high points and low points that you most remember? Lewis: The high point was starting with a relatively blank slate and innovating. Some things worked, some didn't. We kept trying different things and seeing what would work with plenty of failed tries, successes, and repeats. We got a chance to be on the ground floor of a new industry. Another high point was watching this nascent industry emerge into a powerhouse. In the ‘90s, EDAC (Electronic Design Automation Consortium, the predecessor to the ESD Alliance) wasn't interested in tracking IP. As the IP market started growing, EDAC was all over it because it helped pump up the size of the electronic design automation (EDA) industry. Suddenly, IP had become a big enough industry that people were starting to care. And of course, there were successful public companies like Arm, Rambus, Artisan, and others licensing IP. It was fun being part of that.The low points were the hard part. While everything was new for us, it was also new for customers. They had intense resistance to licensing IP that many viewed as product development. They would want the IP company to develop something under a consulting or NRE contract, and then they would own the product and all the IP around it. They wanted to own everything. Many companies had that mentality in the early days and were resistant to licensing or paying royalties.As a side note, Gary Smith, former analyst for Dataquest, now Gartner Group, who died in 2015, and I had an ongoing debate. We went to lunch quite frequently and he would say, “IP is great, but you aren't IP. You are a standard cell, and it is not IP.” It was one of his standard statements.He would make various presentations, and I would argue: “You can't think of it as a cell, think of it as an entire library. It's an entire library with all the design views, layouts, test and qualification data, and everything else. That’s intellectual property. Plenty of intellectual property goes into developing it.”He eventually changed his mind and agreed when he saw the revenue and the value –– IP companies do it better and cheaper than in-house development.A final high point was getting the idea and value of IP across to customers. Smith: At what point did people start to believe IP was a real market and they could trust a vendor? Lewis: I don't know if there was an inflection point. More and more people started getting used to the idea that IP was an industry. Arm was probably the major catalyst. Artisan had two different engagement models. One was the integrated device manufacturer (IDM) model. Mark Templeton, co-founder and CEO of Artisan who died in 2016, and Lucio Lanza, Managing Partner of Lanza techVentures and Artisan’s Chairman, are credited with developing the royalty model and the intellectual property category. They drove it with the IDM model. Executive Advisor Jeff LewisCustomers knew they were paying for a license, understood the terms and became both the licenser and the user of this technology. It was different when Artisan went to the foundry model, which extended the IDM model to the rapidly growing foundry space. In this model, Artisan had the ability to widely disseminate its IP to all the foundry customers for free. However, calling it a “free library” is a misnomer, because often overlooked in this process is that the foundry paid up front for every one of those libraries, and it also paid a royalty on each design that used them. Artisan was profitable from day one by building a library or memory compiler. The engagement model was one where Artisan could proliferate these to the foundry’s users. They would get the library, and the royalty would come from the foundry. Users were beneficiaries – they had a simple license agreement, but unless they needed some customization, they weren't writing checks to Artisan.From the user’s perspective, it was great. They got free libraries and IP. That helped open people’s eyes to the model that could be a good thing. Artisan had 1,000 users at one point, and it helped drive the proliferation of IP use in the industry.Smith: Is that foundry model still in place? Lewis: Largely, yes, with some exceptions because foundries have a standard library that can be used. They have some specialized IP that customers license. While there are variations, foundries provide libraries to their customers. TSMC has engineers developing libraries for its own processes. For a long time, Artisan was the standard IP provider for most of the foundries. Smith: How did companies overcome verifying and testing IP? Were engineers skeptical about buying from an unknown/unproven company? Lewis: This is an important and critical question. Engineers were skeptical about buying from an unknown or unproven company. Artisan’s library quality was our biggest selling point, and it was the same with Arm and Rambus. Size and reputation were a huge advantage.The key was to have a major win that demonstrated your bona fides, and our biggest early win was our work on the Sony PlayStation. At that time, LSI Logic was developing the chips for the PlayStation, but was looking to outsource some of the critical blocks, such as the embedded SRAMs. Sony engineers were nervous and wanted to meet the IP companies to see what they were doing, because the fate of their chip was resting on these little companies. Artisan developed high-performance embedded SRAMs that replaced the existing LSI SRAMs. Our memories were about half the size of the LSI SRAMs, higher performance, and worked the first time.What’s instructive is how Artisan later got the foundry relationships going and sold libraries. Enabling first-time success is a quality argument, because the design would work the first time. At that time, almost every foundry library had bugs in them that caused silicon failures after tape-out. Our primary argument to engage foundries was our impeccable QA story. We had customer testimonials confirming that the foundries would not have library-related failures. When foundries scheduled a volume like a PlayStation ramp, they couldn’t afford a production “bubble” or “hole” in their production schedule from a library bug causing a chip not to work and requiring a re-spin.That's why the argument on quality and first-time success was critical to TSMC.One more thing on quality, and this ties specifically to Artisan and almost all IP companies. Any company that focuses on a mass proliferation model must ensure their product has no quality problems. Mass proliferation needs to be as low touch as possible, so engineers can use it without constantly calling for support. Quality is an absolute fundamental before mass distribution, because the fastest way to go bankrupt is to massively proliferate a faulty product. Smith: According to the EDMD report two years ago, IP surpassed front-end EDA tools as the highest category. Are we now shifting into a world where IP in the form of chiplets may become the dominant player? Lewis: I think the shift is coming. These are different incarnations of Moore's Law and the Carver Mead-structured VLSI. Sometimes the structure may be a chiplet, or the structure may be embedded.Is it virtual or is it actual? Engineers will make tradeoffs with pros and cons of embedding it or keeping it separate. The deciding factor is which silicon process is best and how it will be implemented. The SEMI EDMD report’s tracking of the Semiconductor Intellectual Property (SIP) and its rise to one of the market’s leading category. Smith: You worked for several IP companies that were offering process-related IP. That's a completely different type of market selling cycle, correct? Lewis: It is, because I focused on technology licenses for manufacturing processes, as opposed to the much more understood design IP that was developed for the existing manufacturing processes. Getting inserted into a company’s manufacturing process is much more difficult and challenging.If a company is licensing a technology that modifies the front-end process, then the process parameters will change, presumably for the better. The re-optimization can be like whack-a-mole. While some parameters get better, some may get worse, and further re-optimization can be required. This can go through several cycles until the process converges. This also means that all existing IP must be recharacterized and/or redesigned, which is why it is best to insert a new technology at the beginning of the node development rather than as a retrofit.Adding new process technologies is inherently difficult unless it’s a separable piece. For example, many new memories such as ReRAM or MRAM are licensed technology and separable, because they are set up separately in the metal stack. They don't touch the transistors.For a long time now, companies have been able to pick and choose whether to do in-house development or procure design IP from a third party. We're now starting to see the same thing in process development, because they are getting so complex, and no one can be an expert in all areas. I see process IP as paralleling the early days of design IP, but with a 30-year delay. Back then, most customers were reluctant to procure design IP because they felt: “We can do it all in-house.” Almost no one says that today, and I think this gradual acceptance will apply to process IP as well.Smith: Should Mark Templeton be considered the innovator and creator of the IP industry? Lewis: I’m not sure there’s anything I can say about him that hasn’t been said already. He was a great guy and an important thinker. I credit him for doing an excellent job crafting a successful company. And, of course, Lucio Lanza was absolutely instrumental as well. He pushed Artisan to do royalties, and Mark helped drive it to fruition.About Jeff LewisJeff Lewis is one of the pioneers of the semiconductor IP industry, participating since its inception in the mid-1990s. Lewis is currently Executive Advisor for senior management and investors for semiconductor and AI companies. He was previously an operating executive serving as Senior Vice President of Business Development and Marketing at Atomera Incorporated, Spin Transfer Technologies, SuVolta Inc., and Innovative Silicon Technologies, and held operating roles at Synopsys, VLSI Technology, and HP. Lewis earned an MBA from the UC Berkeley Haas School of Business, and has a bachelor’s degree in electrical engineering, and a bachelor’s degree in economics from UC Berkeley.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

Silicon carbide (SiC), with its wide band gap and high thermal conductivity, is increasingly favored for semiconductor power applications across several fast-growing industries. Its ability to operate at higher voltages and frequencies enables significant efficiency gains, particularly in e-mobility, where SiC offers key advantages in size, weight, and speed compared to traditional silicon-based power devices.However, as promising as SiC is, the industry still faces critical challenges in scaling to meet growing demand. Key barriers include cost, reliability, and manufacturing capacity, all of which must be addressed for SiC to fully mature.SEMI spoke with Entegris Senior Director - Advanced Technology Engagements, Office of the CTO Mark Puttock, Ph.D., to discuss the challenges of scaling SiC power chip manufacturing from a material supplier’s perspective. Puttock shared insights ahead of his presentation at the Entegris session, Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain, taking place on November 14, 2024, at SEMICON Europa in Munich, Germany. Don’t miss the opportunity to engage with experts from Entegris and other industry leaders. Registration is now open. SEMI: Global megatrends like environmental crises and AI drive the necessity for SiC power semiconductors. What is the current status? Puttock: The increasing demand for efficient power electronics — fueled by global megatrends such as vehicle electrification, environmental de-carbonization, and the rise of power-hungry AI chips — drives the necessity of wide bandgap semiconductors. SiC offers advantages of weight, size, and speed over traditional silicon (Si) solutions, which are particularly vital in automotive applications 600V and above. However, SiC chip manufacturing has not reached the maturity of silicon-based processing. Greater maturity will help reduce costs, which will accelerate adoption in the market.SEMI: What are the main challenges in scaling SiC?Puttock: Challenges in scaling SiC power chip manufacturing to high volumes are not surprising. That’s because high volume producers have not been operating long enough to resolve early-stage issues. From a material perspective, SiC is more challenging to manage compared to Si. The challenges we identify include:Chemical Mechanical Planarization (CMP): SiC is nearly as hard as diamond and significantly harder than Si, making it challenging to achieve a high removal rate while maintaining both planarity and low defectivity. This step is crucial toward the end of the wafering process and before the epitaxial growth of device layers.Handling: SiC is more brittle than Si, making it more susceptible to damage or breakage.Implantation: SiC is more difficult to implant than Si, requiring higher temperatures and the use of aluminum instead of boron as a P-type implant species. Additionally, it is a significant challenge to achieve a reliable aluminum source with a long and stable lifetime.Thermal Processing for Wafer Growth and Epitaxy Processes: SiC processes run hotter than Si ( 2000° C for wafering, 1500° C for epitaxial growth), demanding resilient chamber parts to achieve good lifetimes.Sustainability: Because SiC is extremely hard, the CMP process requires significant amounts of slurry. Improving slurry recycling and wastewater management continues to be a challenge.On October 29, we will address these issues in our webinar, “Challenges in Scaling SiC Power Chip Manufacturing: A Material Supplier's Perspective” This session will provide valuable insights and considerations for advancing maturity in high-volume SiC power chip manufacturing. SEMI: Can you elaborate on the challenges associated with CMP for SiC wafers? Puttock: SiC wafers are challenging to process, requiring specialized materials and methods compared to traditional silicon. Defects in the SiC wafer crystal during non-optimized CMP processing can propagate into the device epitaxial layers. This leads to yield loss, increased electrical resistance, reduced performance, and wasted power.SiC wafers must be cut, ground, lapped, and polished to create the necessary surface properties before depositing active layers. As the demand for these devices grows, optimizing the CMP process is essential to ensure the desired surface quality and planarity required for device fabrication. For a deeper understanding of these challenges, we recommend downloading our latest white paper, “Solving CMP Challenges in High-Volume SiC Production,” which covers:Achieving maximum smoothness with high removal ratesReducing the total cost of ownership Optimizing CMP slurry and pads for the unique wafer chemistry and topology of SiC wafersSEMI: What do you mean by optimizing slurry for SiC CMP?Puttock: CMP slurry typically consists of abrasive nanoparticle powder dispersed in a chemically reactive solution. The objective is to achieve a smooth, defect-free surface (less than 1 A Ra) with a high removal rate (greater than 7 µm/m).Traditionally, achieving high removal rates and smooth surfaces required two separate slurries. This approach sometimes forced SiC wafer manufacturers to choose a defect-free surface over a faster, more efficient CMP process, depending on their fab capabilities. Today, optimization allows SiC wafer manufacturers to achieve both high polishing capacity and good final surface quality using a single slurry.Additionally, while the slurry is the most critical part of the CMP process, the pad must be compatible with the application. This ensures the desired planarity while also preventing scratches or contamination of the SiC wafer surface. Research shows that optimized thermoplastic polyurethane CMP pads outperform traditional thermoset polyurethane pads. The optimized pads minimize surface damage and enhance removal rates due to their bulk hardness.SEMI: What are the future challenges for SiC devices? Puttock: SiC devices are increasingly favored for their superior energy efficiency and reduced environmental impact. However, the SiC manufacturing process presents challenges due to its high-temperature operations, which consumes significant amounts of energy and shortens the lifespan of chamber components. To address this, improving efficiency in these processes will be crucial in the coming years.Recycling is another important challenge. For example, CMP slurries present an opportunity for water recycling and conservation. At Entegris, we are committed to this issue and are actively collaborating with key industry players to enhance material circularity and prioritize sustainability in our new product development.SEMI: How is Entegris contributing to advancements in SiC technology, and what initiatives or partnerships do you have planned for the near future? Puttock: Entegris is an active member of the SEMI Global Automotive Advisory Council (GAAC) and participates in a working group focused on SiC with key industry leaders such as Volkswagen, BMW, Porsche Consulting, onsemi, Infineon, STMicroelectronics, and others. Our engagement spans the entire semiconductor supply chain, collaborating with integrated device manufacturers and original equipment manufacturers in fabs worldwide. Additionally, we recently announced our latest long-term agreement with onsemi, which underscores our commitment to advancing SiC technology.SEMI: What are your expectations regarding your participation at SEMICON Europa? Puttock: SEMICON Europa is a unique platform to connect with the semiconductor and automotive ecosystems. Last year, we organized a highly successful SiC session in collaboration with SEMI at both SEMICON West and SEMICON Europa, focusing on “Connecting the Automotive Ecosystem Towards More Mature SiC Manufacturing.”This year, we will continue the discussion with industry leaders during our session, “Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain.” Our goal is to provide insights and propose solutions that will enable SiC power chips to achieve their anticipated role in future technology ecosystems.We will present alongside Porsche Consulting, and the talks will be followed by a panel discussion that will explore the current state and future prospects of SiC technology in power electronics. We invite visitors to join us at the Executive Forum on Thursday, November 14, from 1:40 – 3:00 p.m. and to visit us at Silicon Saxony booth 219 in Hall C1.About Mark PuttockMark Puttock, Ph.D., is the senior director of advanced technology engagements in the office of the CTO at Entegris. He has worked in the semiconductor industry for over 30 years with a background in physics and plasma processing. As a team member of the Entegris CTO office since 2014, Mark has followed technology trends and collaborated with Entegris’ global product development teams to develop timely and differentiated new materials, chemistries, and components for all the world’s semiconductor manufacturers. Maria Daniela Perez is Communications Manager at SEMI Europe.

Use of machine learning and artificial intelligence (ML/AI) is on an exponential rise across fields1 including all aspects of the semiconductor industry. In the last decade, the use of ML/AI exploded in the areas of speech recognition, facial recognition, smart phone features, search engines and now large language models like ChatGPT, Bard AI, and CoPilot. The ML/AI growth has been enabled by massive data storage capacity and increased compute performance, leading to projections for the semiconductor industry to reach over $1 trillion in annual revenue by 2030, with about 50% of the industry’s growth related to GenAI2. Figure 1: McKinsey Company on GenAI driving semiconductor industry growthAs semiconductor manufacturing drives toward Industry 4.0, SEMI member companies have a vision of Industry 5.0, truly adaptive manufacturing, integrating human creativity with robotic precision enabled by AI. Along that path, automation and data exchange in every step of manufacturing is essential, with data acquisition, data integrity and relevance, and operational Digital Twins3 as defined steppingstones to the factory of the future.Based on growing member interest in ML/AI, in 2019, SEMI assembled technology communities that quickly engaged in AI discussions and proofs of concept, discovering gaps in the path to Industry 4.0. Successful demonstrations of the value of AI in chip manufacturing process development and factory efficiency, not to mention GenAI uses in society, hastened the pace to produce faster, more powerful chips to accommodate the computation and communication requirements. Recognizing the industry opportunity and the mounting role AI plays in the semiconductor supply chain, SEMI initiated several thought leadership efforts, namely the Smart Manufacturing Initiative, Smart Data-AI Initiative, and the Future of Computing think tank.Smart Manufacturing According to the SEMI World Fab Forecast, over 100 new and expanded wafer fabs will begin volume production by 2027. This massive capacity expansion will need to achieve the highest possible operational efficiency and performance. To this end, the Smart Manufacturing Initiative is a technology community with over 120 member companies collaborating pre-competitively to transform manufacturing. The SEMI Smart Manufacturing Global Executive Committee (GEC), outlined a roadmap vision for the cognitive factory of the future based-on technology, sustainability and future talent. The GEC has been working with members to realize that vision. Figure 2 describes this vision in terms of the technology progression needed and the approximate timeline for implementation by most manufacturers. The proliferation of this vision through Smart Manufacturing Forums at SEMICON events around the globe, newsletters and blogs has garnered enormous interest and participation in the initiative and is central to the mission of connecting and raising awareness within the ecosystem. Figure 2: AI-Driven Smart Factory (Point Systems to Autonomous Solutions) To move the needle on this vision, industry experts in the initiative successfully created and launched the Industry 4.0 Readiness Assessment Model (IRAM) to help assess technology deployment progress. IRAM adoption is steadily growing. Modern front-end and back-end lines produce an extraordinary amount of multi-modal data from a variety of sources, and this is key to success in unlocking the potential of AI in manufacturing environments. The initiative’s global working groups on Data Architectures and Smart Control Room among others are working towards a holistic Cognitive Factory framework uniting the vertical and horizontal flow of information. Integral to the Cognitive Factory are smart manufacturing standards, that will accelerate the vision outlined above, and without which local solutions are unlikely to scale.In 2023, the Smart Manufacturing Initiative brought together industry leaders in a unique Digital Twin workshop to align on the state of semiconductor development and usage. The key takeaways from this workshop are captured in a white paper that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months. that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months.The GEC has identified critical interrelationships in addition to the technology focus. At the intersection with sustainability, the initiative has formed a collaborative task force with the SEMI Semiconductor Climate Consortium (SCC) to develop a bottom-up technology roadmap that can be used as a blueprint for device makers to meet their proclaimed sustainability goals faster. The task force organized a technical session at SEMICON West 2024 and will be releasing a white paper in the near future. Similarly, the initiative is working with the SEMI Foundation to identify necessary future skills and to make training available through SEMI University. Smart Data AI – Applying AI to Semiconductor OperationsSEMI’s Smart Data-AI Initiative started by assembling a group of interested companies to explore the pivotal role AI could play in the industry and to address the criticality of data. All stakeholders agreed that a formidable challenge was (and still is) the integrity of that data and the security of sharing that data, which is considered IP to most. The optimal implementation of ML/AI techniques can only be gained by access to the comprehensive data set which is owned by numerous supply chain partners. Consequently, semiconductor R D, process and design have not yet realized the full benefit of Data-AI advances. In response, the initiative developed a framework to create value for members and support industry progress. Four pillars underpinning the strategy are:Educating stakeholdersBuilding communitiesExecuting proof-of-concept projectsDeveloping industry standardsTo explore the data challenges the subject matter experts highlighted, a collaborative proof-of-concept (POC) project was proposed in 2019 and accepted by the initiative's partners at Army Research Laboratories4 along with academic and industry partners. The project has completed two phases and is starting on its third phase under the expert guidance of an Industry Advisory Council (IAC) comprised of leaders in the Smart Data-AI community.The POC project, being conducted by principal investigators at Cornell University, demonstrated significant accomplishments from the first two phases, including:An AI model to predict device geometry by optimizing photolithography and plasma etching processesInitial demonstration of secure data-sharing techniques with software-hardware co-optimizationInnovative metrology ideas to train AI algorithms rapidlyStudents trained in cross-disciplinary skills to address the industry’s critical talent shortageFurthermore, the visionary objectives laid out at the initial stages of the POC proved to be synergistic with the strategic goals of the CHIPS Act5, which articulates the need for “collecting, aggregating, and sharing data sets that enable benchmarking and operational improvements, tools development, the creation of digital twins, and training AI models,” and that “the NSTC could develop a methodology for the voluntary sharing of data that protects the proprietary component and national security while enabling access to appropriate performance data.” Phase 3, to be completed by August 2025, will advance the state-of-the-art toward the following specific objectives:A framework to create and integrate Digital Twins of semiconductor R D and manufacturing process toolsAbility to explore processes and generate virtual devices swiftlyDefined interfaces to combine models for each process module or toolAccurate AI-based models for executing virtual process flows to build virtual devicesAdvanced solutions for secure data-sharing across the ecosystem – for example, federated learning where raw data is protected for each entity by building models locally, and only the outputs of the local models are used to build flow-level AI modelsFoundation for future industry standards for secure data-sharing and for interfaces in the virtual innovation environmentSEMI continues to build the collaborative community for Data-AI and strives to synergize with broader efforts such as the Digital Twin Manufacturing Institute, NSTC, and NAPMP in the U.S., and international standards development. Smart Data AI – System-level Innovation for AI – Future of ComputingThe cross-collaborative and synergistic objectives of Smart Manufacturing, the Smart Data-AI proof-of-concept work, and SEMI Standards merge to advance the state-of-the-art. The objective is to help members realize the full value of technology and innovation. In addition to improving semiconductor operations using AI, the efforts also strive to enable SEMI members to participate in, and ultimately profit from, market growth opportunities. Continued progress in AI is crucial both for the industry’s march towards $1 trillion in annual revenue, and for continuing to realize AI’s benefits to society.There are some hurdles to overcome in such a dynamic market. AI models, and the data they process, are outpacing hardware advances, posing a major roadblock for continued progress. As GenAI becomes more pervasive, the performance and power challenges continue to multiply, and require significant innovation in both hardware and software. While individual companies will develop competitive products in this domain, the entire ecosystem needs to evolve in a synergistic manner. As a global industry association, SEMI can play an important role in ensuring this. SEMI started a series of workshops and technology sessions to develop the community and identify opportunities and challenges. The first in this series was a joint workshop with McKinsey Co., held in October 2023, with a focus on innovations in “Domain-Specific Architectures.” Strategically, it brought together thought leaders from three diverse communities - start-ups, investors, and SEMI member companies across the supply chain. This was followed by an overcapacity audience at the Future of Computing session at SEMICON West 2024, where we explored AI-specific hardware with leaders in academia and industry. The Initiative’s next planned event in October 2024 is a focused workshop that is designed to be highly interactive and bring together visionaries and thought leaders from across the value chain – materials, devices, architectures, algorithms, and critical enabling technologies such as photonics, chiplets, advanced packaging, and 3D and heterogeneous integration. The overarching goal is to identify pre-competitive collaborative actions that would help the entire industry. The “Future of Computing” is the broad path to the industry’s future success. While AI systems are the current major wave on this path, future waves may be about heterogeneous integration of photonics and other components, and ultimately, quantum technologies joining the mainstream. SEMI continues to monitor these future trends, strengthen the ecosystem and enable innovation through pre-competitive collaboration, and accelerate implementation through standards.SEMI is fostering today’s collaborations while helping the industry navigate the future of electronics.Melissa Grupen-Shemansky is CTO at SEMI, Pushkar Apte is a Strategic Technology Advisor and Leader of the SEMI Smart Data-AI Initiative, and Mark da Silva is Senior Director of the SEMI Smart Manufacturing Initiative.Definitions and References:1https://arxiv.org/abs/2405.15828 Eamon Duede, William Dolan, Andre Bauer, Ian Foster, Karim Lakhani2McKinsey Company3Digital Twins for semiconductor manufacturing operations are dynamic, predictive, data-driven virtual models of a physical asset, process, or an entire factory, constantly synchronized with its real-world counterpart through real-time data streams and analytics4Research was sponsored by the Army Research Laboratory and was accomplished under Cooperative Agreement Number W911NF-19-2-0345. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Laboratory or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.5“A Vision and Strategy for The National Semiconductor Technology Center (NSTC)” published by the CHIPS R D Office.

Jose Fernandez, U.S. Under Secretary of State for Economic Growth, Energy, and the Environment, sat down with Joe Stockunas, President of SEMI Americas, for a fireside chat on the CEO Summit keynote stage at SEMICON West 2024. In the Securing Critical Supply Chains for the 21st Century discussion, Fernandez emphasized the need to form partnerships to address vulnerabilities as the key to creating stable supply chains. It’s important to band together, he said, to protect our standards, values, and democracy. Diversifying the Global Mineral Supply ChainBecause chip fabricators depend on minerals like germanium, gallium, arsenic, indium, and rare earth elements, he highlighted how imperative it is for the industry to access them sustainably. To accomplish this, he stressed the importance of protection against supply chain bottlenecks in the mineral market. “According to a number of experts, we’re going to need 42x the amount of lithium by 2050, 25x the amount of manganese, and 25x the amount of cobalt,” he said. “Those minerals are basically controlled by one country, and that's a vulnerability.”To address these concerns, he shared that the State Department is working to strengthen the upstream and downstream portions of the semiconductor value chain, with the goal of supporting economic security across the globe. Foreign export controls, he said, have led to supply chain disruptions of key minerals, and bans on rare earth elements, processing equipment, and other technologies. As evidence of the State Department’s efforts to diversify, he highlighted the Minerals Security Partnership (MSP) and its work to seek mineral alternatives. Led by the U.S., it currently includes 13 other countries plus the European Union. Partnership and Investment Opportunities To further secure the industry's supply chain, Fernandez discussed the State Department’s efforts to partner with mining countries with untapped semiconductor resources. These countries, he said, also want alternate options for securing critical minerals. Fernandez highlighted Latin America as a key nearshoring focus area, pointing to the Americas Partnership for Economic Prosperity (APEP) as a solution for addressing obstacles to investment in the region. Obstacles, he said, include education levels, insecurity, and rule of law.To overcome such hurdles, he stressed the importance of fostering economic conditions that will attract investments, emphasizing the importance of workforce development initiatives and private sector involvement. “We don’t have enough trained workers in the U.S., and we certainly don’t have enough trained workers abroad,” he said. Fernandez shared that workforce development programs are being established through the U.S. Department of State International Technology Security and Innovation (ITSI) Fund, as well as private sector efforts and university partnerships. Currently, seven countries have been selected for ITSI funding, he said. “We’ve partnered with a number of universities to address the workforce gaps we see in our ITSI partners,” he said. “We’ve created workforce seminars, and we’re going to spend more time training the labor force.” These efforts supplement the work of the SEMI Foundation to develop a holistic workforce development program for the global semiconductor industry.Preventing Chips From Entering RussiaWith U.S. chips crossing into Russia through third parties, Stockunas asked Fernandez how the semiconductor industry could help address this. Despite existing sanctions against Russia, Fernandez shared that Russia still managed to import $1.7 billion worth of microchips from both the U.S. and Europe in 2023. To help slow this down, he highlighted additional due diligence for companies whose products often make their way into the country. The federal government, he said, speaks with these companies about complying beyond what the law requires.Fernandez shared that private sector cooperation with more stringent standards has been positive, noting that some companies have cut hundreds of distributors to further aid in prevention. In addition, he mentioned that sanctions have made a promising impact overall.“[Russia] has had to use outdated equipment, they’re engaging in counterfeiting, and they’re getting help from other countries,” he said. ​​Official SEMICON West Podcast In a podcast with Francoise von Trapp of 3D InCites recorded at SEMICON West, Fernandez discussed critical mineral partnerships, benefits and setbacks of regional supply chains, and chip sanctions against Russia. To learn more, check out the podcast interview with 3D InCites. SEMI Global AdvocacyDiscover how SEMI Global Advocacy Public Policy supports the microelectronics industry across trade, taxes, talent, and R D.John Cooney is Vice President of Global Advocacy and Public Policy at SEMI.

Presentations at this year’s FLEX Conference illustrated the ongoing development of manufacturing tools and processes, materials, and test and reliability evaluation techniques for the growing field of hybrid electronics, which includes printed electronics and flexible hybrid electronics (FHE). Additionally, the field includes the use of additive manufacturing processes for electronics packaging and system assembly, from die attach to flexible printed circuits.Hosted by FlexTech, a SEMI Strategic Technology Community, the conference provides an opportunity for the device making supply chain to connect to R D, design and manufacturing innovations. A review of some of the key developments highlighted in FLEX presentations follows.Innovations in Flexible Printed CircuitsTokyo-based Elephantech has been focused on using advanced inkjet systems to produce flexible printed circuits. Using additive methods instead of subtractive to produce PCBs can enable reductions in carbon footprint, copper usage and water consumption. In order to achieve these benefits, Elephantech has developed processes for combining inkjet printing of metals and electroless plating. The company synthesizes copper nano particles, which it uses to formulate metal ink. It has implemented artificial intelligence to increase print accuracy, showing the capability of average drop position error of less than 2μm, and depositing 20μm droplets into 40μm grooves and wells (Fig 1).Fig. 1. Elephantech inkjet results showing ~2μm precision and prototypes with 50μm line widthExamples of Elephantech’s use of flexible printed circuit technology include a set of switches for a curved monitor and a pressure sensor with reduced footprint and component count. The company intends to directly compete with larger, rigid PCBs, and is developing a mass-production system with 57,840 nozzles that can process sheet sizes of 500 x 830 mm.Traditional processes for component attach on PCBs include mass reflow ovens, thermal compression bonding, and spot laser reflow. Laserssel has developed laser selective reflow, which promises warpage- and damage-free bonding at increased processing speeds. In addition to improving the productivity of rigid PCB production, the laser selective reflow could also enable in-line processing of roll-to-roll flexible printed circuits, replacing the use of trays for bonding to flexible printed circuits.Scrona, which spun out from ETH Zurich, has developed MEMS-based printheads to improve electrohydrodynamic (EHD) printing. By using an electric field to pull droplets out of the print nozzle, EHD can enable much higher print resolution (sub-micron, compared to tens of microns), and enable the use of higher viscosity inks than would be possible with traditional inkjet heads. While EHD has been under development for some time, its application has been limited by crosstalk, in which the electric fields of adjacent nozzles interact with each other, and the requirement for the nozzle to be within tens of microns from the substrate to enable high print accuracy.Scrona’s MEMS-based nozzles address these EHD problems by shielding adjacent nozzles to prevent crosstalk and by creating a uniform electric acceleration field, which increases print distance to the order of a millimeter. The company has used its system to print a variety of inks on different substrates, as well as conformal printing on 3D surfaces (Fig. 2).Fig. 2. Example of printing silver wires across a polished glass edge; line pitch 25μm, glass thickness 1mmThe Rochester Institute of Technology (RIT) has been developing an additive technique called liquid metal droplet jetting, which can deposit metal traces functionally equivalent to solid wires. The process uses metal wire as a feedstock, which is a fraction of the cost of nanoparticle metals. While tin, zinc, and aluminum have been used, silver and copper are still under development. The wire is melted in a micro-crucible, which feeds a nozzle; metal droplets are then jetted on demand in an argon environment to prevent oxidation (Fig. 3, l). Upon hitting the substrate, the drops solidify into metal traces equivalent to solid wire, quickly enough to avoid melting flexible films, and without curing or drying.Several methods have been explored to eject the jets from the nozzle, including magnetohydrodynamic using electromagnetic pulses, piezo-actuated pistons, and pneumatic jetting using compressed gas (Fig. 3, r). These techniques range from high-jetting-frequency and high-cost to simple and low-cost but low-frequency. Higher frequency enables overlap of droplets, increasing conductivity, and reduced processing time.Fig. 3. Concept of liquid metal droplet jetting (l); pneumatic droplet ejection approach (r)In addition to ongoing development of deposition tools and processes, the material set for additively printed electronics continues to expand. Iris Light Technologies, which spun out of Argonne National Lab and Northwestern University, is developing photonic inks for wafer-scale production of active devices including photodetectors, LEDs, and lasers. The semiconductor-based ink can be deposited via aerosol jet onto silicon wafers. Iris Light is focused on 2D semiconductors, specifically black phosphorous, which has a wider spectral coverage than graphene, is tunable in emission and absorption, and has high mobility.An example of the broadening of the additive manufacturing supply chain, Kraetonics has developed software for creating slices to be used in designing 3D-printed structures and elements. The software enables manufacturing 3D volumetric circuits with reduced size, weight, and power compared to 2D PCBs. The process involves 3D printing of hybrid mechanical-electrical assemblies such as circuits and antennas.Innovations in Test and ReliabilityAn area of active interest in the hybrid electronics community is that of test and reliability. American Semiconductor, a developer of flexible circuitry, and Bayflex, a value-added partner of Japanese equipment company Yuasa, are conducting a project on dynamic harsh environmental FHE reliability testing. The goal is to identify root causes of FHE material and system failures.The companies are developing extended temperature and humidity tests to determine FHE system lifetimes and identify causes of failures from physically deforming FHE materials and systems in harsh temperature and humidity environments. Materials under consideration for testing include:Copper on polyimide substrate with a small outline package IC and surface-mounted componentsNobleflexTM, a multilayer substrate with gold on polyimide in development for medical devicesSilver on PET substrate, with small outline package IC.The team is soliciting other test devices and is planning to coordinate with ongoing development of FHE test standards coordinated by SEMI.Henkel reported on an investigation of accelerated temperature cycling test methods, in which the company applied different combinations of temperature range, stress, and frequency of mechanical force in an effort to reduce cycle time for testing component attach reliability. The study was able to achieve similar failure modes using an accelerated test method in the case of a bonding position shift in which cracking of the die attach film was the failure mode (Fig. 4, approach 4). The study found the greatest acceleration in the case of reduced thermal shock cycles (Fig. 4, approach 1).Fig. 4. Approaches evaluated for accelerated testing of component attach.Engineering consulting firm Exponent presented the results of a study on mechanical testing for characterizing fatigue performance of flexible electronics, conducted with continuous monitoring of fatigue for 6-pin flexible flat cables from seven different vendors. Exponent found that continuous monitoring during bending fatigue testing provided greater resolution in test results including detection of intermittent failure in each sample. The study also found that strain amplitude was a critical factor for determining fatigue life, and that flat flexible cables with larger pitches showed improved fatigue performance.About SEMI FlexTechFlexTech, a SEMI Strategic Technology Community, promotes the growth, profitability and success of the flexible hybrid electronics industry by developing educational forums, directing research, and promoting technology innovation.SEMI FlexTech members benefit from speaking and business networking opportunities, introductions to key industry players, research reports, technical funding, access to end users and industry advocacy at FLEX Conferences.Gity Samadi is Director of SEMI research and development funding programs and SEMI FlexTech and SEMI Nano-Bio Materials Consortium (NBMC). Paul Semenza is an advisor to SEMI on special projects. He was previously with NextFlex, the Flexible Hybrid Electronics Manufacturing Innovation Institute.

John Kibarian, CEO and founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, is a keen observer of the semiconductor ecosystem. Since PDF Solutions sits between design and manufacturing, Kibarian shared unique perspectives on both in a recent discussion.Smith: What trends are you seeing in the semiconductor industry. Are there any that surprise you? Kibarian: We see several trends that have been going on for quite a while.As much as we hear Moore’s Law is dead, there's still a strong drive to get to advanced nodes. The benefits are harder to achieve and require more than geometry scaling, but demand for these advanced nodes continues to grow. Another emerging trend is the need for insatiable compute power in data centers to support the explosion in AI applications. In recent history, the mobile phone market has been the key driver of the push to new advanced nodes, but that is changing as the performance needs of data centers and AI applications are now driving the shift.Next, as companies are still learning from the disruptions in the supply chain due to the pandemic, there’s a tremendous amount of movement to make the supply chain more resilient by expanding sourcing options for critical products or test applications. This is happening in conjunction with significant investment in high-performance compute from many countries that want to bring silicon to their shores.The next trend is that electronics companies are looking to limit investing solely in China or the U.S. Their China Plus One or U.S. Plus One strategies results in adding significant additional infrastructure and overhead. If it's not done right, it will cost the industry more money. It will be hard to sustain the cost benefits and economies of scale of the current single source model just by brute force and adding human capital. A new approach is required to manage cost effectively smaller and globally distributed manufacturing facilities.The final trend is the general electrification of the economy. Cars are moving from internal combustion engines to electric. That means more and more of our energy needs are met with electricity, putting a premium on solar and batteries. Batteries require power conversion.Silicon such as high bandwidth semiconductors on silicon carbide and gallium nitride have a tremendous amount of capacity. What is interesting is how fast and aggressive China is in that part of the market; they could be a major producer of the technologies needed to support electrification. With our exposure to the China market as well as the European and U.S. markets, Chinese manufacturers have come up quickly, and we may see a world with more viable suppliers than originally anticipated.Smith: You mentioned data centers and AI. AI is everywhere and revolutionizing the semiconductor industry. EDA companies are talking about incorporating AI. What are you observing? Kibarian: AI is used for chips that are manufactured for use in data centers. For example, our customers use PDF analytics or the Exensio platform via the cloud to analyze large amount of manufacturing data and product or test engineering data. Without this type of automated solution, only a small proportion of these data sets would actually be utilized.Companies staff their product design and test engineering using a budget based on a percentage of revenue. If a company has billions of dollars of revenue, it will put so much more into product and test engineering. But how productive can these people be? Without AI, they can only use some simple reports and graphics to analyze the subset of data they are looking at. AI solutions such as PDF’s Guided Analytics capability apply sophisticated machine learning tools to analyze entire large data sets. AI is enabling engineers to be more productive by allowing them to work with large data sets that ultimately deliver better results in the products.The amount of compute keeps going up at a rate that outpaced the rate of geometric scaling. More compute power makes it cost effective to go through large data sets and identify what is relevant.Additionally, AI is helping semiconductor companies build products. A conventional compute system is chips assembled on boards. AI is making system-in-package take off.The production flow is more complex, as fabless companies are becoming system companies. Conversely, system companies are becoming fabless companies and manufacturers. In the past, they ordered parts from their foundry of choice. Essentially, the foundry was the system manufacturer, supplying package and test yields of 99%.Now companies are building systems in more complex packages potentially with foundry partners, but this requires getting known good die. High bandwidth memory or other components from other suppliers means the company must make sure these products are available at the right time. In essence, they are becoming manufacturers and changing the way customers manage the problem of product test. They're adding more test insertion points and using machine learning and AI to be more productive.Smith: Let’s talk about digital twins or creating virtual models of everything from chips to the whole system. How do you see the impact or effectiveness of digital twins in manufacturing? Kibarian: From a manufacturing perspective, digital twins had been models for chamber behavior on a processing tool like an etch tool or TCAD simulation of devices and structures.The problem is that purely physics-based digital twins don't exist, and we must utilize empirical data. The joke was that the modeling for tomorrow’s systems was based on yesterday's technology. Trying to have the physics catch up with the materials, device structures and behaviors is why it’s so expensive to develop new technology.Principles-based models will never catch up with production. We can model 90-nanometer technology, but it doesn’t work for one or two nanometer wafers. AI and machine learning – and ways of building models using more sophisticated algorithms – can help close that chasm, and that’s starting to happen at the R D level.In production, no one has yet achieved a good merger of the physics-based and AI-modeling worlds to create a virtual model. Virtual modeling is a big opportunity.The rate of change and improvement in algorithms in large language models moves fast because machine learning can scrape the Internet for data to build huge training sets. In the semiconductor world, however, data sources are typically siloed within organizations and often not shared with vendors. This limits the rate at which the industry can take full advantage of existing data and create tangible economic benefit.By and large, there is a lot of wasted capacity in semiconductor manufacturing. The operational effectiveness of factory equipment is up to 90-95%. The reality is that most factories today process product wafers 40-60% of the time – maybe 70-75% of the time on a test floor. It is critical for the industry to start leveraging new types of AI models to increase the productivity of its manufacturing capacity.The industry needs to look at how companies can share data to take advantage of more sophisticated AI and create a new kind of operational digital twins. If the industry doesn't make a change; it will only be the largest facilities with the largest datasets able to take advantage, leaving one or two winners, with the others not being competitive.Smith: Is it possible for the industry to come up with a standard or some way of sharing information to build better models without giving away the underlying proprietary data? Kibarian: We can look at computer science with technology like homomorphic encryption. The relationships between parameters remain, but the underlying numbers or raw data is not visible after encryption. Pharma and the medical industry have ways to add noise to the data while preserving the information, as required by the Health Insurance Portability and Accountability Act (HIPAA).Our industry has a knee jerk reaction when it comes to looking at how to take full advantage of data and prefers to solve it as if information and data is more proprietary than medical data or financial data. And I don't think that’s true.Bob Smith: Is the open-source movement destined to bring change to the industry? Kibarian: PDF is a big believer in open source when it comes to OS-level virtualization and Kubernetes versus proprietary alternatives. We also use open-source database technology like Cassandra but are skeptical of the value of open-source solutions for end-market verticals. Having an underlying open and available IT layer has tremendous value, because it means a more rapid rate of innovation and greater ability to adjust security vulnerabilities and patches versus proprietary systems.Smith: PDF sits right between manufacturing and design. On the EDA side, more collaboration is going on between designers and manufacturing. How would you bring these two domains closer together? Kibarian: That's a good question. My first instinct is to look at the largest design organizations and manufacturers. They often invest heavily to figure out how to get jobs done right. This results in the concentration of the industry on a smaller number of players and leads to less innovation. However, in the world of chiplets and advanced packaging, there are more opportunities to become a chiplet supplier, because the whole system doesn’t need to be built by a single company. A supplier of chiplets could sell it into many systemsFrom a system view, connecting the pieces together through software, data sharing and analytics could drive more productivity gains that will offset some of the natural headwinds. This needs to be addressed in a way that changes the paradigm with software and systems used to bring manufacturing and design closer together.About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

As more than 400 speakers took the stages at SEMICON West 2024, sustainability and workforce development stood out as two major focus areas. The second day of this year’s CEO Summit keynote program, themed Seizing the Global Opportunities and Challenges Ahead, featured sessions on both topics. One of the first sessions of the day was the Chief Sustainability Officer (CSO) panel discussion, titled Bracing for the Evolving Global Risk for the Semiconductor Ecosystem, moderated by Vice President of SEMI Global Sustainability Programs, Dr. Mousumi Bhat. Later that morning, Shari Liss, Vice President of SEMI Global Workforce Development Programs and Executive Director of the SEMI Foundation, moderated a fireside chat, Advocating for Real Change: Why Inclusion and Belonging Need to be Everyone’s Concern, with Sandra Mahadwar from KLA Corporation. Bhat and Liss were later interviewed for a podcast by Francoise von Trapp of 3D InCites to share additional insights on sustainability and workforce development, respectively. Bhat was also joined by Paul Kelly, COO of the New York Center for Research, Economic Advancement, Technology, Engineering, and Science (NY CREATES). Creating a More Sustainable Semiconductor Industry During their interview, both Bhat and Kelly emphasized that the industry will need to reduce its use of per and polyfluoroalkyl substances (PFAS) to sustainably innovate at today’s nanometer pace. For this reason, Kelly highlighted the importance of learning to balance current production demands with the health of climate.To achieve this balance, they discussed the efforts of the Semiconductor Climate Consortium (SCC). Much of the SCC’s efforts, they said, will focus on driving the industry toward net zero emissions. SEMI and NY CREATES announced a memorandum of understanding (MOU) at SEMICON West 2024 to promote sustainable practices within the industry, with a focus on PFAS reduction. Kelly pointed to the ability of SCC members to test new materials, gases, and chemicals at NY CREATES’ R D facilities in upstate New York to work toward replacing PFAS with more sustainable alternatives. Bhat also shared that this collaboration helps facilitate prototyping, experimentation, and tests and measurements for newer, more sustainable substances.Dr. Mousumi Bhat of SEMI and Dave Anderson of NY CREATES celebrate their organizations’ sustainability MOU at SEMICON West 2024.“The thought leadership comes from the Consortium, and the support on infrastructure comes from NY CREATES,” said Bhat. “This should become a blueprint to solve some of the challenging problems that we have in our industry.” When it comes to reducing emissions, Bhat mentioned two key objectives. The first, she said, is access to clean energy, and the second is the reduction of greenhouse gases. Bhat cited these as the issues that will take the longest for the industry to solve and pointed to the importance of industry collaboration and partnerships to support the needed experimentation. But while partnerships will bring the industry closer to net zero, both Bhat and Kelly cautioned that it won’t be reached overnight. “Much more needs to be done in the industry to reach that net zero goal,” said Kelly. “New chip technologies, new chemicals, and new processes are very much large leaps to achieving that. But right now, even some of the most advanced will only reduce [emissions] by 70%.” To help bridge this gap, Bhat encouraged others to join and participate in the SCC. “Rather than everybody doing a one-to-one experimentation in their own space and spending those resources, I would like to invite anyone that's not part of the climate consortium,” she said. “And [I invite] those that are part of the climate consortium to engage more actively, so that we are all accelerating the journey toward net zero.” Addressing the Talent Shortage This year’s SEMICON West also featured five keynote sessions dedicated to workforce development, as well as a Workforce Development Pavilion that included several talks around diversity, equity, inclusion, and belonging (DEIB). With the estimated one million jobs the industry will need to fill by 2030, Liss shared that every role is needed – from entry level all the way to Ph.D. researchers. “We need to try and bring in as many people as we can over the next few years,” said Liss. “The talent shortage is a global issue, not just a U.S. one.” Shari Liss of SEMI moderated the fireside chat at SEMICON West 2024 with Sandra Mahadwar from KLA Corporation.To begin to close the talent gap, Liss stressed the importance of educating children about the semiconductor industry. “We are just invisible to kids,” she said. “In every part of the globe, they carry chips in their hands all day every day, and they don’t know. So to me, breaking that barrier and making sure kids know about our work as an industry is going to be so critical to making this successful.” Liss also highlighted differences in workforce development programs across the world, noting that what works in one region may not translate to another. For example, apprenticeships are widely embraced in Europe, she said, but they’re a fairly new practice in the U.S. Conversely, she shared that veteran-focused programs wouldn’t work for some regions, but they’re a “powerful win” in the U.S. Each SEMICON show across the world, she shared, includes similar workforce development and DEIB programming, in addition to targeted sessions for students and HR professionals. Companies can interview for open positions at SEMICON shows as well. To learn more about SEMI’s workforce development initiatives and programming, visit semi foundation.org, or check out this overview of DEIB content at SEMICON West 2024. Samer Bahou is director of Marketing Communications at SEMI.

SEMI was honored to welcome U.S. Under Secretary of Commerce for Standards and Technology, Dr. Laurie E. Locascio, to the CEO Summit keynote stage at SEMICON West 2024 on Tuesday, July 9. Locascio, who also serves as the Director of the National Institute of Standards and Technology (NIST), delivered her morning CHIPS Act Update keynote address to a packed room of over 1,000 attendees at the Moscone Center in San Francisco.During her address, Locascio emphasized how far the U.S. chip industry has progressed since 2021. “Prior to 2022 and the passage of the CHIPS and Science Act, the U.S. produced 0% of the world's leading edge chips,” she said. “But now, after these proposed investments, we've changed the global landscape.”Industry Shifts from the CHIPS and Science ActDue to long delays and price increases resulting from supply chain vulnerabilities, Locascio shared that Congress began developing the CHIPS and Science Act with two key goals in mind. The first, she said, was to protect economic security, and the second, was to lower costs for American taxpayers. As part of the CHIPS and Science Act, CHIPS for America was established to advance semiconductor manufacturing in the U.S. CHIPS for America encompasses two offices: The CHIPS Research and Development Office, as well as the CHIPS Program Office - both of which are responsible for implementing CHIPS and Science Act law.CHIPS for America, said Locascio, couldn’t be another procurement program. Instead, it needed to be a purpose-driven approach to build domestic manufacturing capacity. Locascio highlighted that CHIPS for America galvanized several experts from the federal government, R D, and other core areas to work together to revitalize the U.S. semiconductor industry and increase capacity. To achieve this, Locascio pointed to CHIPS for America’s $30 billion in proposed direct funding and $25 billion in proposed direct loans.Locascio also noted diversity of technology as being essential for the American chip industry, citing how Intel, Micron, TSMC, and Samsung have recently expanded in the U.S., with SK Hynix planning to build a fab and R D facility in Indiana. No other economy in the world, she said, has more than two of these companies producing leading edge chips on its shores.“The total public and private investment from our four, leading-edge companies will equal roughly $300 billion between now and the end of the decade, far and away the most investment in new production in the history of the U.S. semiconductor industry,” said Locascio. Industry Investments on the HorizonTo further aid these efforts, Locascio mentioned CHIPS for America’s notice of intent to invest $1.6 billion in an open competition to accelerate advanced packaging domestically and encourage innovation. Funding will be directed toward five key R D areas, including equipment tools, power delivery, connector technology, chiplets, and Electronic Design Automation (EDA), she said. Additionally, Locascio shared that CHIPS for America recently announced its first preliminary memorandum of terms (PMT) to support the upstream supply chain, and shared plans to announce several more PMTs in the future. Lastly, Locascio revealed that CHIPS for America plans to release a model and process for bringing new facilities to life, in partnership with the National Semiconductor Technology Center (NSTC). NSTC members, she said, will gain access to partnership funds and state-of-the-art facilities to support the U.S. semiconductor industry. “Across all these efforts, from manufacturing incentives to research funding, to workforce development efforts, the U.S. must cultivate and build our competitive assets to protect and grow our technological leadership,” said Locascio.In a podcast with Francoise von Trapp of 3D InCites recorded at SEMICON West, Locascio discussed her career background, CHIPS Act investments and the path forward for the semiconductor industry in the U.S. To learn more, check out the podcast interview with 3D InCites. SEMI Global AdvocacyDiscover how SEMI Global Advocacy Public Policy supports the microelectronics industry across trade, taxes, talent, and R D.John Cooney is Vice President of Global Advocacy and Public Policy at SEMI.

Per- and polyfluoroalkyl substances (PFAS) are a large class of thousands of synthetic chemicals that are used throughout the semiconductor industry in the form of gases, liquids, and solid high-molecular weight polymers, due to their wide range of physical and chemical properties. PFAS contain carbon-fluorine bonds, which are one of the strongest chemical bonds in organic chemistry, allowing them to resist degradation and to cover long distances away from the source of their release.In recent years, the high persistence of PFAS in both the environment and the human body has encouraged the European Chemicals Agency (ECHA) to launch a PFAS restriction proposal aiming to regulate and eliminate their use over the next few years. The proposal is currently under assessment by ECHA’s scientific committees for Risk Assessment (RAC) and for Socio-Economic Analysis (SEAC).PFAS in the Semiconductor Industry The exceptional physiochemical properties of PFAS provide them a high degree of functionality in semiconductor manufacturing across the entire supply chain, and often the combination of their properties allows manufacturers to satisfy multiple and overlapping technical requirements.While the industry recognizes the importance of transitioning away from PFAS, and research to that effect is ongoing, current technological limitations do not allow the industry to manufacture semiconductors without the use of PFAS or to discover scientifically viable alternatives that can effectively substitute their use.At this point in time, no known alternatives exist for most of the uses of PFAS by the semiconductor industry. Alternative substances must be researched, invented and potentially applied into mass production to be recognized as viable alternatives. Many different pathways will have to be explored as PFAS are currently used across the entire supply chain for over 1,000 semiconductor applications, including articles, support equipment and fab operations, or as process chemicals.SEMI Europe—European Semiconductor Industry Association (ESIA) PFAS Research Workshop Considering the criticality of the PFAS issue for the semiconductor industry, SEMI and the European Semiconductor Industry Association (ESIA) have greatly strengthened their joint advocacy efforts over this past year concerning the ECHA’s PFAS restriction proposal.In this regard, SEMI and ESIA successfully organized a workshop in October 2023 with the relevant representatives of the European Commission (DG GROW, DG ENV, DG CNECT and DG RTD) to present and discuss in-depth the key technical evidence for the use of PFAS is the semiconductor sector. The discussions built upon the extensive technical evidence that was presented by SEMI and ESIA in their respective submissions for the six-month PFAS consultation facilitated by ECHA.Following the successful execution of this first workshop, there was a keen interest from the European Commission to enquire further upon the current state of play of research and development efforts in the field of PFAS detection, abatement, capture and destruction, circularity, recycling and alternativesFor this reason, after the first workshop, ESIA and SEMI collaborated to develop and deploy a joint PFAS Survey aimed at identifying the research priorities in PFAS from the perspective of their member companies. Based on the survey outcomes, the associations compiled the SEMI–ESIA PFAS Research Roadmap and officially presented it to the representatives of the European Commission during a follow-up workshop on 13th June 2024. Discussions at the workshop focused on the key research priorities for the semiconductor industry to discover potentially viable alternatives to the use of PFAS. In the upcoming legislative period, SEMI Europe will continue to engage with relevant stakeholders to contribute to the political debate and encourage a legislative framework that can enhance sustainability across industrial supply chains while preserving Europe’s technological competitive advantage. Get InvolvedGet involved in the SEMI PFAS Working Group! The SEMI PFAS Working Group is composed of industry technologists from leading companies across the global semiconductor manufacturing supply chain. The working group meets regularly to share intelligence and develop strategies to earn exemptions and/or extensions from regulators. Join SEMI in this crucial effort to enable the industry to continue manufacturing chips vital to the prosperity of the world by contacting [email protected]. Stefano Orlando is Manager Advocacy and Public Policy at SEMI Europe.

As the semiconductor industry works to attract talent to overcome its labor shortage, governments, educators, and the private sector must collaborate to make industry career opportunities more accessible for prospective employees. This concept provided the framework for a panel discussion during SEMI’s 35th annual Advanced Semiconductor Manufacturing Conference (ASMC) that took place in Albany, New York in mid-May.Despite extensive CHIPS and Science Act news coverage and escalating efforts to promote semiconductor career development initiatives, there’s still a tremendous amount of work to do, noted Fran Dillard, Vice President and Chief Diversity Inclusion Officer at Micron. “We're going to have to work to reduce barriers to this industry, and we have a chance to make a generational difference for American citizens,” she said. The panel, titled Talent Pipeline: Building a Sustainable and Diverse Semiconductor Workforce, featured Dillard and representatives from government and education who shared insights on growing the industry to fulfill unprecedented chip demand. Dillard was joined by Kylie Patterson, Chief Opportunity and Inclusion Officer at CHIPS for America; Kevin Younis, Chief Opportunity Officer and Executive Deputy Commissioner at Empire State Development; and Hector M. Rodriguez, Ph.D., Dean of Science, Technology, Engineering and Math at Hudson Valley Community College. Shari Liss, Executive Director of the SEMI Foundation, moderated the panel.Building the Future Together The need for extensive collaboration to bring semiconductor manufacturing back to the United States fueled the discussion. Patterson explained that given current investments in the semiconductor industry, the U.S. must double its workforce and triple its graduates in technical and construction-related fields. Overall, she estimated the industry will need to train around 100,000 new technicians.To achieve these goals, Rodriguez said that representatives from GlobalFoundries, the New York State Department of Labor, State University of New York, Center for Economic Growth, and the National Institute for Innovation and Technology, meet monthly to discuss on-the-job training programs for high school graduates and General Educational Development (GED) holders. He explained that by frequently evaluating training programs, they can quickly adjust curriculums if results don’t meet expectations. Younis said that bringing manufacturing back to the U.S. creates a unique alignment of interests between the government and the private sector. He highlighted the opportunity to work together to build the country’s manufacturing capacity, citing Empire State Development and Micron’s Green CHIPS Community Investment Fund for Central New York as an example of public and private collaboration. Part of the fund, he explained, will go toward workforce development. “We can focus on succeeding, with everyone marching in the same direction,” he said. Tapping Underrepresented Populations To find the talent needed to sustain the pace of semiconductor innovation, the panel stressed the importance of attracting people from all backgrounds and exposing them to the industry earlier in life. Dillard pointed out that women account for just 10-15% of workers in technical roles, and that percentage is even lower for people of color. “If we’re going to resource the semiconductor industry over the next 10-20 years, we’ve got to bring everyone with us,” she said.Helping those from underrepresented communities overcome barriers like limited access to childcare and transportation is important, said Rodriguez. He noted that wraparound services can be essential for transitioning these individuals into industry careers. Younis also highlighted Empire State Development’s One Network for Regional Advanced Manufacturing Partnerships (ON-RAMP) program, which will help provide these services in Upstate New York. If we’re going to get the people the industry needs, we must look for every opportunity, Rodriguez said, as they need to see that a great job is on the other side of the fence. Patterson said schoolchildren should be exposed to the semiconductor industry at a younger age, particularly girls and those from underrepresented groups. She cited a study about LEGO blocks, explaining that when the toy is introduced in primary school, boys are often excited, but girls are generally uncomfortable. “This is an example of the role of exposure,” she said. “If you’re not exposed to something, you have a lack of comfort, and that lack of comfort means you also have a lack of persistence to arrive at a level of competence.” Retaining the WorkforceAs an example of how to retain employees, Dillard pointed to the success of Micron’s Employee Resource Groups, as evidenced by the company’s internal data. These groups offer space for Micron’s underrepresented populations to connect with peers from similar backgrounds. Currently, the company has 10 groups, including groups for veterans, women, disabled employees, racial groups, and others. Diversity within leadership was also noted as key for retaining employees. Rodriguez said that when employees see people from similar backgrounds to their own in leadership roles, those employees are more likely to stay with those companies. Leadership training around psychological safety and working cross-culturally was also mentioned, with Dillard highlighting the importance of developing leaders that value inclusion. The cyclical nature of the industry was addressed during the Q A as a reason people may not stay long-term. Part of the solution, Patterson said, is to be transparent about market challenges and the importance of having a few months’ worth of savings. When employees encounter market challenges, they may be forced to switch industries if they don’t have savings to cover them. “There’s a role for us to be playing when it comes to supporting the financial literacy of our employees,” she said. View the full 2024 panel discussion to learn more. Additional ASMC 2024 HiglightsASMC 2024 featured keynotes by thought leaders from IBM, Wolfspeed, and Semiconductor Advisors. ASMC is the leading international technical conference for discussing solutions that improve the collective manufacturing expertise of the semiconductor industry. Solving the challenges presented by semiconductor manufacturing is a combined effort by device makers, equipment and materials suppliers, and academics. ASMC provides a platform for semiconductor professionals to network and learn the latest in the practical application of advanced manufacturing strategies and methodologies. Technical presentations at ASMC highlight industry innovations with specific results and select ASMC manuscripts are published in the ASMC Special Section of IEEE Transactions on Semiconductor Manufacturing.Krish Raghunath is Sr. Specialist for Conferences Committees at SEMI Americas.