semiconductors

Veterans often have essential skills and experiences that make them ideal candidates for careers in the chip industry, but it sometimes can be difficult for them to understand how the skills they developed while in the service translate to those that are sought after in the civilian workforce.

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger design. While the new market segment created excitement and new opportunities, it also was untested and created uncertainty. Many fledgling companies failed. It’s a different story today. Arm, as well as Cadence and Synopsys, are silicon IP suppliers and the segment’s yearly revenue tops $4 billion, a long way from those early garage startup days. ESD Alliance member CAST, a silicon IP provider since 1993, participated in the remarkable growth and impact on the semiconductor industry. Nikos Zervas, CAST’s CEO, and I discuss those early days of the IP business and what’s ahead. Smith: What were the early days of silicon IP like? Zervas: In those early Wild West days of IP, vendors and customers both wanted to benefit from IP, but nothing was standardized, and people just tried things to see if they worked. The perceived barrier to entry was low: hundreds of IP companies sprang up thinking they only needed RTL coding skills and tools, an FPGA to prototype, and a few thousand dollars to invest. IP deliverables, quality standards, and business practices varied from vendor to vendor and over time. Risk was high, and there are many horror stories of re-spins or market failures due to faulty IP cores. Smith: How has the silicon IP market changed from its early days? Zervas: Firms delivering high-quality IP and providing outstanding customer support survived. Others disappeared. Eventually the industry centered around a reasonably common sense of IP requirements and quality and a consistent set of business practices. IP product complexity has driven upwards as SoCs have grown. The largest ASICs used to approach a few million gates; today they’re hundreds of millions, and the granularity of IP has evolved from small functions to pre-integrated subsystems. Early on, a designer doing image processing might license individual functions like a Finite Impulse Response (FIR) filter or a Discrete Cosine Transfer (DCT) block. Today, instead they would license a complete JPEG compression core containing those functions and more, or even a complete black box subsystem streaming processed, stabilized, compressed video over Ethernet. IP selection criteria have also changed. Early IP was handcrafted to eliminate every extra gate, as being a few thousand gates smaller was a killer advantage in the era of 180nm ASIC processes. Today, at 7nm or 5nm process, tens of thousands gate differences are just noise, and it’s usually the reliability, functionality, and performance of an IP core that matter most. Smith: When did the silicon IP market start to take off? What was the driving force? Zervas: By the early to mid 2000s, uncertainty about what IP was and how best to use it – and the early wave of less-than-great providers – were being replaced by increasing acceptance and emerging best practices. The introduction of smartphones, the wild growth of Internet of Things applications, growing automotive system sophistication, and other advances fueled the explosion of the IP market in the late 2000s. In fact, according to the ESD Alliance Electronic Design Market Data Report, revenue from IP licensing today has surpassed the license revenue from front-end EDA tools. This would have been unimaginable in the late 1990s. Smith: How has silicon IP changed chip design? Zervas: Designers today must develop massive, complex systems with an even tighter time to market. Only the higher level of design abstraction and the distributed expertise that silicon IP provides make this possible. But IP also increases the challenge of differentiation: With the same IP available to everyone, how do you design a product that stands out in its market? The answer to differentiation today lies mainly in clever SoC architecture. Delivering better features with superior performance, lower power consumption, or other winning characteristics now depends not so much on perfecting each separate IP block but rather from selecting the best IP for the system’s requirements, integrating those IP cores for clean communication and efficient resource sharing, and other smart system-level decisions. It’s similar to modern building design: Every firm has access to the same materials and tools – concrete, glass, etc. – but only a few produce exceptional buildings. Smith: It seems that are several different business models for IP licensing, such as up-front license fees, subscriptions, royalties, or a combination of these. Do you think the IP market will gradually align around one basic model, or will it continue as is with a variety? Zervas: Different models serve different needs. For example, commodity IP like a SPI interface can’t demand royalties, but unique, leading-edge IP – like a 112Gbps SERDES – still can. I believe the market will continue with different business models, though the number of different models may shrink and their terms begin to align. About Nikos Zervas Dr. Nikos Zervas is the chief executive officer of CAST, Inc. He co-founded image and video compression IP developer Alma Technologies in 2001, and led the bootstrapped firm as chairman and CEO for nine years before joining CAST. He was a founding member of the Hellenic Semiconductor Industry Association and served on its board for several years with responsibility for strategic planning. He is a senior IEEE member and member of the Technical Chambers of Greece, had contributed to the GSIA's IP Working Group, and has published multiple technical papers on data compression design and related topics. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

China’s semiconductor sector has exploded to become one of the largest in the world and match the region’s prominence as the biggest consumer of chips. From 2015 to 2020 alone, revenue of China’s integrated circuit (IC) industry expanded at a rapid clip of 20% CAGR (RMB) to $128 billion.

Demand for hi-tech manufactured goods is at an all-time high and is expected to grow significantly in our new digital age, COVID-19 economy. This is especially true for semiconductor chips. Chip manufacturers have been working to meet this demand by building new factories and by optimizing processes and equipment in existing fabs. While there is much media coverage about new factories planned by leading-edge chipmakers and government investments in the semiconductor sector, greenfield fabs entail significant capital expenditures and are sometimes fraught with complex political concerns. As a result, they can take several years to complete and reach their planned production capacity. Instead, the semiconductor industry needs to optimize existing factories in order to increase productivity and yield and meet growing demand by implementing smart manufacturing solutions. Smart manufacturing solutions will inherently reduce costs with more efficient and automated processes, and those savings can be reinvested for the next wave of solutions. Chip Industry on the Bleeding Edge Semiconductor manufacturers have always been focused on bleeding-edge technology to outflank strong competition and build the best products – faster and cheaper. Today, pioneering organizations are using data to optimize manufacturing processes and equipment, a practice known as Smart Manufacturing. While there are many definitions of Smart Manufacturing, the essence is maximizing the utility of big data generated in these factories by leveraging three pillars: Sensing, Connecting, and Predicting. It is not just the digitization in manufacturing, but it is also about turning the data into actions that generate value – an effort the SEMI Smart Manufacturing Committee is driving based on the three pillars. Optimizing return on investment is the ultimate goal. SEMI Smart Manufacturing Initiative activity is based on three pillars that support the goal of increasing ROI. Making the Right Decision, Faster Smart manufacturing practices enable organizations to make the right decisions and take action faster based on insights generated from real-time and historical data. This requires data management technologies and applications that can process, analyze, and act on information instantly. It has become ever more difficult to process and discern the relevant data or signal from the vast volume of data, perform analytics or develop new ML or AI analytic tools, and then make the critical decisions to solve problems as close to real-time as possible. Who’s Responsible – IT or OT? In the past IT (Information Technology) and OT (Operations Technology) were separate entities within organizations, with IT focused on storing large amounts of data for enterprise systems and OT concentrated on using data to perform specific functions. Smart Manufacturing often demands combining IT and OT, difficult in rigid organizations that operate the two organizations independently and lack the infrastructure to implement comprehensive solutions. Success requires executive leadership sponsorship, motivated technical personnel and, most importantly, a clear deliverable on the value in implementing Smart Manufacturing. Many organizations have introduced top-level leadership positions such as a Chief Information Officer or Chief Data and Analytics Officer to address this convergence and many of these leaders are embracing Smart Manufacturing practices. The SEMI Smart Manufacturing community includes many of these leaders and therefore has highlighted the importance in the return on investment for Smart Manufacturing solutions. Read more about IT and OT convergence and note that Smart Manufacturing is synonymous with Industry 4.0. The SEMI Smart Manufacturing Initiative covers the entire supply chain. Get Smart in Smart Manufacturing While new technologies and applications are being created to deal with mountains of data, it is the underlying methodologies and practices that are key to a successful Smart Manufacturing deployment. SEMI, the trade association representing the electronics manufacturing and design supply chain, is in a perfect position to evangelize Smart Manufacturing experiences and best practices for the entire manufacturing community. The more than 30 member companies participating in the SEMI Smart Manufacturing Initiative bring more than 500 years of collective experience and knowledge to the topic. Many segments of the supply chain participate in the SEMI Smart Manufacturing Initiative including packaging, assembly, SMT and PCB assembly, test, software, data management, sensor and material suppliers. Learn How to Manufacture Smarter SEMI SMART Manufacturing is hosting two great conferences in the coming months – the Global Smart Manufacturing Conference (GSMC) and the SEMICON West Smart Manufacturing Pavilion. As a leader of the organizing committee and chair for the SEMICON West Smart Manufacturing Pavilion, I encourage people who want to learn how to implement Smart Manufacturing or expand their knowledge of Smart Manufacturing to attend these events. The GSMC will feature keynotes highlighting the value of Smart Manufacturing, offer tutorials on the three pillars, and introduce several case studies for each of the pillars. Thirty-two organizations – ranging from global cloud providers, semiconductor factory operators, leading equipment vendors and software application solution companies – will present. See the full agenda here. The SEMICON West Smart Manufacturing Pavilion will compliment GSMC by showcasing a number of use cases that highlight the value of Smart Manufacturing. Panel discussions will deep dive into the challenges of implementing these best practices and the direction smart manufacturing is taking in the coming years. Our goal for these events is for you to take this knowledge back to your companies, implement and improve on the detailed solutions highlighted at the conferences, and return next year to share your success stories with the community. See you soon, in person or virtually! About the Author Bill Pierson is VP of Semiconductors and Manufacturing at KX, leading the growth of streaming data analytics in this vertical. Bill is also a chair for the SEMICON West Smart Manufacturing Conference and an active team member of the SEMI Americas Chapter. He has extensive experience in the semiconductor industry including previous experiences at Samsung, ASML and KLA. Bill specializes in applications, analytics, and control. He lives in Austin, Texas, and when not at work can be found on the rock-climbing cliffs or at his son’s soccer matches.

Areas packed with dense foliage. Mile-deep mines and tunnels. Urban canyons. Indoor environments. Global Positioning System (GPS) technology has long been a boon to location tracking of aerial, terrestrial and aquatic vehicles — as well as to people in motion — but in many cases it can’t function with a high degree of reliability, either because the GPS signal is somehow obstructed, or worse, is jammed or spoofed. Delivering higher precision and higher reliability in GPS-denied environments — as well as immunity to jamming and spoofing — positioning, navigation and timing (PNT) represents the next evolutionary step in location positioning and tracking. With PNT so critical to a range of defense, commercial and industrial applications — and with sensors the building blocks of PNT solutions —the MEMS Sensors Industry Group, a SEMI Technology Community, is ensuring that our members play a transformative role in PNT innovations. We’ve secured $14.9 million in research dollars for PNT R D over the past 18 months, marking Phase I of a project funded through a public-private consortium with the U.S. Army Research Laboratory (ARL). With the typical funding structured as a 50/50 cost share with the industry participant, the research dollars go farther, and the level of commitment that each recipient makes is more pronounced. As we look ahead to Phase II of the MSIG PNT R D project, the details of which we’ll announce later this year, we’d like to reflect on the companies and research labs that won bids through a competitive process supported by the SEMI-MSIG PNT Technical Advisory Council and the SEMI-MSIG PNT Governing Council. Winners submitted proposals that both met our criteria for advancing PNT technologies relative to mobility, size and weight, and that laid a path toward greater cost efficiency and lower product price. “PNT doesn’t displace GPS,” said Tim Brosnihan, executive director of SEMI-MSIG. “Rather, getting the two technologies to work together improves position and tracking. While current PNT solutions use inertial measurement units, or IMUs, to effectively maintain positioning accuracy in the absence of a GPS signal, it’s also true that accumulated bias and noise-related errors in the IMUs make positional determination unreliable. Like most great pairings, GPS and PNT can work together. We can use IMUs when GPS is unavailable, and when GPS returns, it can be used to reset the IMU errors. So when the GPS signal is lost again, the IMU can maintain navigation and location. “We’re focusing this PNT project on technologies that will allow accurate positional determination in the absence of a reliable GPS signal for prolonged periods,” added Brosnihan. Here are snapshots of the 10 companies and research institutions that won awards for their PNT-focused developments. Analog Devices is developing an optimal size, weight, power, and cost (SWaP-C) solution for applications requiring high-accuracy navigation and uncompromised reliability. The company’s mode-matched navigation-grade gyroscope with system ID leverages an innovative sensor and its associated process design, a robust high-volume manufacturing flow, and system-control algorithms to achieve very high-performance (0.01 degree/hour bias instability and 0.005 degree/√hr angle random walk). Carnegie Mellon University (CMU) is developing a CMOS MEMS high-stability accelerometer through machine learning (ML). If embedded in footwear, these ML-optimized accelerometers could be used in personal navigation. If embedded in a golf ball, baseball or hockey puck, the accelerometer could extract the trajectory of the object in motion by measuring its shock (force). The CMU device validates state-of-the-art performance of the university’s high-dynamic-range accelerometer systems-on-chip. It also validates and tests ML models by measuring the accelerometer and auxiliary sensor output over long time periods (e.g., 1 hour, 10 hours, days) to collect independent long-duration time-series data. By modeling drift from environmental influences — along with possible overall system changes from extreme events, such as high-temperature excursions and shock — designers can dramatically reduce navigation errors to support more accurate navigation over longer time periods. GE Research is developing a novel MEMS gyrocompass that will enable high-end north-finding systems, traditionally unaffordable for automotive and consumer applications. The device will be available in mass-market applications such as robotics and autonomous vehicle navigation in GPS-denied environments. The MEMS gyrocompass enables a 10x reduction in SWAP-C with high accuracy. An additional benefit of this work is that GE will offer a foundry service process development kit (PDK) for its Polaris MEMS process, speeding the development and manufacture of MEMS devices in an advanced processing facility. Georgia Institute of Technology is developing high-aspect-ratio monocrystalline silicon carbide-on-Insulator (SiCOI) MEMS devices that will reduce navigation angle errors, potentially making widescale pedestrian navigation available in mass-market applications such as smartwatches and smartphones. The platform for ultra-high-performance bulk acoustic wave (BAW) gyroscopes and timing resonators will feature material properties that allow a much better structural symmetry and a higher-resonant quality factor (Q) than silicon MEMS (Si MEMS). Honeywell is working to enhance the navigation accuracy of commercial and military vehicles in GPS-denied environments through an innovation that dramatically improves the performance of a MEMS IMU by both refining candidate ML algorithms, including recurrent neural networks (RNNs), and by combining deep neural network (DNN)-based calibration and sensor fusion algorithms. PARC is developing a new materials platform for photonic integrated circuits (PIC). Aluminum gallium nitride (AlGaN), an ultra-wide bandgap semiconductor, is epitaxially grown to produce single-crystal layers for fabrication of optical components, such as waveguides and micro-ring resonators for optical signal processing. The project includes design and fabrication of specialized laser diodes at wavelengths needed to probe qubits based on atomic ions (e.g., strontium and ytterbium). The new platform offers several benefits: low optical loss from the ultraviolet (UV) to infrared spectral bands excellent non-linear optical properties for efficient frequency-generation processes (e.g., optical frequency combs); and enabling technology to realize compact, field-deployable quantum systems for PNT applications, such as ultra-fast distance measurements, microcombs for optical atomic clocks, photonic radar, optical coherence tomography, and coherent communications — all applications that benefit from the lower cost and small chip size of these integrated photonic circuits By expanding its proprietary EpiSeal encapsulation process to include new materials and topologies, SiTime is developing low-impedance and low-noise MEMS resonators with an ultra-stable wafer-level package. Because these novel MEMS resonators are highly reliable and very compact — while using less power and providing lower RF noise — they’re ideal for 5G RF timing applications, IoT devices, and smart vehicles. Teledyne Scientific Imaging (CSAC project) is conducting a study to identify paths to reduce the cost of battery-operated chip scale atomic clocks (CSAC) that provide affordable precision timing for denied environments. The project goal is to identify viable paths of reducing cost by an order of magnitude, without sacrificing performance. In addition to exploring design and manufacturability solutions, project researchers are performing short loop experiments as proof-of-concept validation. Through a second award, Teledyne Scientific (IMU project) is advancing packaging and integration for compact, navigation-grade six degrees of freedom (DOF) MEMS IMUs. Featuring reduced bias instabilities associated with packaging stresses and ambient temperature influences, the Teledyne Scientific IMUs promote environmentally robust low-stress packaging of wafer-level vacuum packaged (WLVP) MEMS gyro resonators, facilitating a lower-cost, smaller and more accurate IMU for performance-driven PNT applications. Twinleaf is developing a new light source module ideally suited for integration directly into quantum sensors. This project integrates a bright, tunable distributed Bragg reflector (DBR) near infrared (IR) 795nm wavelength laser made by the project’s subcontractor (Photodigm) into a package that locks the laser to an atomic reference line in a microfabricated vapor cell. The laser module’s high-output intensity and low magnetic signature will enable breakthrough performance levels for Twinleaf’s magnetometer and other quantum sensors requiring the light source integrated into the sensor module. Request for Proposal for Phase II of SEMI-MSIG PNT Program Opens Q4 2021 SEMI-MSIG will accept request for proposal (RFP) submissions for Phase II of its PNT program starting in Q4 2021. This year, in addition to funding IMU and timing device projects, MSIG will also consider proposals on imaging-based navigation solutions. If you’d like to submit for Phase II, sign up to receive more information on the RFP by visiting SEMI’s R D Programs page. You can also connect with Paul Carey by email, [email protected] or LinkedIn. Paul Carey, Ph.D., is the director of the MEMS Sensors Industry Group. With deep domain expertise in X-ray imaging backplane platforms — and their supply-chain technologies such as flexible substrates, laser annealing for semiconductors and silicides, thin film transistors (TFT) for flexible OLED displays, and polysilicon-on-plastic TFT technology — Carey has held technical leadership positions at dpiX, Applied Materials, and Lawrence Livermore National Laboratory. He received a double-major B.S. from UC Berkeley in Electronical Engineering and Computer Science (EECS), and Materials Science and Engineering (MSE). Carey holds an M.S. in EECS from UC Berkeley and a Ph.D. in MSE from Stanford University.

In response to the PFAS Low Volume Exemption (LVE) Stewardship Program recently established by the U.S. Environmental Protection Agency (USEPA), the SEMI PFAS Working Group (WG) is focused on identifying strategies that minimize supply chain risks and impacts to downstream users.

Terry Tsao, Global Chief Marketing Officer at SEMI and President of SEMI Taiwan, recently discussed technology trends with Young Liu, Chairman of Hon Hai Technology Group (Foxconn), as a prelude to SEMICON Taiwan’s five online forums.

Today, AI algorithms are primarily run at large data centers-- in the cloud. For this intelligence to be used at the edge, data must be transmitted to the cloud, analyzed there, and the results transmitted back to the field of operation, such as a mobile phone, medical implant or autonomous vehicle.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.