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Taking aim at advancing smart medtech innovation, the SEMI Nano-Bio Materials Consortium (NBMC), in collaboration with the U.S. Air Force Research Laboratory (AFRL), in March 2020 identified 12 organizations from industry and academia as recipients of $20.4 million in funding, leveraging $10.7 million of cost-share from award recipients. Unique to this round – the sixth in NBMC’s eight years – is a pilot program for NBMC and AFRL to collaborate more closely and share more resources. As part of that effort, AFRL is contributing additional funding to seven of the 12 projects to enable its researchers to work alongside industry on the projects in the new AFRL-Industry Co-Development Program. After being matched to a project during pre-RFP discussions – also known as the White Paper Stage – AFRL researchers were designated as NBMC Consortium Project Investigators before collaborating with industry on the second stage of proposal development. Once contract negotiations between NBMC and the proposing entity wrap up, the AFRL investigators will participate in the development of smart medtech innovations. “This is a new way for AFRL researchers to participate as project performers responsible for contributing to project milestones and deliverables, in addition to providing program management oversight that AFRL has employed for past NBMC projects,” said Dr. Jeremy Ward, past NBMC government lead and current participant in the AFRL Entrepreneurial Opportunity Program. “This program should enable technical risk-reduction for industry by leveraging AFRL competencies and U.S. Air Force aeromedical and airmen performance mission connectedness and ultimately help speed the development of dual-use smart medtech,” added Matt Dalton, AFRL Materials and Manufacturing Directorate program manager and NBMC Governing Council member. “We need efficient mechanisms to leverage research being done outside of AFRL,” said Sharma, who is also senior technical lead for Cognitive Neuroscience at AFRL's 711th Human Performance Wing. “If someone is developing a groundbreaking technology that can be helpful for our airmen, then let’s work with them so that we have an opportunity at an early stage to actively shape that research for Air Force-relevant use cases. Similarly, with this co-development initiative, external researchers will also get an opportunity to work alongside world-class researchers at AFRL and, through those interactions, get insights into the needs of the operational community.” “The AFRL-Industry Co-Development Program strengthens the work between AFRL and industry to better target the strategic needs of the Air Force for dual-use technologies while more closely aligning with commercial market requirements,” said Dr. Melissa Grupen-Shemansky, SEMI CTO and Executive Director of NBMC. “This new collaboration will enable the growth of the ecosystem critical to bringing the latest smart medtech innovations to market while making the technology’s supply chain more sustainable and resilient.” SEMI NBMC connects military, industry and academia for research and development into the practical use of nano-biomaterials. The 2020 RFP targeted nano-bio materials for wearables, flexible and alternative power sources for wearables, and open concepts for wearables for diagnostics and ambulatory monitoring. These technologies address the critical need to monitor, evaluate and mitigate stress experienced by workers in high-pressure occupations – such as aviation, emergency, critical care and aeromedical evacuation – to enhance their warfighter performance and help ensure their well-being. For more information on SEMI NBMC, our R D funding projects, and how you can help shape the direction of our funding programs, visit our website or contact me at [email protected]. Learn more about our projects at the 2021 Global Smart MedTech Symposium July 28-29 and August 4-5, 2021. For more information about the NBMC-AFRL collaboration, see the 2020 Smart MedTech Virtual Workshop agenda. This article borrows from a U.S. Air Force press release on May 27, 2021. Rene Krantz is program manager for SEMI NBMC Smart MedTech.
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When COVID-19 hit the semiconductor industry, SEMI members were confronted with new hurdles to keeping their employees safe and their operations running uninterrupted. We quickly assisted our global membership around the globe by providing a forum for collecting member insights on best practices for operating and safety procedures, supply chain issues and sentiments on business impact and recovery. That forum took the form of surveys we launched in March 2020. We shared the results with the larger SEMI member community to help them cope with the evolving impacts of the pandemic on their businesses. Following is a summary of our 4th survey, issued last month. Regional and Sector Representation Nearly 40% of our respondents represented companies headquartered in North America. Of the respondents, 10% each were from companies headquartered in Taiwan and China; 5% from Korea, 13% from Japan and 20% from European and Middle Eastern members. The largest share of respondents – 40% – develop equipment for semiconductor fabrication, assembly, and test; 21% supply materials to the microelectronics industry; 14% are device makers; 6% supply software and design services; and 3% are OSATs, EMS suppliers or ODMs. Measures Member Are Taking to Continue Operations The May survey found that almost no companies ceased production for any significant length of time. In order to continue operations, companies instituted social distancing and masking requirements, temperature checks, schedule changes, and some contact tracing, all to varying degrees, as shown in Figure 1. In addition, several companies implemented some combination of mandatory testing, bump sensors, air purification and site capacity limits and sequestered foreign workers in separate housing for required quarantines after travelling. Figure 1 All of these measures are routinely discussed during the regular SEMI EHSS COVID-19 Working Group calls. That group consists of facilities, HR managers and others tasked with ensuring safety monitoring and compliance at member companies. Company Vaccination Policies With the pace of vaccine rollouts varying widely around the world, only 5% of respondents are requiring all workers to be vaccinated before returning to the office, and 12% have not yet considered a vaccine policy. The majority of companies are encouraging but not requiring employee vaccinations, and 26% leave the decision to the individual employees. Figure 2 North American companies constituted the majority of the required and encouraged vaccination categories. In Europe, companies fall into the employee decision or encouraged categories but none require vaccinations. Japanese companies primarily leave the vaccination decision to employees, while Chinese companies are split among the required, encouraged and employee decision categories. Clearly, these guidelines are not required by law in each region, but instead fall to employers and local policymakers. Member Readiness for Digital Transformation A solid majority of members reported they have invested in the adoption of digital transformation technologies and practices, though only about 14% expect to continue their digital investments in the coming year. Many respondents have deployed virtual meeting software and have implemented or plan to put in place virtual reality tools for remote diagnostics and predictive modeling for semiconductor manufacturing. Figure 3 Location by Functional Group in Returning Employees to Sites Not surprisingly, manufacturing and distribution staff that could work from home during the pandemic are back on site, and respondents signaled that R D and engineering groups will soon end their remote work, following by finance and procurement. Sales and marketing show the highest percentage of staff working remotely, with sales having the highest number remaining remote for some time to come. Figure 4 Resilience to Further Economic Uncertainty Of the 274 companies responding, 229, or 84%, feel more resilient in the face of further economic uncertainty after their response to COVID-19, though continuing supply chain issues and raw materials shortages ranked among their top concerns, as did rising customer demands, their ability to increase capacity utilization rates, and the increasing demands on employees and facilities overall. Figure 5 Many thanks to all survey respondents over the past year! We’ll keep you up to date on results of future surveys. For more details on the SEMI EHSS COVID-19 Working Group calls, visit the SEMI COVID Response Site. To watch the recording of our most recent CEO Webinar – Surging Chip Demand, Digital Transformation, and the Pandemic – What’s Next? – click here. More than 750 people attended the June 2nd webinar sponsored by SEMI members Brooks Automation, Hitachi, JCET, KLA and TEL. Heidi Hoffman is senior director of Technology Communities marketing at SEMI.
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For the second straight year, SEMICON China, among the world’s largest and most influential semiconductor industry events, was the first local tradeshow of its scale held in-person, reflecting China’s rising prominence in the semiconductor industry. After securing approval from the Chinese government to hold large events, SEMI staged SEMICON China 2020 and 2021 with advanced protections against COVID-19 in place. There were no reported infections at either event. Highlights from SEMICON China 2021: Large Scale: Attendance of over 92,000, including more than 66,000 visitors and 25,000 exhibitors. Expo hall totaled 84,500 square meters with about 1,100 exhibiting companies and over 4,000 booths. World-Class Thought Leaders: Strong industry support from key foundries, OSATs, equipment and materials suppliers. Keynote speeches featured world-class industry leaders and head of China’s IC industry fund and global investment consulting agency, who explored the latest global business, technology and market trends and hot domestic investment topics. Concurrent Forums: Forums included SIIP China: SEMI Innovation Investment; Smart Manufacturing; Advanced Manufacturing; Advanced Packaging; Memory; Power Compound Semiconductor; China Display Conference; the all-new Advanced Materials Forum; and China Semiconductor Technology International Conference (CSTIC). Rich Digital Content: SEMICON China’s digital platform provided a rich array of content to attendees around the world including the Grand Opening Keynote and CSTIC, which were broadcast live online. Workforce Development: SEMI China worked closely with industry and government partners to promote SEMI Workforce Development programs to help attract and retain talent for China’s semiconductor industry. SEMICON China again featured the SEMI Workforce Pavilion and SEMI Workforce CXO Talent Forum. Outstanding COVID-19 Protective Measures: SEMICON China deployed advanced testing and monitoring equipment and implemented strict COVID-19 preventative measures to ensure a safe environment for all attendees to network and conduct business. Looking Ahead With the resounding success of SEMICON China 2021, optimism is growing that more physical events will be held with travel restrictions set to ease later this year. The more than 2,500 SEMI members around the world are eager to again network and collaborate face-to-face with customers, suppliers and partners to solve challenges in the microelectronics industry and drive semiconductor innovation that continues to transform how we work and live. That very innovation made many businesses more resilient as the virus spread and enabled people worldwide to work, learn, and shop from home. As SEMI starts to stage other events in-person, we will put in place advanced protective measures against COVID-19 to ensure the safety and well-being of all attendees. As the vaccination roll-out continues worldwide and new COVID-19 strains emerge, SEMI’s flagship SEMICON events are evolving in several ways, most notably with a larger digital presence. In this new era, we offer an international platform for SEMI members and partners across the microelectronics supply chain to collaborate, discuss industry trends, solve common challenges, network, and accelerate business growth through physical, virtual, and hybrid formats. Hybrid events – on-site exhibitions and conferences featuring a digital presence – allow the face-to-face connections so important to the semiconductor industry but also improve the attendee experience by offering an online option with the following benefits: More international accessibility to content live or on-demand Robust interactivity with live-streamed events, allowing more people to participate Greater cost effectiveness to enable companies and people under tight budgets to take advantage of world-class content, including keynote presentations, panel discussions, and technical sessions. In a recent survey of advanced manufacturing businesses, Informa Markets, a multinational publishing, business intelligence, and exhibitions group, found that 93% of respondents are likely to return to in-person events between August and December 2021, signaling a widespread eagerness for the return of live events and face-to-face connections. SEMICONs Scheduled for 2021 In a normal year, each of the seven regions where SEMI operates stages a SEMICON, with the exhibitions spread throughout the year. With the world continuing to combat COVID-19, more SEMICONs have been moved to the second half of 2021 – most of them with a hybrid format so exhibitors and attendees can take advantage of the increasing popularity of online events. After last year’s disruptions to the SEMICON schedule – and with more experience in the new normal – SEMI is excited to welcome the businesses and peers who couldn’t attend the 2020 events back to the in-person and hybrid shows. Innovation never sleeps. And SEMI will continue to evolve its events to help you form the partnerships and make the connections vital to the growth of your company and the industry. For more information about regional SEMICONs, please visit the SEMI events page. About the Author David Ghodsizadeh is the Director of Global Product Marketing at SEMI, where he develops customer-centric strategies to market SEMI Membership, Market Data, Expositions, Smart Initiatives, and Technology Communities to members, partners, and industry peers. Connect with David on LinkedIn.
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Traditionally, defect classification is done manually by operators or using Automated Optical Inspection (AOI) machines, often leading to classification inconsistencies. Also, rules-based AOIs may at times be unable to fully satisfy project requirements due to the rigidity of inspection recipes. SixSense – Breaking the Status Quo with Artificial Intelligence Enter SixSense, an AI-powered defect classification software platform that has been making breakthroughs in defect detection and classification for semiconductors to make manufacturing smarter and more efficient. Founded in 2018, SixSense has already amassed a wealth of experience and chalked up a number of successes such as automating the manual image classification process, reducing manufacturing false rejects, and capturing escapees. Infineon Technologies and GlobalFoundries were amongst the early adopters of SixSense’s platform: classifAI. With Infineon, classifAI has allowed over-rejection rates to be precisely quantified. classifAI – Simple UI, Easy Usage, Powerful Models As a UI-based assistive software platform, classifAI, SixSense’s automated defect classification platform is built with the defect and yield engineer in mind. SixSense takes care of all the back-end complexities – such as coding, algorithm modelling and deployment – to enable end users to get started and use the platform with a simple GUI. The simplified end-to-end AI pipeline offered on the platform includes data labelling to make data AI-ready, model training, and model testing. Ultimately, models are deployed on the production floor for 24/7 inferencing of hundreds of millions of images every year, at scale, across processes, tools and sites. Machine learning models built by the SixSense team have seen strong results, with model accuracy of up to 98% in certain use cases. Track Record of delighting IDMs, Foundries and OSAT Customers SixSense has consistently solved visual inspection problems and enabled the success of IDMs, foundries and OSATs since its inception. The AI technology has helped a range of customers across 100mm-300mm wafer standards, both pure silicon and compound wafers, and caters to specific end-use market requirements such as RF and automotive. Partnerships between startups and established manufacturers are key to actualizing the value of AI in manufacturing. “Our collaboration with AI startup SixSense has enabled us to explore opportunities in yield gain, improving cycle time, and real-time monitoring of process shifts,” said Dato’ Tan Soo Hee, Executive Vice President, Global Backend Operations at Infineon Technologies Asia Pacific. “SixSense has been very attentive to the needs of our engineering team, addressing project requirements using a customer-first approach evident in the design of the intuitive software platform,” said Melvyn Peh, Principal Engineer, Automation-Scan-Pack, Infineon Technologies Asia Pacific. The intelligent annotation module is one of many offered by SixSense, which uses AI to train AI and accelerate the data annotation process by focusing on the semiconductor-specific requirements. Another valuable module in classifAI is advanced analytics that capture the heatmap for defect distribution on the images. Images are stacked on top of each other, with the location of defects aggregated to provide the defect heatmap. Through this, systematic failure patterns were identified that allowed defect engineers to zero in on key sources of failure and assist in root-cause analysis. Infrastructure – Scale Fast, Adapt Quickly, Accelerate Value Creation In the dynamic world of technology, machine learning and AI projects must meet changing infrastructure demands. A cloud-first approach is often favored for the plethora of benefits it offers. “We’re looking forward to a great partnership with SixSense, treading together hand in hand exploring fresh ideas and possibilities,” said Manju Jalali, Vice President of digital manufacturing at GlobalFoundries, who oversees the company-wide roll out of classifAI. For use cases where on-premise deployments are preferred, SixSense offers such options for infrastructure integration, satisfying all possible infrastructure requirements in the market. Contributing to a vibrant innovation ecosystem SixSense was mentioned by Singapore’s Deputy Prime Minister Heng Swee Keat during an event that marked Infineon’s 50th anniversary in Singapore: “I am heartened that Infineon will be investing more than $27 million over three years on an AI initiative in Singapore. Under this initiative, Infineon Singapore will be partnering academia, industry, and local startup SixSense AI to develop new AI solutions and courses.” Explosive Growth of AI in Chip Manufacturing According to a McKinsey Company report, AI contribution to semiconductor company earnings is projected to rise to between $85 billion and $95 billion per year in the coming years. SixSense has been taking great strides in creating value for their semiconductor customers. “SixSense offers tremendous value in a high-growth vertical in the semiconductor industry, marrying the latest deep learning algorithm with the compute power of the cloud,” said Rajan Rajgopal, CEO of DenseLight Semiconductor. “This leads to faster root-cause analysis that helps reduce the cost of non-conformance and improve quality.” Dominic Teo is Enterprise Business Development Representative at SixSense. He can be reached at [email protected].
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What does it mean to identify as LGBTQIA+ in the semiconductor industry? It’s an interesting question to ask, but a difficult one to answer. Because we live in a world in which cisgender heteronormity is assumed, it’s possible to self-identify as LGBTQIA+ without sharing that information publicly. Coworkers and managers might not even realize that their colleague or employee is gay, lesbian, transgender, non-binary or other. Unlike other minorities, notably people of color, LGBTQIA+ people may choose to keep their identities invisible.As I began outreach for this article, I recognized that some people might not want to expose a potential vulnerability to both their co-workers and a broader global audience of SEMI members, so I tried to make them feel more comfortable. I told them I’m a lesbian. I said that I’d send content for their review before publishing. But I quickly discovered that wasn’t enough, despite sweeping cultural and legal advances around LGBTQIA+ attitudes and identity. According to a 2020 Gallup Poll, 5.6% of U.S. adults now identify as LGBTQIA+, up from 4.5% just three years ago. In 2004, Massachusetts became the first U.S. state to legalize same-sex marriage, and in 2015, the U.S. Supreme Court made same-sex marriage legal in all 50 states. The semiconductor industry has been historically conservative. The times, however, are changing. Large chip companies such as AMD, Intel and Lam Research actively support diversity and inclusion efforts across minority groups, including LGBTQIA+, and that’s a good thing, but is it enough? And if not, what actions can SEMI members take to help LGBTQIA+ people in semiconductors feel safe enough to choose visibility?According to Antoinette Hamilton, global head of Inclusion and Diversity at Lam Research, more than 46% of LGBTQIA+ employees in the industry aren’t out in the workplace. That tells us there’s still work to be done, a challenge that Lam is embracing. With its Pride employee resource group (ERG) leading the way, partnerships with organizations such as PFLAG and Out Equal, and recruitment efforts made through organizations such as Out in Science, Technology, Engineering, and Mathematics (oSTEM), Lam has earned a score of 100 on the Human Rights Campaign Foundation’s Corporate Equality Index and was named one of the Best Places to Work for LGBTQ Equality.“At Lam, we understand the importance of empowering employees to bring their authentic self to work,” says Hamilton. “We believe when employees feel valued and included, each person can reach their full potential.”Back in 1992 when Intel paid to relocate Judi Goldstein, her partner and their son from New Jersey to Oregon, mainstream cultural attitudes toward gays and lesbians were very different. According to a June 1992 Gallup poll, only 48% of Americans thought that “gay or lesbian relations between consenting adults should be legal,” with 44% saying they should be illegal. A May 2020 Gallup poll recorded a dramatic shift in attitudes, with 72% affirming the legality of same-sex relations and only 24% opposed.By the late 1990s, Intel had extended domestic partner benefits to same-sex couples. “I registered my partner – now my wife – and our son, and realized that from then on, my whole family would have health insurance through Intel,” says Goldstein, who identifies as a gay woman and uses she/her pronouns. “Both relocating my family and providing family health coverage solidified my attachment to Intel, which was way ahead of other companies at the time.”By 1995, Goldstein became one of the first members of IGLOBE, Intel’s ERG for LGBTQ+ employees. Since that time, she’s observed further progress at Intel, first with the addition of gender identity and expression to Intel’s anti-harassment policy, and later with the inclusion of gender-neutral bathrooms at all major US sites. And advancement didn’t stop there.“We now have international IGLOBE chapters, a celebration of Pride Month in June, company support for the Equality Act and other legislation, a provision for transgender health benefits, and the launch of Self-ID efforts in 2017,” she says.From her start as software engineer more than 32 years ago to her current positions as director of the Open Source Audio and Security Engineering teams, Goldstein has played an instrumental role pioneering new technologies and mentoring other engineers at Intel – in addition to serving as a role model for LGBTQIA+ employees coming through the ranks. Now a grandmother with a five-year-old granddaughter, Goldstein lives in Oregon with her wife of more than 30 and two dogs. Location, Location, LocationAs social animals, we tend to value safe and welcoming places to live. When you’re LGBTQIA+, this may mean moving to an urban area that is more likely to embrace diverse orientations and cultures.After getting his master’s in astrophysics, Chuck Chung had a decision to make. Remain in the same field, which would limit his options on where to live, or get a doctorate in engineering, which would expand them.“In the ‘90s when I was making this choice, things were very different, and I knew that where I worked and lived would have a huge impact on how open I could be,” said Chung. “While I would have loved a career in astrophysics, I realized that engineering would be a more practical choice because I was more likely to find work in a city.”Both personally and professionally, engineering has proved a good choice for Chung. He’s lived in San Francisco and Silicon Valley for the past 18 years, where being out in the workplace is rarely an issue. “I compartmentalize my personal and professional lives when necessary, such as when business colleagues who are overseas talk about their families in casual conversation. Most of the time, though, my identity as a gay man is a non-issue, and I work for a company that really cares.”From his pioneering work in MEMS and genetic sequencing to his current focus on the next generation of microarchitectures at IBM, Chung has long thrived. Now, with a new book on MEMS Product Development – co-authored with two other Ph.D.’s, Alissa Fitzgerald and Carolyn White of A.M. Fitzgerald Associates – the best days of Chung’s career may still be ahead of him. He lives in the Bay area with his husband and their two children.Kunal Garg’s identity didn’t influence his career choices because when he started in semiconductors, he wasn’t out to himself or others. A few years into his engineering career at his former company, Garg realized his identity as a gay man at a time when the national discussion about same-sex marriage was at its apex – leading to some uncomfortable situations at work. “As some of my colleagues and managers openly debated same-sex marriage, they seemed oblivious to the fact that there were LGBTQIA+ people at work,” says Garg. “I knew then that I wanted to steer such conversations in a way that would feel safe and inviting for people like me, who work in this industry while being true to their identities.”Once he’d come out to his family and friends, particularly after he married his husband, Garg wasn’t willing to stay silent at work. “Although it took courage and internal struggle to come out to colleagues, my identity as a gay man wasn’t something I wanted to hide or deny anymore,” he says. “Some people laughed when I mentioned my ‘husband.’ The idea that their colleague, an engineer, an Indian immigrant, a man, could be gay and married to another guy was so foreign, it was almost laughable. Luckily, this didn’t stop me from being myself at work, and over time, these types of conversations became very rare.”Nonetheless, Garg looked around for ways to be part of the LGBTQIA+ engineering community. When he moved to AMD in Austin, he wanted to start with a clean slate. “When my manager called to invite me to join his team at AMD, I casually brought up the fact that my husband was going to need to start looking for a new job in Austin. And, very casually, he asked me what my husband did for a living, and we went on to discuss how Austin would be a great city for us to live in,” says Garg. “The fact that this was such a normal conversation was a big factor in my decision to join AMD.”Soon after starting as a design engineer at AMD, Garg found that LGBTQIA+ engineering community for which he’d been searching. He joined AMD’s Pride ERG, a group that he now chairs. “Being a part of this ERG has been transformational for me on a personal level and has allowed me to connect with my fellow engineers and people in my industry, beyond our mutual love for science and technology.”Become a change agentWhile some chip companies actively promote inclusion and diversity of LGBTQIA+ employees, others still have a long way to go. SEMI and the SEMI Foundation are uniquely positioned to help advance LGBTQIA+ equity issues in the microelectronics industry. "The SEMI Foundation is committed to promoting Diversity, Equity, and Inclusion (DEI) in our industry for the benefit of our workers and our member companies,” says Shari Liss, executive director of the SEMI Foundation. “We are designing programs for human resources departments, company leaders, and DEI allies to make the case for stronger DEI practices that will attract, retain, and promote LGBTQIA+ individuals and other underrepresented groups in our industry. We will soon publish SEMI's Roadmap to Diversity, Equity, and Inclusion and DEI Toolkit, which will contain tools to help companies strengthen their workplace cultures so everyone – including those that identify as LGBTQIA+ – will feel welcome, and will be able to do their best work."“If we want to truly see the semiconductor industry flourish on a global level, we need to push for equitable treatment of LGBTQIA+ and other minority employees,” says Garg. “SEMI can help by educating industry leaders, especially in countries outside North America and Europe, on how diversity and inclusion through policy are vital to their sustained productivity. These workshops and trainings should be data-driven to encourage companies to hire more LGBTQIA+ employees and to create policies that promote the well-being of all employees.”It’s not just at the company level or the industry association level that matters. Just as individuals are necessary change agents in proliferating greater equity among women and people of color, they’re also needed as allies of LGBTQIA+ people.“Like so many of us, I’d love to wave a magic wand to end discrimination based on gender identity or sexual orientation, but like any cultural shift, most change comes in small steps, not in giant leaps,” said Karen Lightman, executive director, Metro21: Smart Cities Institute – Carnegie Mellon University. “Fortunately, it’s easy to help make those small steps by becoming an ally to LGBTQIA+-identified people. When you see an injustice, don’t stay silent. Use your voice. There’s transformative power in that act alone. As one step, I’ve started using my pronouns when I introduce myself and now include them in my digital signature. It’s an easy way for me to express that I am an ally to LGBTQIA+-identified people.”Help us make the change. Use your voice. Get involved. Encourage your company to advocate for LGBTQIA+ inclusion and diversity.Maria Vetrano, principal of Vetrano Communications, is a PR consultant at SEMI Foundation.
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Adnan Hamid, CEO, founder and visionary of Breker Verification Systems, an ESD Alliance member based in San Jose, Calif., once described his job in chip design verification at AMD as “breaking things.” When it came to naming his startup, Breaker was a natural choice. After some consideration, the “a” was dropped and the company became Breker. Now Hamid is breaking the most complex semiconductor designs and Breker, moving from a startup to a scale-up company, is a noted part of the functional verification space. Smith: Why does verification continue to take the most amount of time in a project cycle? Hamid: The project cycle for semiconductor design has changed. Design abstraction has been raised to a much higher level than the days when developers were connecting logic gates. Today’s developers are typing functions that don’t include lower-level implementation details. Designs incorporate more blocks of reusable IP. Both reduce design time. Meanwhile, designs are getting bigger with more blocks of IP stitched together, all in need of testing. As design complexity grows, the amount of testing and verification increases as a square of design effort. One block requires one functional verification effort. Four blocks of IP mean up to 16 functional interactions require verification. While design is moving up the abstraction level, that’s not the case for verification, where plenty of detail must be reimplemented. Verification has certainly evolved, but engineers still think at the level of independent stimulus, response and coverage, driving the need to allocate so much time for verification. Smith: Are chips targeting artificial intelligence and machine learning applications more difficult to verify? If so, why? Hamid: Yes, absolutely and it’s an interesting challenge, especially given that machine learning is based on massively connected processing element arrays. Attempting to verify the individual processing elements and the critical interconnects is complex. AI device arrays and, interestingly, verification test content operation may both be thought of as a mathematical graph of processing elements and interconnect. Their operation involves walking through the graph form to generate a result. Finding the optimum path through these arrays is key. To understand how these systems may be effectively verified, it is worth investigating planning algorithms. Originally proposed by IBM, these hold the key to this type of verification process. The AI- style algorithm starts backward at the end of the processing element array and tracks down the most optimal and likely paths through it. At Breker, we have used these planning algorithms extensively to drive our graph-based test content synthesis process. Smith: Does system integration require verification? Hamid: Yes, it does. In the past, most functional verification has been performed at the block level. However, with the increase in more specialized SoCs, functionality is spread across multiple blocks, as well as the software running on the processors, driving full system-on-chip (SoC) functional verification. In addition, new requirements such as security and safety must be validated. A system-level infrastructure such as cache coherency and power domain execution has become more complex and these must also be tested. The new frontier in verification is ensuring a fully operational SoC. Of course, given the size of these SoCs, hardware-assisted verification such as emulation is essential, and porting tests from block simulations to SoC emulations has become a requirement. This porting process is problematic and this in turn has driven portable tests, giving rise to the idea behind Accellera’s Portable Stimulus Standard (PSS), of which Breker was a major participant. Indeed, some companies are taking this to the next level by composing their system-level testbench at the same time as they commence SoC architectural design, and then developing the hardware design, software design and test content all in parallel, in the so-called “shift-left” manner. Smith: Is “shift-left” a growing trend that are you seeing in verification? Hamid: Yes. Shift-left is taking hold in hardware and software design, giving way to an increase in early test content composition. Then as individual blocks are finished and connected, their verification is driven from this same test content, saving a significant amount of time and effort. This is a huge verification and test generation change that was inevitable given the increased time-to-market constraints and SoC complexity. Figure 1: Shift-left is ushering in the next generation of SoC verification. Source: Breker Smith: As an entrepreneur, what advice would you give someone founding a startup or thinking about starting one? Hamid: Do not take the attitude “Build it and they will come.” My best advice for an entrepreneur or fledgling entrepreneur is to solve a specific customer problem, however narrow it might seem. Including services as part of a product offering and developing partnerships with other vendors helps with this and turns your company into a solution provider not a product developer. This is essential for getting the right products to market on time and within budget, and then ultimately scaling them across the market. The ESD Alliance and Accellera are hosting a two-part webcast series on the work-from-home experience titled Remote Work, Remote Chip Design: Building Chips During a Pandemic. The first panel, Wednesday, June 9, at 9:00am PDT, will feature a discussion led by Tom Fitzpatrick, strategic verification architect from Siemens EDA verification engineers through their experiences converting their home offices into verification test labs. The second panel in July will explore how executives managed a remote workforce and explain how they plan to bring employees back to physical offices. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.
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A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.
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