semiconductor manufacturing

On Friday, September 19, 2025, the President signed a proclamation requiring a new $100,000 fee for United States H-1B visa applications effective September 21, 2025 seeking to curb what the administration views as significant overuse. A memorandum later issued by the United States Citizenship and Immigration Services (USCIS) Director clarified that the fee applies only to new, unfiled petitions. Current visa holders can continue traveling to and from the United States.While SEMI recognizes the economic and strategic concerns raised by the administration, the high cost of the new fee poses a significant burden on SEMI members and the broader technology industry. As SEMI members continue to share the impact this policy will create on their operations, SEMI will work with fellow trade associations to address the high-cost of the fee and find solutions for the administration’s policy concerns.The proclamation cites misuse and calls "abuse of the H-1B program" a "national security threat." All entries under an H-1B visa beginning September 21, 2025, are restricted unless supplemented by the $100,000 payment. The administration must review this restriction annually, and DHS will issue implementation guidance. The proclamation also directs DHS to revise prevailing wage levels and prioritize "high-skilled and high-paid" applicants.The H-1B program currently caps new visas at 65,000 annually, plus 20,000 for those with U.S. master's degrees or higher. Employers must petition for these visas. Demand for skilled workers—especially in technology-driven industries like semiconductors—far exceeds the limited H-1B supply. The changes risk driving away U.S.-educated foreign graduates and their skills to foreign markets, further straining workforce needs.SEMI recognizes the impact of the proposed H1-B visa fee on companies, particularly the additional burden it places on smaller firms. While SEMI supports the administration’s objectives, the policy will create near-term challenges — especially for companies working to scale in order to meet the goals set by Congress and the administration to strengthen economic and national security. By straining the talent and resources these companies rely on, the fee risks undermining those objectives.In the coming days, SEMI will be gathering information to better understand the impact across the industry, with particular attention to smaller companies. This input will guide our communications with the administration as it refines the policy. We will also be meeting with member companies to assess the impact and prepare talking points for upcoming discussions with the administration.Next Steps: SEMI issued an initial statement recognizing the administration's economic and security concerns while urging collaboration on solutions that benefit economic growth and talent retention. SEMI will work with industry groups, the administration, and Congress to address H-1B challenges and help grow the American workforce while retaining global talent. SEMI is spearheading a letter to the administration highlighting industry concerns while expressing the desire to work together, and we will be inviting related industry associations and groups to join us. SEMI encourages members to share details on the anticipated impact of the policy on their operations. Please reach out to Christina Banoub at [email protected] policy aligns with forthcoming H-1B rulemaking that would weigh applications by wage levels instead of the current lottery system. The rule hasn't yet appeared in the Federal Register but should follow soon.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Royal Kastens, Senior Director of Public Policy and Advocacy at SEMI.

John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collaboration is the key to growing the semiconductor industry to $1 trillion and how we will get there.Smith: What is the major industry evolution or dynamic that's making collaboration essential today?Kibarian: The semiconductor industry has dramatically evolved from a simple, linear process to a complex, collaborative ecosystem. Previously, everything happened at the wafer fab. Testing occurred at wafer sort, package yields were high, final testing was straightforward, and products were shipped. Collaboration was mainly between foundries and fabless customers, intensive during early qualification and test chip stages, then evolved to routine yield monitoring once production stabilized.Today's advanced packaging puts multiple chiplets into single packages, creating an explosion of test insertion points. This has driven up both test complexity and costs significantly. Front-end fabs now house the most complex machines, while test and assembly facilities, once relatively simple, now feature sophisticated system-level testers with integrated robotics. Assembly tools have become highly complex, with die-attach processes requiring increasingly tight tolerances. Success now requires collaboration across the entire chain, from system companies to equipment vendors, both for new product launches and ongoing production maintenance.Companies are adopting AI and machine learning (ML) to manage these complex production flows, whether for testing or equipment control. This demands even broader collaboration since AI requires combining data from multiple sources across foundries, fabless companies, OSATs, equipment vendors, and more, data that no single entity controls. What was once a straightforward handoff between two parties has become an intricate web of interdependent relationships requiring continuous coordination.Smith: Chiplets and chiplet-based architecture is in the news and seems to be a key solution or practical solution in response to the slowing down of Moore's Law. This demands incredible levels of collaboration and coordination across the whole value chain. Is this doable at scale where it starts to move into the mainstream?Kibarian: The semiconductor industry will need unprecedented collaboration to make chiplet manufacturing work at scale. But this can be done! Consider EUV lithography: Initially expected during the 65nm generation, it took years longer than anticipated despite being an incredibly complex technology. Extraordinary engineering was needed but it also required extensive collaboration between ASML, suppliers, customers, and the broader fabless community.If the industry achieved this level of coordination for EUV, it can do the same for chiplets. However, chiplet manufacturing will require even greater collaboration as more companies will build systems using chiplets from multiple suppliers.Today's chiplet-based systems typically source all components from one manufacturer, making standards like UCIe less critical since companies control their entire supply chain. This will change as companies increasingly use third-party components for cost-effectiveness.More and more, we will see systems using components from multiple players to get to market more cost-effectively. Consequently, future production flows will be significantly more complex, requiring coordination of substrates and base dies, third-party dies and interposers, OSAT and specialized testers with specific configurations.This orchestration must work not just for initial bring-up but for the ongoing production as well, and when reconfiguring chiplet combinations for different products, all requiring rapid, automated responses.All of that must be automated for quick reaction. Considering the complexity of the manufacturing flow, people will want to apply AI/ML to anticipate what is going on in each individual product built.Manual oversight of every chip and package during manufacturing isn't feasible at scale. Automated AI agents must handle this monitoring and quality control. Expanding this automation will require close collaboration between the manufacturing entity and engineering teams at the product companies.This will also require a different level of alignment and orchestration across all the software packages managing this complex multi-company process. The financial enterprise resource planning (ERP) systems know where material is going, what the demand is, and what the forecasts are. While separately, the manufacturing execution systems needs to know which tools are going to be available when. Most often, these manufacturing systems operate in factories the product company doesn't own. The product company’s PLM systems control the bill of materials and test flows, but these tests will be conducted at the OSAT requiring complex coordination between the software systems of multiple companies controlling different process domains. This orchestration spans organizational boundaries and must be able to take data from upstream test results and make decisions on what tests to run downstream. This is required to get the right chiplets put together into a package in an efficient manner within a short cycle time and not require a Formula 1 pit team to keep everything running.Smith: The volume of data is staggering, especially now with design data. What will it take to enable this vision, at scale, where everything's connected? Kibarian: It’s a marriage of the human establishing the bounding box within which the systems operate that employ agents to do a lot of the work on a day-to-day or hour-by-hour basis. A good example is how manufacturing execution systems (MES) connect to ERP systems to share data. When a company sets up an orchestration, it creates rules that govern how information flows between systems. These rules tell the ERP system: "To calculate costs for each process step, here's the recipe information you should use."Once these rules are in place, they work like guidelines that control daily operations. An AI agent automatically creates insights based on actual data collected from the MES and moves data between systems according to these rules. The ERP AI agent will use this data to spot when costs are rising and send alerts, to notice when production yields drop, to calculate what lower yields mean for costs, and will take action to fix problems.This same process happens between equipment suppliers and manufacturing facilities. They share data automatically based on pre-set rules, and AI helps identify issues and take corrective action. Fabs determine who can access which machines and when, what types of data can be transmitted and through which channels, and how frequently these transmissions occur. When new software or AI models are introduced to run equipment, the systems specify what virus scanning and security checks must be completed before installation.Human operators primarily configure these control systems by determining the most effective collaboration protocols. However, the day-to-day execution is handled by automated agents due to the enormous scale involved, both in terms of data volume and the sheer number of transactions that occur continuously throughout operations.A human will not go through and review that data. I'll give two examples of this. One outside of our industry and one in our industry. At our 2019 user conference, board member Marco Iansiti, a Harvard Business School professor, shared insights from his book on AI in business. He compared traditional banks with Ant Bank, Alibaba's banking arm, which was experiencing explosive growth before Chinese government intervention.Ant's AI wasn't particularly sophisticated, but its process was revolutionary. While traditional banks require customers to fill out loan applications that then go to human loan officers for review, Ant's system would automatically scrape the internet and social media to verify applicant information. Within seconds, an algorithm would approve or deny the loan.The crucial difference is that Ant could scale exponentially because its only constraint was computing power. Traditional banks need to hire more loan officers to double their business, a human bottleneck that limits growth.I invited him to speak because I believed in this principle six years ago, and I'm even more convinced now.For the semiconductor industry, to build a trillion-dollar industry with complex, integrated systems, we need to minimize human intervention in data intensive processes. Despite the trust issues between stakeholders in our sector, collaboration remains essential. The solution requires establishing systematic principles that allow AI agents to operate autonomously. This is a way forward to achieving exponential growth.The Ant Bank example perfectly illustrates what our industry needs. At PDF, we believe this approach is crucial for industry advancement. Consider this: We manage petabytes of data, yet humans only examine 5-10% of it. This shows AI's potential to handle the vast majority of operations without human oversight.The reality is that our customers build millions of chips a week, billions a year. They cannot look at every dataset. Algorithms can, AI can. We launched a product called Guided Analytics last year. An engineer spoke about it during our user group last year. Her company has a couple of thousand products. Her group could not keep track of them every day, but Guided Analytics could. When her group came in the morning, the daily report noted 90% of the chips were fine or alerts pointed to where issues are. It's a simple AI bot crawling over data and identifying where the root cause seems to be.Our industry will require more agents to scale. Those agents will span the industry, and yet we as humans need to set up the governing principles under which they can operate. That's how we're going to deal with the massive amounts of design and manufacturing data to get the velocity the industry will need, and to benefit from the AI that we create for our businesses.Notes: Kibarian’s keynote, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” is scheduled for Wednesday, October 8, at 10:20 a.m.SEMICON West adds design to its program with “The Convergence of Semiconductor Manufacturing and Design” to highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session will be held Tuesday, October 7, from 1 p.m. until 4 p.m. Learn more about the design program in our latest blog. SEMICON West 2025 will be held in Phoenix, Arizona from October 7-at the Phoenix Convention Center. SEMICON West’s homepage has links to the full program, including more details about “The Convergence of Semiconductor Manufacturing and Design,” special features, sponsor and exhibits. Registration is open. About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

As the Department of Commerce explores options to adjust patent fees, these changes will have important implications for the semiconductor industry, where thousands of patents are filed each year to protect groundbreaking technologies. At SEMI, we understand the complexity of getting this right for our member companies. The fee proposal is not only about rates, but also about how fees are structured, applied across different types of filers, and administered in practice. Designing a system that is fair and workable is a significant challenge and one that requires close collaboration between government and industry. The SEMI Global Advocacy team is consistently engaged with the Trump Administration and Congress as a resource. We want to ensure the unique needs of the semiconductor sector are understood and that any adjustments to the fee schedule strengthen U.S. innovation without creating unintended barriers. By working together, SEMI members with U.S. operations can help shape an approach that supports the U.S. Patent and Trademark Office's mission and U.S. competitiveness. Next Steps: SEMI will continue to provide technical insight from across our membership as this process develops and looks forward to partnering with policymakers. We will also share updates as information on new patent fees become available beyond the initial reporting by the Wall Street Journal and other news outlets.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Scarlett Bickerton, Manager, Federal State Affairs at SEMI.

The semiconductor industry faces an unprecedented paradox: AI demand is booming, fab investments are rising, yet wafer shipments remain stubbornly flat. What's driving this disconnect, and when will it break?As of mid-2025, the global silicon wafer market appears calm on the surface, but underlying structural tensions are quietly mounting. The demand for AI semiconductors remains resilient, and certain high-value supply chains continue to operate near capacity. Yet wafer shipments have shown little sign of meaningful recovery—a divergence that raises questions about the conventional supply-demand playbook.SEMI's latest Silicon Wafer Market Monitor Report begins with a structural hypothesis: that the current market dynamics cannot be explained solely by weak demand or delayed orders. Instead, we propose that the demand pattern of fab operations itself has fundamentally changed.The Hidden Constraint: Time ExtensionOne critical metric has emerged as a structural bottleneck—fab cycle time, or the average duration for a wafer to complete its full process flow. Our quantitative analysis reveals that since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained.Why is this happening? Rising process complexity, increased equipment density, and tighter quality control requirements are absorbing more capital per wafer while paradoxically slowing production. Equipment spending per wafer area has surged over 150% since 2020, yet this investment translates into longer processing times rather than higher throughput.The High Bandwidth Memory (HBM) Economic ThresholdSimultaneously, the market is approaching a new inflection point driven by the rapid rise of HBM. HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand. However, HBM currently accounts for just 16% of total memory revenue—still below a critical economic threshold.Our analysis identifies that when HBM reaches 25% of total memory revenue, the trade ratio rises to 1.5. This is the structural breakeven point where CapEx per wafer for HBM-dedicated lines aligns with standard DRAM economics. At this threshold, memory makers gain clear incentives to expand wafer input, and customers become more willing to pay premium prices.The Quantitative FrameworkInstead of relying on conventional forecasts, we model the interaction of four critical variables—HBM penetration, DRAM bit growth, fab utilization, and cycle time—using a quantitative simulation framework. Under current conditions (16% HBM revenue share, 15% annual bit growth, 95% fab utilization, and 14.8% cycle time increase), wafer input would need to increase by 23.9% annually to meet projected demand.Yet no fab is scaling wafer input to that extent today. This suggests the market isn't demand-constrained but operating within a conditionally responsive system—one that won't activate until key thresholds align.Beyond Economics: Technical and Operational ReadinessThe slow pace of HBM expansion isn't solely about investment timing. Technical constraints including low yields, delayed customer qualification, and process stabilization challenges also play critical roles. These preconditions—investment readiness, yield optimization, and qualification completion—haven't yet aligned, keeping the market in strategic latency despite robust underlying demand.Additional factors compound this delay. Backend bottlenecks in Chip-on-Wafer-on-Substrate (CoWoS) packaging are causing semi-finished wafers to accumulate as inventory, constraining upstream wafer input. At the fab level, companies prioritize efficiency gains through process conversions over new construction. Meanwhile, macroeconomic uncertainty, geopolitical tensions, and foreign exchange volatility continue suppressing capital execution.The Three-Tier Response ModelThis structural shift creates a three-tier demand response across the supply chain:Wafer demand: Conditionally responsive, awaiting economic threshold alignmentEquipment investment: Process-transition driven, already responding to complexity increasesMaterials demand: Directly tied to cycle time extensions, with potential for early bottlenecksFor certain process-critical materials like EUV photoresists and TSV chemicals, supply constraints may emerge even before wafer input fully ramps, preceding equipment expansion.Strategic ImplicationsFor industry stakeholders, this analysis suggests three key actions: wafer suppliers should prepare scenario-based capacity plans around the 25% HBM threshold; equipment makers should anticipate process-transition driven demand regardless of current wafer volumes; and materials suppliers should prepare for potential bottlenecks as extended cycle times increase consumption per wafer.Crucially, the current stagnation shouldn't be interpreted as structural decline. Rather, the market exists in a state of strategic readiness, with key conditions not yet aligned. Once they are, wafer demand will likely respond nonlinearly—and momentum is already building in that direction.The structural inflection point (≈25% HBM penetration) and cycle time increase (+14.8%) serve as forward-looking indicators not just for wafer producers, but for the entire upstream supply chain. The question isn't whether this inflection will occur, but when. Companies that understand these structural dynamics and prepare accordingly will be best positioned to capitalize on the nonlinear demand response when it arrives.These key insights are from the market update section of the Q2 2025 Silicon Wafer Market Monitor Report. This quarter's analysis models structural inflection points using scenario-based projections across nine core charts and tables, offering data-driven perspective on the industry's readiness for the next demand shift. Download your free sample report today.For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on the complete SEMI market data portfolio are available at our Market Intelligence website. Sungho Yoon is a Principal Analyst in the Silicon Wafer Market Research at SEMI Market Intelligence.

On July 7, President Trump issued an executive order (EO) extending the ten percent baseline tariff rate through August 1, 2025. In addition, the EO suspends the variable "reciprocal" tariffs imposed under the International Emergency Economic Powers Act (IEEPA) until August 1. The order applies to nearly all countries except Mexico, Canada, and China. These changes do not impact separate reciprocal tariff actions on China or alter existing Section 232 measures on steel, aluminum, autos, and their derivative products. At the time of this posting, letters had been sent to 20 trading partners outlining expected tariff rates if no agreement is reached by August 1; bilateral negotiations are ongoing. Eleven of the 21 countries received rate cuts compared to the "Liberation Day" announcements on April 2, ranging from one to 13 percent. President Trump indicated rates could rise around 25 percent if trading partners retaliate. Next Steps: The extension offers short-term stability for SEMI member companies to assess supply chain exposure. SEMI continues to monitor bilateral trade and tariff policy negotiations, including for discussion related to the semiconductor supply chain. We aim to keep member companies informed of relevant tariff escalations. If your company is directly impacted by a country-specific rate shift, please reach out to your region’s SEMI Global Advocacy contact with any feedback on how these tariffs are affecting your operations.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Scarlett Bickerton, Manager, Federal State Affairs at SEMI.

In a letter sent to the United States Congress, SEMI, the leading industry association serving the global electronics design and manufacturing supply chain, and 16 member companies urged Congress include in reconciliation an expansion and extension of the Advanced Manufacturing Investment Tax Credit. The letter calls for the expansion of eligibility for the federal investment tax credit (ITC) to make the entire semiconductor manufacturing supply chain, as well as R D and design expenditures eligible for the ITC and extend the credit beyond the current 2026 expiration date—to allow sufficient time to plan and execute investments. The U.S. semiconductor market is growing to meet the needs of critical technology applications like artificial intelligence (AI), telecommunications, and bioengineering that rely on semiconductors. That growth requires increased investment for upstream materials, chemicals, and electronic design automation (EDA), which are currently excluded from receiving the tax credit (also known as Sec. 48D). Excluding these critical manufacturing and R D projects undermines domestic investment efforts potentially ceding U.S. leadership and competitiveness. Semiconductor infrastructure requires billions of dollars in upfront investment, and tax incentives are essential to help offset these exorbitant costs. A competitive tax environment encourages semiconductor companies to invest in the U.S., strengthening domestic manufacturing and innovation while helping the U.S. meet its goals of maintaining global leadership with lower-cost regions also providing incentives.Also, the credit expires at the end of 2026, leaving insufficient planning and implementation time for the billions in upfront investment required to support semiconductor infrastructure in the United States. To support the success, growth, and innovation of the U.S. semiconductor ecosystem, SEMI and its members urge Congress to include in the reconciliation package:Expansion of the Sec. 48D tax credit for the entire supply chain—as included in the SEMI Investment Act (S. 1642)Extension of the credit to allow enough time for businesses to plan and execute needed investments as included in the BASIC Act (H.R. 3204)Recognition of R D and design expenditures as eligible Sec. 48D projects as included in the STAR Act (H.R. 802)These inclusions are crucial to maintain U.S. competitiveness in attracting global semiconductor industry investments.The letter was signed by CEOs or presidents of the following leading companies: SEMI; ASML; ASM; Advantest America, Inc.; Axcelis Technologies Inc.; Brewer Science; Chemours; Dupont’s Electronics business, and Qnity™; Entegris; Evatec NA, Inc.; EFC Gases Advanced Materials; GlobalWafers Co., Ltd.; Lam Research Corporation; Micron Technology; Tokyo Electron America, Inc. TEL Manufacturing and Engineering of America, Inc.; SACHEM, Inc.; SkyWater Technology.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Christina Banoub, Senior Manager, Federal Affairs at SEMI.

The semiconductor industry has long followed a well-defined cyclical structure. Typically, price declines lead to a contraction in capital expenditure, followed by inventory normalization and eventual recovery. This repeated pattern—comprising pricing correction, investment pullback, inventory adjustment, and eventual market rebound—continues to offer a relevant lens through which to interpret the current uncertain market environment.As of April 2025, the industry faces a mix of conflicting signals. Concerns are rising that AI-related demand may have already peaked, while cautious optimism persists over a possible rebound in DRAM prices in the second half of the year. These market dynamics are further complicated by rising macroeconomic uncertainty, including renewed trade friction between the U.S. and China, reemerging tariff risks, and persistent inflationary pressure. In such a complex and volatile environment, the importance of cycle-based structural analysis has never been greater.Viewed from a momentum perspective, the recovery in semiconductor equipment investment—marked by a rebound in year-over-year growth (measured on a 12-month moving average basis) beginning in mid-2024—can be interpreted as a potential sign of renewed demand. However, this apparent stability may be misleading. While global companies significantly curtailed their fab investments throughout the second half of 2023 and the first half of 2024, China moved in the opposite direction, intensifying state-led expansion efforts aimed at achieving semiconductor self-sufficiency. This divergence in investment behavior has distorted the global capital expenditure landscape, potentially creating the impression of a broader recovery, while in reality the momentum remains concentrated in a single region driven by policy rather than market fundamentals.Similarly, the recent uptick in DRAM pricing appears to be driven more by production cuts than demand-side momentum. Major suppliers have been deliberately scaling back output to manage inventory and support pricing. In this context, price rebounds not backed by end-market demand are unlikely to sustain a meaningful recovery in wafer procurement. Simulation results—based on second-half projections—suggest that unless DRAM blended ASP increases by more than 20% quarter-over-quarter in both Q3 and Q4 2025, a meaningful upward inflection in the year-over-year pricing trend (on a 12-month moving average basis) remains improbable. This highlights the fragility of the current price recovery suggests that without a meaningful improvement in end-market demand—particularly for DRAM—wafer procurement for DRAM production is unlikely to recover in a sustained manner, regardless of supply-side actions. As SEMI highlights in this Silicon Wafer Market Monitor Report, a deeper understanding of the wafer market requires a close examination of raw material inventory trends. The inventory behavior of memory makers—due to their dominant scale and transparency—is widely regarded as a proxy for broader semiconductor industry trends. Following the pandemic, memory makers' raw material stockpiles surged to levels equivalent to five times their historical average relative to sales. While these ratios were significantly reduced between 2023 and 2024, inventory levels still meaningfully exceed pre-pandemic norms. With leading players signaling further inventory drawdowns, there is little incentive to rebuild raw material stockpiles—including silicon wafers—unless there is clear evidence of sustained demand recovery.This inventory dynamic is closely tied to wafer shipment growth. Historical data reveals a strong inverse relationship between raw material inventory-to-sales ratios at the top three memory makers—Samsung, SK hynix, and Micron—and wafer shipments. When this ratio declines year-over-year, wafer shipment growth typically improves. However, a slowdown in the pace of inventory ratio reduction could result in stagnant or declining wafer shipment growth in subsequent periods.Moreover, even as these inventory ratios continue to decline, wafer average selling prices (ASPs) have yet to show signs of recovery. This decoupling of pricing from inventory adjustments reflects the presence of a structural imbalance in supply and demand. On the supply side, all top five global wafer producers have secured greenfield fab capacity and are prepared to scale production. With depreciation pressures mounting, they face strong incentives to maintain economically viable utilization rates, contributing to ongoing ASP erosion.Meanwhile, chip capacity expansion in China—primarily driven by demand for 200mm applications—is adding further downward pressure. Chinese wafer suppliers, who already hold a meaningful share in China’s 200mm market, are now directing more of their investment toward 300mm wafer production—intensifying price pressure and adding to the longer-term competitive pressures facing global suppliers. This focus aligns with China’s broader push into mature process nodes, even as demand outside the region remains tepid. Accordingly, local Chinese wafer suppliers are competing aggressively on price, weakening the regional competitiveness of established global wafer players.As a result, the competitive landscape is undergoing a structural shift: global wafer suppliers are contending with intensified price-based competition among themselves in non-China markets, while simultaneously coming under mounting pressure from Chinese local players within China. This dual-front competition highlights the threshold point the industry has reached—where traditional pricing models and market dynamics are being fundamentally challenged.Moreover, long-term supply agreements (LTAs), once effective tools for pricing stability, are expected to gradually lose relevance. As semiconductor manufacturers—who purchase wafers under LTAs—move toward shorter-term and more customized purchasing models, and as pricing volatility increases, the incentive to commit to such agreements is projected to steadily diminish. The market, therefore, is not yet in a phase of strong recovery but appears to be undergoing a structural transition defined by persistent imbalances. The full report presents three scenario-based outlooks centered on four key variables—DRAM pricing, inventory normalization, equipment investment, and China’s regional influence. The most probable scenario currently assumes modest growth in 2025–2026, a correction in 2027, and a recovery in 2028. Wafer shipment growth rates under this scenario are projected at +5.1%, +5.4%, –6.2%, and +9.8%, respectively.However, even this base case remains vulnerable to potential macroeconomic disruptions. The large-scale tariff measures announced by the U.S. in April 2025 could trigger cascading effects across the ecosystem—from weakening enterprise demand and delaying infrastructure investments to softening DRAM prices and curbing wafer procurement. In past cycles, leading macro indicators such as the OECD Composite Leading Indicators (CLI) tended to lead DRAM price movements. If macro momentum slows, the market could deviate from the base case and move closer to the downside scenario. This downside scenario assumes weak or negative growth through 2026, a moderate recovery in 2027, and a stronger rebound by 2028 as supply-demand conditions begin to normalize.The current market trajectory suggests limited room for either sharp declines or sharp rebounds. The next phase will depend on how four forces interact: DRAM price momentum, inventory rebalancing pace, regional investment activity, and policy risks. A clear inflection point will only emerge when these factors begin to align. In other words, a meaningful shift—either upward or downward—will only occur when these forces move in the same direction and reinforce one another. Ultimately, any directional shift—whether delayed or accelerated—will still unfold within the broader framework of the semiconductor cycle previously discussed. In that sense, these indicators do not reverse the cycle itself; they merely influence the timing and pace at which it plays out.This article presents a summary of key insights from the Q1 2025 Market Update section of the SEMI’s Silicon Wafer Market Monitor Report, which is compiled in PowerPoint format and distributed as a PDF. In this edition, scenario-based analysis was used to navigate growing macroeconomic uncertainty and assess potential turning points in wafer demand. To support this analysis, the Market Update section presents 10 core quantitative charts and long-term data series dating back to 2000—particularly curated to visualize and analyze semiconductor revenue, investment, and pricing cycles in a single view. Separate from this focused section, the full SEMI’s Silicon Wafer Market Monitor Report includes a much broader array of charts and indicators, providing a multi-dimensional analysis of how fundamental variables interact to shape the future of the silicon wafer industry. Rather than simply offering background explanation, the full report is intended to provide clear, data-driven insights that can support strategic thinking amid market uncertainty.For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on SEMI market data are available at SEMI Market Data. Sungho Yoon is a Principal Analyst on the SEMI Market Intelligence team.

New pilot lines offer European innovators access to the most advanced semiconductor technologies for product development and validation.The global semiconductor landscape has undergone significant transformation in recent years. With disruptions such as the semiconductor supply chain crisis and the challenges it posed to the automotive sector, Europe’s dependence on external fabrication facilities, particularly in Taiwan, has become a pressing concern. In response, the European Union (EU) introduced the EU Chips Act, a comprehensive framework designed to reduce this reliance and boost Europe’s share of the global semiconductor market. ITF Chip into the Future, hosted by imec at SEMICON Europa 2024, was a pivotal event that brought together industry leaders, policymakers, and experts to explore the implementation of the EU Chips Act and the future of Europe’s semiconductor ecosystem. Jari Kinaret, Executive Director of the Chips Joint Undertaking (Chips JU)—the body overseeing the EU’s semiconductor investments—explained, “The Chips JU is about capacity building to drive semiconductor innovation in Europe. We will continue to be dependent on the rest of the world, but we want to make sure that the rest of the world depends on us as well.” Jari Kinaret, Executive Director, Chips JUEuropean research is driving progress towards sub-nanometer fabricationOne of the pilot lines, located at imec’s research center in Belgium, is focused on advancing methods that push Moore’s Law forward by achieving smaller and more efficient circuit features. As Luc Van den hove, President and CEO of imec, explained, “imec is now powering innovation for tomorrow’s chip designs, including stacked layers of chips, with each layer containing specific functionality implemented on chip processes optimized for each function. This allows us to scale much further than if all functionality had to be implemented on a single monolithic layer.”Luc Van den hove, President and CEO, imec Another pilot line, based in France and operated by CEA-Leti, is focused on pushing the limits of technology across multiple dimensions. CEA-Leti CEO, Sébastien Dauvé, explained that the goal of the FAMES pilot line is to advance “not only FD-SOI at 10nm and 7nm nodes, but also novel non-volatile memory technologies, RF components, 3D integration, and the development of small inductors for DC-DC converters.” Sébastien Dauvé, CEO, CEA-LetiAdvancements in 3D integration and chiplet technologies are closely tied to innovation in chip packaging. Christoph Kutter, Executive Director of Fraunhofer EMS, described how the Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems (APECS) pilot line in Germany is designed to meet the needs of industrial customers’ growing demand for advanced packaging solutions. Kutter noted “Customers told us that they needed to integrate logic and power, sensors and logic, and other combinations of functions. We have built the APECS pilot line to provide what they asked for.”Christoph Kutter, Executive Director, Fraunhofer EMSThe EU Chips Act is spurring investments not only in chip fabrication but also in the underlying technologies which support chipmaking. Emmanuel Sabonnadière, EVP at Soitec, highlighted how fabrication of advanced silicon carbide (SiC) power devices “is enabled by SmartSiC™ technology from Soitec – part of a built-in-Europe solution for silicon carbide.” Sabonnadière explained that SmartSiC technology “creates very thin layers of SiC material which make really differentiated substrates supporting the production of high-performance SiC devices.” Emmanuel Sabonnadière, EVP, SoitecInnovation in materials emerged as an important theme at ITF Chip into the Future. Julien Arcamone, Vice President of Corporate R D at ASM, described the critical role of materials for atomic layer deposition (ALD) in the advancing 3D semiconductor integration. Arcamone emphasized the importance of collaboration across the semiconductor value chain, describing ASM’s partnership with imec as part of “a win-win ecosystem.” Julien Arcamone, Vice President of Corporate R D, ASMDeveloping the skills to implement advanced semiconductor technologiesWhile the EU Chips Act is subsidizing the construction of new facilities including pilot lines needed for the hardware of the semiconductor industry’s expansion – the ITF speakers underlined the equally important “software” element of the semiconductor industry ecosystem: the knowledge and expertise of the people working in the industry. One of the biggest challenges in implementing the EU Chips Act is addressing Europe’s talent gap. Katrien Marent, Executive Vice President and Chief Marketing and Communications Officer at imec, said that the gap is in part “because students who graduate in STEM subjects are not trained in advanced semiconductor technologies.” From left to right: Katrien Marent, Executive Vice President and Chief Marketing and Communications Officer, imec; Julien Arcamone, Vice President of Corporate R D, ASM; Thomas Heurung, CEO, Siemens EDA; Frédérique Le Grevès, President STMicroelectronics France and Executive Vice President, Europe France Public Affairs, STMicroelectronics; Romano Hoofman, Director imec.IC-link, imec; and Christophe Frey, Vice-President of EU engagements Managing Director, ARM.Thomas Heurung, CEO of Siemens EDA, highlighted the need for educational reform in the electronics industry. He suggested that “we might not have the right degree-level curriculum for changing times in the electronics industry. We need to change the way that we train students at university, and we need more scope for early or mid-career training on specialist micro-curriculums aimed at a particular skill or knowledge set.”The industry also struggles to attract individuals. Frédérique Le Grevès, President of STMicroelectronics France and Executive Vice President, Europe France Public Affairs of STMicroelectronics, emphasizes the importance of rebranding the industry to attract new talent. She remarked, “The word ‘semiconductor’ itself isn't very exciting—it’s even off-putting to some. By simply changing the name of educational programs, we’ve seen significant increases in enrollment. This demonstrates the power of language in shaping perceptions and interest.”Thomas Heurung of Siemens EDA also called for a stronger emphasis on entrepreneurship, noting “there is a big contrast between Europe and the US, particularly Silicon Valley.” He explained how his company’s Cre8Ventures unit had been set up to help start-ups through the key stages of creating a successful new company, including product development, attracting funding, and bringing the product to market. Thomas Fleischmann, Program Manager at Robert Bosch, explained how the EU Chips Act has accelerated the formation of the European Semiconductor Manufacturing Company (ESMC) joint venture, in which Bosch is a key stakeholder. ESMC is building a new semiconductor fabrication plant in Dresden, dedicated to producing chips for the automotive and industrial sectors. Fleischmann emphasized that ESMC will play a crucial role in helping Europe “scale advanced technologies to high volumes at a competitive cost.”In addition, the EU Chips Act also provides a broader platform for the expansion of Europe’s deep tech capacity. This includes the creation of five pilot lines, which will offer European companies access to manufacturing capacity for prototyping at the most advanced semiconductor technology nodes.Thomas Fleischmann, Program Manager, Robert BoschITF Chip into the Future at SEMICON Europa 2024 highlighted the broad scope of the EU Chips Act – not only supporting the building of advanced fabs but also providing the foundations for technology development, production, and marketing – all aimed at supporting semiconductor innovation in Europe. SEMI ContactMaria Daniela Perez, Communications ManagerEmail: [email protected]

Leaders in the semiconductor industry are finding ways to balance rapid demand growth with strategies to mitigate the risks of geopolitical uncertainty and a complex supply chain.At the CxO Summit during SEMICON Europa, industry leaders gathered to share insights into the immense opportunities ahead for the semiconductor sector, as well as the challenges that could impede growth. Laith Altimime, President of SEMI Europe, highlighted how discussions last year centered on reaching $1 trillion in global sales by 2030. “The conversation today is about how far above $1 trillion we will be in 2030,” said Altimime. “Artificial intelligence is an amazing and exciting technology, and the semiconductor industry is at the heart of it.”Laith Altimime, President, SEMI EuropeAjit Manocha, President and CEO of SEMI, described the current state of the semiconductor industry with one word – “unprecedented.” Emphasizing quantum computing as the next growth driver after AI, Manocha urged leaders to prepare for the next landmark - $4 trillion in global sales by 2040. However, the challenges facing the industry are equally unprecedented. Manocha identified four key obstacles: geopolitical volatility, the Net Zero challenge, the competition for top talent, and supply chain disruptions. “We need to work together to solve these challenges – we need unprecedented collaboration,” he explained. Ajit Manocha, President and CEO, SEMIA European Perspective on the Industry’s ChallengesWith the CHIPS Act in the US and the European Union (EU) Chips Act, the industry is also seeing unprecedented governmental engagement. Gustav Kolbe, Acting Director of Enabling and Emerging Technologies at Directorate-General for Communications Networks, Content and Technology of the European Commission, explained that Europe had been deeply impacted by the effect of trade tensions and supply chain disruptions. “In the field of semiconductors, we realized that we cannot keep doing business as usual and expect to achieve more resilience and reduced dependence on non-European supply chains,” Kolbe said. Gustav Kolbe, Acting Director of Enabling and Emerging Technologies, DG CONNECT, European CommissionJari Kinaret, Executive Director of the Chips Joint Undertaking (Chips JU), which is responsible for implementing EU Chips Act programs, described how its projects amplify the effect of EU funding by leveraging matching contributions from member states and participating companies. “This means that our budget of €4 billion actually produces investments in the semiconductor industry of about €11 billion,” he noted. Jari Kinaret, Executive Director, Chips JUThe Chips JU funded projects are designed to position Europe at the forefront of advanced semiconductor technology. Belgium’s imec, for example, is operating a Chips JU pilot line focused on leading-edge semiconductor innovation. Luc Van den hove, President and CEO of imec, highlighted the potential for 3D integration, “We can now combine multiple chips through silicon interposers with very fast connectivity between them. This allows us to build compute platforms which are far larger than what can be made with a single silicon chip,” he explained referring to this approach as “CMOS 2.0.” However, Van den hove warned that Europe cannot achieve its goals alone, emphasizing the complex semiconductor value chain and the need for collaboration. “Self-sufficiency leads to mediocrity,” he warned, advocating for a global approach that leverages the “best of the best.”Luc Van den hove, President and CEO, imecStephan Haferl, Chief Executive Officer of Comet Group, introduced the CA20, a tool designed to improve efficiency and quality in semiconductor manufacturing. The CA20 uses advanced imaging and AI to quickly identify and address production challenges, such as defects in solder bumps, without damaging components. Now fully automated, it integrates smoothly into factory workflows, providing real-time information to help manufacturers maintain high standards and increase production yields. This innovation highlights the role of new technologies in overcoming key obstacles and driving progress in the semiconductor industry.Left to right: Isabella Drolz, Vice President Marketing Product Strategy, Comet Yxlon; Laith Altimime, President, SEMI Europe; Stephan Haferl, Chief Executive Officer, Comet Group; and Dionys van de Ven, President, Comet YxlonCarlos Mazure, Chief Strategy Officer at Institute of Microelectronics – A*STAR in Singapore, illustrated this point by highlighting the institute’s focus on advanced packaging, a key Singaporean strength. “We have built a state-of-the-art 300mm prototyping line, enabling companies to implement wafer-to-wafer and chip-to-wafer bonding as well as fanout chip packaging,” Mazure said. Carlos Mazure, Chief Strategy Officer, Institute of Microelectronics – A*STARTurning back to Europe, Pierre Barnabé, CEO of Soitec, highlighted materials science as a regional strength. Soitec’s engineered substrates are driving energy efficiency breakthroughs in electronic, acoustic, and photonic applications. “We can bond anything to anything, creating advanced substrates for any active layer,” Barnabé explained. Pierre Barnabé, CEO, SoitecKai Beckmann, Member of the Executive Board and CEO Electronics at Merck KGaA, Darmstadt, Germany, also emphasized the role of materials in enabling sustainable growth. “The semiconductor industry faces a challenge with the contribution of process gases to its total greenhouse gas emissions. We hope to solve the problem by using AI to support materials research, and to design new molecules – an approach we have learned from the pharmaceuticals industry,” Beckmann shared. Kai Beckmann, Member of the Executive Board and CEO Electronics, Merck KGaA, Darmstadt, GermanyCollaboration Strengthens the Semiconductor Supply Chain Despite the breadth of enabling technologies emerging from Europe, the rapid growth in semiconductor demand has not always been matched by a secure supply. Barbara Frenkel, Member of the Executive Board Purchase at Porsche, shared that the company is collaborating with the industry to improve its access to the chips needed for automotive electrification. This includes joining industry groups such as the SEMI Global Automotive Advisory Council (GAAC) and, as she said, “learning your language.” Frenkel added, “Porsche aims to emulate Apple’s approach with Intel and Motorola to drive innovation – we will do the same with suppliers of automotive chips.”Barbara Frenkel, Member of the Executive Board Purchase, PorscheAnother solution to supply constraints is to widen the supply pipeline. John Behnke, General Manager for Smart Manufacturing at Inficon, described how smart technology can significantly improve efficiency and output. “A semiconductor fab is 100 times more complicated than anything else in the world – it is a mathematical nightmare to model it. That gives massive opportunities for improved productivity if we can implement smart control technologies,” Behnke explained. John Behnke, General Manager for Smart Manufacturing, InficonThe Challenge of Achieving Sustainable GrowthWhile the prospect of exceeding $1 trillion in annual sales energizes the industry, there is widespread recognition that growth must not come at the expense of environmental responsibility. As the industry doubles in size in the 2020s, it cannot afford to double its use of resources, such as energy or greenhouse gas emissions. Frédéric Godemel, Executive Vice President for Power Systems and Services at Schneider Electric, shared that the biggest impact on sustainability could come from “energy frugality” – using energy more efficiently. He explained that implementing data fusion in a semiconductor fab – combining detailed analysis of the operation of chillers with external data sets, such as weather conditions to allow for more efficient use – results in energy savings of 10%. “This approach saved costs, reduced CO2 emissions, and provided a financial payback in less than one year,” Godemel said.Frédéric Godemel, Executive Vice President for Power Systems and Services, Schneider ElectricThe value of smart control in fab operations was also highlighted by Katharina Westrich, Global Vice President of Electronics, Semiconductors Simulation Digital Industries at Siemens. She described how Siemens makes digital twins of factories before they are built. “This is an approach that the semiconductor industry can also adopt,” Westrich said. “A digital twin enables more efficient allocation of resources to the fab and sub-fab, allowing simulation of fab operation and optimization of processes and resources.”Katharina Westrich, Global Vice President of Electronics, Semiconductors Simulation Digital Industries, SiemensThe semiconductor industry faces a future full of opportunity, yet also marked by significant obstacles—ones that delegates at the CxO Summit are now better equipped to tackle head-on.On behalf of SEMI, the SEMI Europe team would like to express appreciation to the industry leaders for sharing their visions and readiness to collaborate during the CxO Summit.SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

The silicon wafer market showed promising signs of recovery in Q2 2024, bouncing back after a prolonged downturn. The growth is fueled by seasonal factors and strong demand from investments in AI data centers, however, the consumer, automotive, and industrial segments are experiencing a slower pace of recovery. Historically, year-over-year (YoY) growth in semiconductor equipment investments tends to hit a low point before rebounding and typically contributing to an upward trend in wafer shipments. Figure 1 depicts this trend since 2001, with the only exceptions to wafer shipments following the rebound of fab equipment spending coming in the periods of the second and third quarters in 2002 and 2013, which are highlighted in gray. Figure 1* Notes 1) Data source: SEMI WWSEMS and SMG wafer shipments data 2) For semiconductor equipment spending, data from 2001 to 2024 is based on WWSEMS wafer processing equipment billing data 3) Equipment spending is updated through August 2024 This pattern underscores the crucial role of equipment investments in expanding production capacity and driving wafer demand. Following the rebound in equipment investment growth rates observed in 2024, projections indicate continued growth into 2025. This recovery in investments is expected to translate into increased wafer shipments, reinforcing a positive outlook for the silicon wafer market’s sustained growth.Additionally, the influence of DRAM Blended ASP (Average Selling Price) growth trends on wafer demand is significant. The historical data in Figure 2 shows that when DRAM ASP growth rates peak and then decline, wafer shipment growth tends to slow down after a lag. Figure 2* Remarks 1) Data source: SEMI SMG wafer shipments data and the Bank of Korea 2) DRAM ASP is updated through September 2024. With DRAM pricing potentially entering a downward trend in early 2025, this poses a key risk to the pace of the wafer market’s recovery. Looking ahead, wafer shipment growth is expected to vary by wafer type and diameter, with low to mid-double-digit growth projected for 2025, mid-to-high single-digit growth for 2026, and a notable slowdown in 2027. This forecast reflects evolving demand dynamics and ongoing market adjustments.In conclusion, the sustained recovery of the silicon wafer market hinges on a combination of increasing semiconductor equipment investments, the stabilization of raw material inventory levels among chipmakers, and careful monitoring of DRAM pricing trends. While the current upward trend in equipment investments is a positive driver for wafer shipments, the potential deceleration of DRAM Blended ASP growth poses a significant downside risk. If DRAM pricing exerts a sustained negative influence, it could shorten both the amplitude and duration of the current wafer market upcycle more than anticipated. This report not only examines these key investment and shipment dynamics but also provides an in-depth analysis of broader market trends, including supply-demand balances and pricing dynamics. By addressing these interconnected factors, it offers a comprehensive and forward-looking perspective on the long-term growth potential of the silicon wafer market.SEMI’s Silicon Wafer Market Monitor Report offers unique insights into global silicon wafer shipments, supply and demand dynamics, and average selling price (ASP) projections. This comprehensive quarterly report breaks down silicon shipments by region and wafer size, including 300mm, 200mm, and 150mm wafers, providing a detailed view of the market landscape.Semiconductor manufacturers, investors, and industry analysts rely on this report as an essential tool for making informed business decisions and exploring the latest data and trends shaping the future of the semiconductor industry.Download a sample of the Semiconductor Manufacturing Monitor report. For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on SEMI market data are available at SEMI Market Data. Sungho Yoon is Principal Analyst on the SEMI Market Intelligence team.