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Let’s celebrate! As of April/May 2020, Advanced Substrate News – or ASN for short, and now aka the SOI Consortium newsletter – has been bringing you news for 15 years. I hope you’ll forgive me if this post has a personal angle, as I have been the Editor-in-Chief since Day 1 back in 2005. One of the things I’ve learned over my career covering technology in general and SOI in particular is that “new” technologies are never really new. They don’t pop out fully formed like Venus Boticelli-style. They take years – decades, even. SOI is no exception. What is exceptional about SOI imho is that the ecosystem – from the substrate providers to the end-product designers – keeps finding new things to do with it. There have always been naysayers – and for a while it took on an quasi-fanatic ferocity. There were those who quipped that SOI was the technology of the future...and always would be. But as it turns out, SOI’s is, has been and will be the right technology at many right moments, and I don’t see any sign of that changing in the years to come. We Need a Newsletter! [caption id="attachment_32012" align="alignright" width="189"] My Design News piece on SOI from June 2000 - it changed my life![/caption] As so much in the SOI story, ASN began with Soitec. I first encountered Soitec when I was working as Contributing Editor in Europe for Semiconductor International in the mid 1990’s. It was a start-up of just a few people that made silicon-on-insulator aka SOI wafers. Most of us at the time had barely a notion of what that was all about, but they had an intriguing story to tell about higher performance and lower power. It so happened a few years later (circa 2000) I was also writing for another publication called Design News – not about chip design, but product design, for folks designing cars and consumer electronics and washing machines and such. I kept hearing a new requirement added to the product-design mantra of faster-smaller-cheaper: lower power. It seemed to me that these SOI wafers could go a long way in solving some of product designers’ challenges. I pitched a story to my editor and it wound up on the cover (those were the days some might remember when trade magazines were on paper…). The big players were IBM for digital (in a current-events aside, DKY that those big iron machines at the US national labs cranking on the solutions for the current pandemic use IBM FinFET-on-SOI chips? Just saying…), Philips (now NXP) for power/analog, and Soitec for wafers – and of course Honeywell for aerospace and the big electronics players in Japan for all sorts of things automotive and ultra-low power. Top management at Soitec read the piece and saw that I “got it”. They brought me on board as a consultant, writing early websites, PR, brochures and such. But also most importantly, they invited me “in” – I sat in on sales reviews and attended the big shin-digs they sponsored on the Riviera and in the Alps. The people I met there – and stayed in touch with – were many of the ones that drive the industry today. (Of course, that was then, this is now: I don’t have that insider status any more, but I’ve kept in touch with and often still rely on the expert advice of people I met during that heady time.) Anyway, one day at the end of 2004, the Soitec folks said to me, “We need a newsletter.” They asked me to come up with a concept they could pitch to the Board. Since Soitec was also doing GaN SiC at the time, I thought it should be called Advanced Substrate News – ASN for short. And we agreed it should involve the entire ecosystem: end users, equipment manufacturers, academics, suppliers of all sorts, and especially: chip designers. But it was not an easy pitch. Who’d want to read about SOI wafers, they asked? Wouldn't we run out of things to say after two or at most three editions? But the idea was a solid one: ASN could be a bully pulpit for the nascent SOI ecosystem. Happily it won the day. I was named Editor-in-Chief, and have held that title ever since. Our very first edition (we were a print quarterly then) had about a dozen articles on SOI, including automotive with Philips, ultra-low power FD-SOI with Oki for Casio’s G-Shock watches (oh yes – it goes back a long ways!), low-power (by a company that Arm then bought), high-performance, high-resistivity SOI wafers for RF…it was all there. And if you look at what we cover now, it’s still all there – albeit better than ever and growing fast. (I just listened to the most recent Soitec Q4'20 quarterly financial report audiocast – announcing that they’d just had their best quarter ever – largely driven by RF-SOI.) We Need a Consortium! In 2007, the SOI Consortium was created with 19 members (a dozen of whom are still members today). As ASN Editor-in-Chief, I was honored to be part of that effort, participating in the meetings where we hashed out what it was all about and what a consortium would do. It was a great opportunity to meet the movers and shakers across the industry, many of whom I’m still in touch with. We published steadily, as the years, technologies and applications came and some went, but ASN readership continued to grow worldwide. Then in 2015, I got an email from the head of the Shanghai Academy of Sciences, which had recently spun off an SOI wafer maker called Simgui. He was (and is!) an ASN reader (though now he’s China’s Vice-Minister of Science Technology). Would I come to Shanghai and present some of the SOI-based applications ASN had been covering to his team there? They’d been working on SOI in parallel for many years, and were interested in where it was going in Europe and America. That was exciting! My first trip (of many, now) to China, it coincided with Semicon China 2015 and the announcement of the “Big Fund”. It was hall upon massive hall of stands immense and tiny, and the level of excitement was nothing short of amazing. (I was one of the only Western journalists there, and essentially broke the story in a piece I wrote for Consortium member Applied Materials’ customer magazine). That trip opened a lot of doors for me and ASN. As the SOI Consortium teamed up to with partners in China to host symposia there, we devoted more and more extensive coverage in ASN to those exciting events. [caption id="attachment_32041" align="alignright" width="328"] Here's some of our core players at the SOI Consortium: Executive Co-Directors Carlos Mazure (also of Soitec) and Jon Cheek (also of NXP) on the far left and right, respectively, Event Manager Iris Rith in the middle, me (Adele Hars) next on the right. We're joined here by Lucy Dai (2nd from left) of Simgui.[/caption] Eventually in 2016, ASN moved under the aegis of the SOI Consortium. We’re quite a jolly band that I have the privilege of working with. Granted at the time of this writing, the world is a difficult place, with so much uncertainty. But there are exciting times ahead with new products and technologies enabled by SOI, and you can be sure we’ll be covering them. RF-SOI will continue its juggernaut path in 5G mmWave. FD-SOI is steadily defining the new mainstream at the edge. The huge amounts of data the world is generating is driving photonics (which is all about SOI) to new heights. SOI for power (meaning high-voltage – think smart power) and imagers continues to grow. [caption id="attachment_32045" align="alignleft" width="99"] That's me - Adele Hars, ASN Editor-in-Chief - at the SOI Consortium's 2019 FD-SOI Symposium. (Photo courtesy VeriSilicon)[/caption] I’m honored to have brought you ASN for the last 15 years. Our archives are truly a treasure trove, and our mailing list of over 2500 really is an industry who's who. We’ve published well over a thousand (!) pieces in that time, most of which I’ve written with guidance from many an expert. However, we of course encourage our readers to pitch stories and/or submit SOI articles for publication consideration - so please, don't hesitate! I want to thank you all for your interest and your continued support. And thank you especially to all the SOI experts out there who so generously – and so patiently – share their time and enthusiasm with me and our readers. Stay safe! With warm regards, - Adele P.S. If you're not already on our emailing list and would like to join, just fill in the form at the bottom of this page. Thanks!

As a leading TCAD provider, Silvaco has very deep SOI roots, reaching back over 20 years. When Oki* pioneered the first FD-SOI chips in 2000 (really? yes!), whose tools did they use? Silvaco's. And those early FD-SOI chips went into Casio's most advanced G-Shock watches in 2005. (Yes, ASN has been covering FD-SOI for a long time!) But note that while those earliest chips used fully depleted architectures, they were on regular – not ultra-thin – SOI wafers, as they are today. [bctt tweet="Deep Roots: When Oki pioneered the 1st FD-SOI chips in 2000 (really? yes! for #CasioGShock) look whose tools they used: @SilvacoSoftware #FDSOI #lowpower #chipdesign #semiconductor #semiEDA" username="@soiconsortium"] When we look at the IEEE Spectrum Digital Library, it’s clear that Silvaco is continuing to be very active in the SOI space. There are 72 conference and journal publications citing Silvaco for their SOI research simulations since the year 2000 and 27 in the last five years. They’ve supported all the SOI evolutions – including partially-depleted SOI up through and including today's FD-SOI on ultra-thin SOI wafers. There are two Silvaco presentations that were given in Japan last fall – they're now on the SOI Consortium website. A Bit More About Silvaco Headquartered in Santa Clara, CA and founded in 1984, privately-held Silvaco is a leading provider of TCAD tools. TCAD (short for Technology-Computer Aided Design) is the use of computer modeling and simulation in developing semiconductor devices and processes. As such, TCAD tools reduce the development cost and shorten the development time. Silvaco also provides a full suite of analog and custom design tools spanning schematic, layout, signoff and variation analysis. The portfolio also includes tools for power integrity sign off, reduction of extracted netlist, and production-proven IP cores for automotive, consumer, and industrial applications. Silvaco provides a full TCAD to custom circuit design flow for vertical markets including: displays, power electronics, optical devices, radiation soft error reliability, analog circuits, library and memory design, advanced CMOS process, and IP development. They have 500+ customers in worldwide, and market leadership in TCAD design solutions for flat panel displays and power devices. Recent SOI Presentations Here's a quick recap of the two Silvaco presentations from the Japan SOI Symposium, October 2019, which you'll find on the SOI Consortium website. (To view the full presentations, however, your company needs to be a member of the Consortium.) Silvaco RF-SOI TCAD Solution was given by Sun Tao, Applications Engineering Manager, Silvaco. Silvaco positions itself as a “cost-effective partner to the FD-SOI community.” And as the presentation title indicates, it's a review of the tools Silvaco offers that support SOI – especially for RF applications. The presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory Process for speeding up 2D/3D process simulations, and Victory Device for device simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – flow, semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. [caption id="attachment_31635" align="aligncenter" width="589"] An example of how Silvaco Victory Tools Support Detailed Simulations of RF Devices on SOI (Courtesy: Silvaco and the SOI Consortium)[/caption] Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the distortion from the active device, device biasing, and substrate, all of which can be co-optimized using Victory Process and Victory Device. In conclusion, he notes that Silvaco is offering TCAD to custom EDA solutions for predictive and comprehensive FD-SOI design work that can save money before committing to silicon. Platform Infrastructure for SOI-IP Ecosystem was given by Thomas Blaesi, VP of Global Marketing, Silvaco. "The massive use of IP is both an advantage and a challenge," began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians, and support folks use various systems, while procurement, finance, and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance, and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. [bctt tweet="One of the first beneficiaries of the Xena IP repository from @SilvacoSoftware will be the SOI ecosystem, as providers of SOI IP are already signing on. #FDSOI #RFSOI #semiconductorIP" #lowpower #chipdesign username="@soiconsortium"] Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that cannot be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. [caption id="attachment_31634" align="aligncenter" width="591"] Silvaco's Xena Supports Audits of IP Usage in SoC Projects (Courtesy: Silvaco and the SOI Consortium)[/caption] It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. -- *Oki's now part of Lapis Semi, btw, which is still active in FD-SOI

GlobalFoundries recently announced that its embedded magnetoresistive non-volatile memory (eMRAM) has entered production on the company’s 22nm FD-SOI (22FDX®) platform. (See the full press release here.) The company says this advanced embedded non-volatile memory on its FDX™ platform provides a cost-effective solution for low-power, non-volatile code and data storage applications. It is now working with several clients with multiple production tape-outs scheduled in 2020. GF heralds the announcement as a significant industry milestone, demonstrating the scalability of eMRAM as a cost-effective option at advanced process nodes for IoT, general-purpose microcontrollers, automotive, edge-AI, and other low-power applications. [caption id="attachment_31334" align="alignright" width="485"] (Courtesy: GlobalFoundries. Click to enlarge.)[/caption] “We continue our commitment to differentiate our FDX platform with robust, feature rich solutions that allow our clients to build innovative products for high performance and low power applications,” said Mike Hogan, senior vice president and general manager of Automotive and Industrial Multi-market at GlobalFoundries. “Our differentiated eMRAM, deployed on the industry’s most advanced FDX platform, delivers a unique combination of high performance RF, low power logic and integrated power management in an easy-to-integrate eMRAM solution that enables our clients to deliver a new generation of ultra-low power MCUs and connected IoT applications.”[bctt tweet="In production! @GlobalFoundries’ eMRAM on #22FDX FD-SOI replaces #eFlash for #IoT genpurpose #microcontrollers #automotive #edgeAI more. #lowpower #chipdesign #FDSOI" username="@soiconsortium"] [caption id="attachment_31330" align="alignleft" width="467"] (Courtesy: GlobalFoundries. Click to enlarge.)[/caption] Designed as a replacement for high-volume embedded NOR flash (eFlash), GF’s eMRAM allows designers to extend their existing IoT and microcontroller unit architectures to access the power and density benefits of technology nodes below 28nm. It is a highly versatile and robust embedded non-volatile memory (eNVM) that has passed five rigorous real-world solder reflow tests, and has demonstrated 100,000-cycle endurance and 10-year data retention across the -40°C to 125°C temperature range. The FDX eMRAM solution supports AEC-Q100 quality grade 2 designs, with development in process to support an AEC-Q100 quality grade 1 solution next year. [caption id="attachment_31331" align="alignright" width="280"] GF’s state-of-the-art 300mm production line at Fab 1 in Dresden, Germany, will support volume production of 22FDX with MRAM. (Courtesy: GlobalFoundries)[/caption] Custom design kits featuring drop-in, silicon validated MRAM macros ranging from 4 to 48 mega-bits, along with the option of MRAM built-in-self-test support is available today from GF and their design partners. eMRAM is a scalable feature that is expected to be available on both FinFET and future FDX platforms as a part of the company’s advanced eNVM roadmap. GF’s state-of-the-art 300mm production line at Fab 1 in Dresden, Germany, will support volume production of 22FDX with MRAM. Prior to this announcement, an excellent GF blog by David Lammers recapped GF's 2019 IEDM presentation of their eMRAM reliability data. You can read that here. It also provides a lot of interesting background information.

Dear SOI Community, The ongoing pandemic of the CoronaVirus COVID-19 has impacted the whole world. Governments are reacting strongly to contain the spread of the pandemic. Gatherings, conferences and meetings are not possible today. Health and safety are the priority. We have postponed our May events. We follow the evolution of the pandemic and we will update you with the June and July workshops. We are committed to ensure the quality of our conferences at a later date. Please take note of the updates for the Consortium events: Singapore Electronics Week (26-29 May) co-organized with Singapore Semiconductor Industry Association and Semi SEA: postponed to 1Q2021 SOI Silicon Valley Symposium (19 May), DoubleTree Hotel, San Jose, CA: December 1st, 2020 SOI Photonics Workshop hosted by Semicon West (22 July), Virtual Event 8th FD-SOI Forum and RF-SOI/5G International Workshop (16-17 September), Shanghai: maintained till further notice Member event: LETI Innovation Days, Grenoble, France: October 12-16, 2020 We will communicate the updates and confirm new dates as soon as we have enough visibility. If you have any questions, please contact us. We thank you for your understanding and support. Looking forward to hosting you in our events later this year. Stay safe! Very best regards, Carlos Mazure, Chairman and Executive Director Jon Cheek, Executive Director SOI Industry Consortium

The chip design ecosystem finally has the book it’s been clamoring for: The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems. [bctt tweet="The FD-SOI Chip Design Book: Yes, It’s Finally Here!" username="@soiconsortium"] The editors (who have also contributed chapters) are Andreia Cathelin, Sylvain Clerc and Thierry DiGilio, all world experts from STMicroelectronics. As Cathelin and Clerc note in the introduction: “The aim of this book is to introduce to the design community the straightforward design solutions in any modern FD-SOI planar CMOS technologies, by taking full advantage of body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode. All design techniques are based on the classical pillar of regular planar CMOS devices. As the first fully industrial solution has been the 28nm FD-SOI CMOS technology from STMicroelectronics, all the design examples in this book have been demonstrated within this process integration frame.” [bctt tweet="The Fourth Terminal...taking full advantage of (FDSOI) body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode" username="@soiconsortium"] The folks at ST were really the first to get into FD-SOI in a big way – in fact they’ve been at it for over two decades (!) so you’d be hard pressed to find experts at a company with deeper expertise. [caption id="attachment_29610" align="alignnone" width="535"] The Fourth Terminal team friends sporting Tour de Fourth Terminal t-shirts at ISSCC 2020. From left to right: MIT Prof. (and Series Editor for Springer's Integrated Circuits and Systems) Anantha Chandrakasan; Charles Glaser, Springer Editorial Director; Laurent Le Pailleur, ST; Andreia Cathelin, ST Fellow; Sylvain Clerc, ST; Stanford Prof. Boris Murmann (Photo courtesy Springer STMicroelectronics)[/caption] The Fourth Terminal is structured to cover three major areas: a technology overview (including body biasing for digital, analog and SRAM); a selection of circuits that illustrate body biasing in various fields; body bias deployment in mixed-signal and digital SoCs. The initial response has been tremendous. Editor Andreia Cathelin reports that posts she's made about it on LinkedIn were quickly viewed 10k times and more. Then came the book review by the eminent Stanford Professor Boris Murmann, who heralded its tour de force status in a clever turn of phrase: “With the help of a renowned international team of experts from industry and academia, the editors have distilled everything you need to know about FD-SOI circuit design into a 16-chapter "tour de fourth terminal". (Read his complete review here).[bctt tweet="Stanford Professor Boris Murmann calls this book a #Tour_de_Fourth_Terminal. #FDSOI #lowpower #chipdesign" username="@soiconsortium"] EETimes journalist Junko Yoshida blogged about it as Body Bias Gets Its Own Book (read that here), which generated lively discussions on LinkedIn (and underscored just how necessary this book is!). The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems is part of the Springer Integrated Circuits Systems Series -- considered by many to be the most prestigious in the industry. Weighing in at 431 pages, The Fourth Terminal is available in both e-book and hardcover versions. See the Springer website to order this must-have addition to your library.

The GAP9, GreenWaves Technologies latest IoT application processor -- which is being fabbed on GlobalFoundries 22FDX (FD-SOI) technology -- will be sampling in the first half of 2020, according to EETimes (read the whole article here). Mass production is slated for 2021. Greenwaves (which has been an SOI Consortium member for several years now) is a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for AI processing in sensing devices at the very edge. GreenWaves marketing director Martin Croome told EETimes, “We are using the body biasing ability in FD-SOI to allow us to achieve even lower power consumption.” Compared to GreenWaves’ currently shipping product, GAP8 (which is on a 55nm bulk process), GAP9 reduces energy consumption by 5 times while enabling inference on neural networks 10 times larger. This is thanks to architectural enhancements and the move to GF's 22FDX semiconductor process. The new chip delivers a peak cluster memory bandwidth of 41.6 GB/sec and up to 50 GOPS combined compute power at an overall power consumption of 50mW. It enables customers to embed machine learning and signal processing capabilities into battery operated or energy harvesting devices such as IoT sensors in smart building, consumer and industrial markets and consumer and medical wearable devices. GAP9 was showcased at the last RISC-V Summit in San Jose (read the full press release here). [caption id="attachment_29061" align="alignnone" width="400"] GAP9 Block diagram (Courtesy: GreenWaves)[/caption] Some of the (many!) features include: 10 identical high performance, extended ISA, RISC-V ISA cores (cluster of 9 cores for compute-intensive tasks and a fabric controller core for control and communication) Dynamic voltage frequency scaling and automatic body biasing Multiple power states: deep sleep, deep sleep with retentive RAM, low activity, SOC on, SOC on cluster on Click here for a full GAP9 product brief.

It should really be called SOI photonics – not just silicon photonics, quipped Soitec CTO Christophe Maleville at the SOI Consortium Japan event last fall. You’ve got to have SOI for the waveguides. There are megatrends driving significant growth in photonics – and they were all covered at the event. This is the final post in our coverage of the SOI Consortium’s Japan event (thank you for your patience!). It covers the photonics-related presentations by Soitec, Leti, Cisco/Luxtera, GlobalFoundries, Cadence and TowerJazz. Most of these presentations are now posted on the SOI Consortium website – you can access them if your organization is a member of the consortium. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. In case you missed our previous posts about the event, you’ll want to go back and read them, too. The first post covered the 5G/RF-SOI presentations by ST, Toshiba, Incize, GF, Silvaco and Sitri – you can read it here. The second post on the event covered eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC – you can read that here. Note that you can click on any of the illustrations to see enlarged versions. And now without further ado, here are the summaries of the photonics presentations. SOI Enabling Photonics – Ecosystem and Market Outlook – by Aziz Alami-Idrissi, GM Specialty SOI, Soitec. [caption id="attachment_28773" align="alignleft" width="233"] (Courtesy: Soitec SOI Consortium)[/caption] The megatrends in SOI photonics are: 5G (for more bandwidth, HPC, edge quantum computing), data centers (for high data rate transceivers and high-switch bandwidth), sensors (lidar, gas/chemical and gyroscopes) and biosensors (especially for medical). These are driving big changes: the 44% CAGR means the market is growing from a current TAM of about 500M$ to over 4B$ in 2025. One thing that’s really interesting is the expansion of the photonics market into these new fields in the next few years. While in 2019 90% of the photonics market served data center applications (the other 10% is for long haul), in 2025 optical I/O’s will account for over a third of the photonics market TAM. The other applications making an impact include AI, quantum, lidar (which will move into high-volume manufacturing in 2024) and medical sensors (hitting high-volume in 2023). For its part, Soitec is strengthening its portfolio with 8” and 12” large product coverage, new product sampling engaged, and extended features including newer engineered layers and RF immunity. Advanced Silicon Photonic Solutions Leverage SOI Technology – Eleonore Hardy, Business Development Manager, Silicon Photonics, CEA-Leti [caption id="attachment_28769" align="alignright" width="358"] (Courtesy: Leti SOI Consortium)[/caption] Leti helps companies make photonics products they can bring to volume foundries, explained Hardy. (btw, they’re presenting 21 (!) papers – including 5 invited – at PhotonicsWest 2020. Read about that here). You want to do integrated photonics to bring down costs, reduce power consumption, and scale (for higher volumes and reduced footprint). There are essentially three substrate choices: InP, SiN or SOI. SOI uses CMOS processes, so it’s low-cost and can be used in high-density photonic integrated circuits. What about the laser? Leti has developed III-V on silicon bonding, so you can have the laser on 4” III-V with a 300mm CMOS process (this is what Intel’s doing). They’re moving to 300mm wafers, 3D and advanced packaging. While communications is the big application realm, Leti is also applying photonics in automotive, medical, environment and computing. In the computing realm she gave the example of the European QuantERA SQUARE (Silicon Photonics for Quantum Fibre Networks) project for which Leti is doing the quantum emitter for absolute security and computing, wherein the transceiver/receiver for quantum cryptography integrates a hybrid III-V on silicon pump laser. Other examples of their work include miniature, low-cost and agile lidar for automotive and industrial applications (they’re working on a beam-steering emitter for an optical phased array). GlobalFoundries Silicon Photonics Solutions for Wired Infrastructure – Anthony Yu, VP, GF [caption id="attachment_28770" align="alignleft" width="684"] (Courtesy: GlobalFoundries SOI Consortium)[/caption] GF is giving their photonics business a big push. Optical interconnects are the future, said Yu, so they’re putting a lot of money into it. With data streaming multiplying by 3x/year and a current foundry TAM of $63 billion, the opportunity is huge. Fab 10 in Fishkill runs their 90WG process on 300mm wafers. A new process, 45CLO (also on 300mm) for O and C bands is going into the Malta fab. A big focus here are optical transceivers that convert RF signals to light. They see RF on SOI in a monolithic solution is needed to serve 100Gbs applications. They’re also moving to co-packaging optics: the packing technology will surround it with photonic chiplets. Customers have indicated that pulling the signals off the chips is limited by power, so they’ve worked hard on the fiber attach with MEMS and packaging technology for co-packaging. GF relies on substrate providers for high-quality SOI, and they have a world-class development team, he concluded. Integrated Electro-Photonics Design Platform – A multi-physics, multi-fabrics system design solution – Scott Li, Sr. AE Manager of Custom IC Platform, Cadence [caption id="attachment_28771" align="alignright" width="374"] (Courtesy: Cadence SOI Consortium)[/caption] This talk focused on photonics design challenges and solutions – including the CurvyCore™-based PDK for waveguide creation modal properties calculation that Cadence will soon be announcing. It’s a math-based engine that generates complex curvy shapes to support photonics. The first design challenges, said Li, are at the circuit level: how to do the schematics. The detailing tools, timesteps management and circuit simulation need to give the user the best performance. Cadence is working in close collaboration with a company called Lumericable on this. The next set of design challenges come at layout – especially generating curvilinear layout for any shape so that there are no gaps in connections. This is where CurvyCore comes in, fully automating layout and making it easy to modify. This includes place route, DRC and LVS for curvy shapes. The final challenge is at the system level. There is work to do here, but Cadence is collaborating closely on solutions with key partners. The ultimate goal is for photonics layout and editing to be available with all the features designers get in electronics editing. Silicon Photonics for High Volume and High Performance Optical Interconnects Applications – Thierry Pinguet, Technical Leader Engineering, Cisco /Luxtera [caption id="attachment_28772" align="alignleft" width="396"] (Courtesy: Cisco/Luxtera SOI Consortium)[/caption] Over the last decade there’s been steady growth in optical high speed interconnect solutions, mainly driven by HPC, enterprise, and especially the hyperscale datacenter. The largest volumes are for intra datacenter interconnect (between servers). Now mobile applications for backhaul are also driving volume for high speed optical interconnect for 5G network implementation. ASICs and photonics are getting closer as the industry moves to put them in the same package. But everybody does silicon photonics differently (even within Cisco). Luxtera tries to use the same infrastructure as electronics, but patterning is still a challenge: it’s not 90o “Manhattan” style. The wafers are no problem – they work with leading wafer suppliers like Soitec and SEH. They have explored a “double SOI” substrate (like a mirror), which showed large insertion loss improvements in grating couplers . For the electronics and the laser (MEMS), they do a micropackage, although at one point they also did monolithic integration. For better performance, they’re moving to TSVs. A hot topic is ASIC and photonics co-packaging. You can use optical tiles, but then the light is remote, like a power supply. No matter how you do it, though, the bottom line is that silicon photonics is the only way forward for the data center. PH18: World’s First Open Commercial Silicon Photonics Process and PDK from TowerJazz – Masanobu Kumazaki, Engineer, TowerJazz. This presentation was given in Japanese without translation into English, and is not available on the consortium website. But the slides showed at the event indicated that their PH18 is the world’s first open commercial silicon photonics offering. For optical transceiver components, silicon photonics provides another opportunity for a specialty foundry. It is a high-growth market. The TowerJazz offering is 220nm SOI, and uses standard EDA tools from Synopsys, Cadence and Mentor for design flow.

Digitimes Research is predicting a doubling of the global SOI market between 2019 and 2024, "...thanks to significant expansion in applications to mobile devices, communication infrastructure, IoT devices and automotive electronics in the 5G era...". (Read the full article in Digitimes here.) Beyond the continued enormous success of SOI in front-end modules (FEMs) for RF (aka RF-SOI, which as we know is found in every smartphone on the planet), the report cites high growth specialty areas such as imaging chips for smartphones and photonics in data centers. They also predict that FD-SOI will be "massively applied" in 5G, with applications in base stations and data centers. And of course, low voltage and low power consumption will be the big drivers in IoT and wearables. All this is driving Soitec, the major SOI wafer manufacturer, to expand capacity at its facilities in France and Singapore in 2020, says the report. This is happening in strategic cooperation with Shanghai-based Simgui. As noted in ASN about a year ago, Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. At that time the two companies redefined their manufacturing and licensing relationship to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics. Separately, Okmetic of Finland, which specializes in SOI wafers for MEMS, sensors and RF, is also doubling its capacity (we covered their 2019 Shanghai presentation here.) (Image courtesy: Soitec)

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

The industry continues rewarding luminaries of the SOI ecosystem. Recently recognized are Jean-Pierre Raskin for RF-SOI, Lattice Semi and NXP for FD-SOI products, and Bich-Yen Nguyen for her work in SOI. The SOI Consortium extends hearty congratulations to all the winners and their teams. Professor Jean-Pierre Raskin was awarded by the prestigious Médaille Ampère 2019 for the originality of his scientific work in the field of RF-SOI technologies for wireless communication. The international award was delivered by Mr. François Gérin, president of the SEE - Société de l'électricité, de l'électronique et des technologies de l'information et de la communication, on December 3rd, 2019, in Paris, France. We’ve long covered the work of Professor Raskin and his UCLouvain team – which is largely responsible for why SOI is in every smartphone on the planet. It’s a great story (read it here) and it goes on! In his Ampère acceptance speech, Professor Raskin said, “...significant industrial research and development is being performed toward fully integrated SOI front-end-modules. Notably, the 45nm PD-SOI [RF-SOI] and 28nm and 22nm FD-SOI nodes are being extensively designed with to develop 5G mm-wave low-noise amplifiers (LNA), power amplifiers (PA) and switches, in particular at 28 GHz. […] Overall, SOI is expected to be a big contender as a technological platform to enable mass production of millimeter wave 5G and ultra-low power RF IoT devices and products in the near future.” [caption id="attachment_27119" align="alignleft" width="294"] Lattice CEO Jim Anderson (left) and Mark Lipacis (right), Managing Director of Jefferies (Courtesy: GSA Lattice Semi)[/caption] Lattice Semiconductor was the recipient of the Global Semiconductor Alliance’s (GSA) 2019 Analyst Favorite Semiconductor Company award based on technology and financial performance. The GSA awards recognize the achievements of top performing semiconductor companies and the 2019 winners were announced at the annual GSA Awards Ceremony held on December 5, 2019. In thanking his team, Lattice CEO Jim Anderson, added, "We are even more excited about the solid execution of our product roadmap, specifically, the accelerated product rollouts of both CrosslinkPlus and our next generation FPGA platform based on FDSOI technology, which will be key catalysts to our achieving sustained long-term revenue and profitability growth.” [caption id="attachment_27120" align="alignright" width="71"] (Courtesy: NXP)[/caption] NXP was a recipient of a Best-in-Show Award at the 2019 Arm TechCon this fall. As was noted by Brandon Lewis, Editor-in-Chief of Embedded Computing Design, “The i.MX RT1170 crossover MCU marks a technology breakthrough in MCUs, running up to 1GHz while maintaining low-power efficiency. It is architected to deliver a record-setting performance, with a 6468 CoreMark score and 2974 DMIPS while executing from on-chip memory. The solution uses advanced 28nm FD-SOI [note: fabbed by Samsung Foundry] technology, making NXP the first company to build MCUs in this advanced technology node. This new MCU family is redefining the "edge" and MCU landscape, bringing unprecedented performance and high levels of integration to propel industrial, IoT, and automotive applications.” And finally, Soitec Senior Fellow Bich-Yen Nguyen was elevated to the status of IEEE Fellow in the Class of 2020 “for contributions to silicon on insulator technology”. As previously noted in her IEEE bio, “Her honors and awards include the Dan Noble Fellow, the highest technical award at Motorola; the Master of Innovation Award; and the first national Women in Technology Lifetime Achievement Award. She holds over 200 worldwide patents and has authored more than 180 technical papers on integrated circuit technologies.”