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By Sowmyan Rajagopalan, Founder and CTO, Thalia Design Automation FD-SOI is receiving significant traction with analog designers, but analog IP reuse often equates to tough choices. Porting chips from bulk to FD-SOI or creating new chips on FD-SOI means making decisions on porting existing bulk IP or starting from scratch. To invest the time and resources in reusing an analog IP requires a judgement call on the potential returns from the market and the time it takes to get the IP to that market to generate revenue is key – if a competitor's project hits the market first, then the potential returns are greatly diminished. There is also a need to understand the differences in process technologies and the impact those differences have on the efficient reuse of analog IPs. All this means that the demands on resources and time are high. Decisions, decisions A typical decision fork faced by many companies is whether to design new IPs, or if they should instead build a portfolio of analog IPs. Given the opportunity cost, availability of resources, time and resources needed for each option means that doing both is a difficult option. Both have their advantages; designing new IPs allows companies to branch out and address new sectors or markets. New IPs often demand higher revenues and engages in-house designers as the work, by its nature, is more innovative and challenging. On the other hand, building a portfolio of analog IPs allows companies to expand in an existing market, bringing stabilisation and strengthening revenues from existing product sectors. But why should you have to choose when there’s a third option? Have your cake and eat it It is difficult for a company to drive both options internally – not least because there’s a paucity of good analog designers in the market, and the opportunity cost is simply too high. However, the good news is that firms like Thalia have the specialist expertise and toolsets required build a portfolio of analog IP, saving time and investment while in-house designers focus on new IP design. Looking back Over the last 18 months, there has been a rapid uptake of FD-SOI process technologies. With production at foundries such as GlobalFoundries and Samsung now in full swing, more and more analog designers are reaping the benefits of FD-SOI. At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customers on projects that use FD-SOI technology. [bctt tweet="More more analog designers are reaping the benefits of #FDSOI. At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customers on projects that use FD-SOI technology. - @Thalia_IP_Reuse CTO " username="soiconsortium"] Driving the shift to FD-SOI [caption id="attachment_34410" align="alignright" width="347"] (Courtesy: STMicroelectronics)[/caption] This figure contrasts the structures of traditional bulk planar and SOI type transistors. The main difference is the inclusion of a buried oxide layer that isolates the channel of the transistor from the bulk silicon of the substrate. This results in a very thin, controllable channel structure, with much lower leakage currents being ‘lost’ into the device substrate than traditional alternatives. This in turn improves two key figures of merit for the device. First, standby power consumption is dramatically reduced. Second, the threshold voltage is much more predictable and controllable – yields are improved, and power/performance tradeoffs via voltage scaling are more easily enabled. The penalty is that FD-SOI transistors are generally not so fast. But one other feature of the technology – particularly important for mixed signal and analog designs – allows smart designers to mitigate this effect. Biasing the body structure at a different voltage to the source enables the designer to trade speed for power: a reverse bias increases the threshold voltage of the device, making it slower, but reducing leakage current; conversely, forward biasing reduces the threshold voltage, increasing the speed of the device, at the cost of power. Design migration Thalia has worked on a number of projects that utilize SOI technologies. A recent RF front end for Bluetooth Low Energy (BLE), for example, used exactly the techniques I have outlined above. We migrated an entire subsystem design, composed of around 30 blocks (including ADCs, PLLs, mixers, amplifiers and power controllers), to a 28nm Samsung FD-SOI process. [caption id="attachment_34412" align="alignright" width="451"] Click on this slide to see a YouTube video of the full Thalia presentation given at the Design Reuse FDSOI Virtual Event in March 2020.[/caption] The circuit was verified for compliance with design specifications. Design changes were implemented to ‘nudge’ the design to meet the requirements. And we made full use of the body biasing techniques I have already outlined. We used reverse body biasing to keep leakage as low as possible in parts of the circuit in which speed was not a factor; and, where speed was a key requirement, implemented forward gate biasing to increase performance. We’re expecting increasing numbers of customers to start moving their analog and mixed signal designs to SOI technologies in the coming months and years. The process is not without its challenges: but with an intimate knowledge of circuit design and optimization, and of the subtleties of the processes themselves, there are substantial advantages to be reaped. Technology analyzer – identifying the root cause when circuits fail A large part of the effort involved with migrating an IP from one technology to another is involved with qualifying the IP in the target technology; if a block doesn’t meet the requirements of the target technology, it won’t function. Identifying the cause of this – the technology characteristics that cause it – and then addressing them is key to a successful outcome. Whenever a key specification is not being met in the target technology, we have to determine which process technology or circuit characteristic is causing this. By using our automated technology analyser, we can take a design-centric approach to analyse and compare base and target technologies to see where the process technologies are similar and where they differ the most. The technology analyser considers both first and second order effects including FT, gm/id, Vdsats among others. Using this technology, we can identify which characteristics differ between the origin and target technologies. With traditional methods, identifying differences in characteristics would be time consuming, but our technology analyzer gives a clear and rapid identification of the issues, allowing us to fix any mis-matched topologies and achieve a functioning result in the target technology. The reality? IP reuse is not a dream or a myth Our platform comprises three elements – Technology, Methodology and Design Expertise. Using this trifecta, we have been able to deliver IPs in different technologies, nodes and with improved characteristics. The AMALIA technology consists of four elements: a technology analyzer, schematic porting, design enabler and layout migration. Tech analyzer: Using a design-centric approach, the platform addresses key first and second order effects of process technologies and extracts and compares characteristics between base and target technologies to provide the user with clear inputs on how similar the technologies are. Automated schematic porting: Taking the inputs from the analyzer and generates a circuit in the target technology. This circuit can then be verified for response and characteristics. Design enabler: Once the circuit design for the target technology is correct, the design enabler and our team of experienced designers can nudge the circuit back into specification. Layout migration: The final stage is focussed on putting together the base layout framework which is then expanding on by our experienced layout designers. Who we are?We are Thalia Design Automation. I founded Thalia in 2011, with the aim of improving the efficiency and process cost of analog circuit design and to rollout an analog IP reuse platform. We’ve worked with vendors, numerous foundries and different nodes and have design centres in Germany and India with our headquarters in the UK. We have successfully rolled out an analog IP reuse platform that combines smart technology, a smart methodology and our smart and experienced resources to streamline the IP reuse process. In doing all this, Thalia regularly provides customers with a time saving of around 50% compared to a traditional circuit redesign. And as I stated at the beginning of this article, achieving a faster time to market is key to maximizing revenues from any IP.

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).

SkyWater Licenses Key FDSOI Technology From MIT Lincoln Laboratory, Moves Up Availability Of Its 90 Nm Strategic Rad-Hard By Process Offering. (press release, 11 June 2020) Transferring MIT Lincoln Laboratory’s proven 90 nm FDSOI process into SkyWater’s Trusted fab will enable accelerated delivery on a previously announced up to $170 million Department of Defense (DOD)-funded program at SkyWater to enhance microelectronics capabilities for the Department and develop a new 90 nm Strategic Rad-Hard by Process manufacturing flow.Green Hills Software Adds Support for the Heterogeneous NXP i.MX 8 Application Processors in Airborne Safety- and Security-Critical Systems (GHS press release, 19 May 2020). Per the release, “NXP i.MX 8 applications processors have several features that are useful for avionics, airborne mission computers, and cockpit displays. With four Cortex-A53 cores and two Cortex-A72 cores, the i.MX 8QuadMax enables power consumption optimization by matching the performance requirements of each application task to the performance capacities of the different cores. The low soft-error rate of i.MX 8 processors results from a robust 28 nm FDSOI manufacturing process, which has inherently high immunity to alpha particle flux and enables high MTBF. Along with many of NXP's product families, the i.MX 8 processors have a minimum of 10-15 years of product supply longevity.”IBM Power9: Digging Into the Architecture and Materials - 14 May 2020. EETimes article by Jeongdong Choe ofTechInsights. This article summarizes TechInsights' analysis of the IBM 14HP HKMG FinFET-on-SOI eDRAM cell architecture, process, and design recently used in the IBM Power9 processor, which is fabbed by GlobalFoundries. It includes a list of new GF innovations, especially in the areas of architecture, process, materials and design.A major advance in high-performance computing - Leti Press Release, 7 May 2020. ​CEA-Leti unveiled a state-of-the-art demonstrator chip for high-performance computing applications at ISSCC 2020. The low-cost, energy-efficient processor is built on an innovative multi-core system that is both modular and expandable. The 96-core demonstrator is arranged into six FDSOI chiplets 3D integrated onto the active 65 nm silicon interposer.Silicon Photonics: A Marriage of Optical and Digital on GF’s RF Process - GF's Foundry Files blog, May 07, 2020. GF and Ayar Labs collaborated on ways to optimize GF’s 45 RF SOI process for the optical structures and other functions. That technology, developed for the mmWave market, was modified to include photonic function and is now being used to build prototypes. RF SOI CMOS is an “enabling thing, because it allows us to build both transistors and optical devices in the same planar layer. And the SOI process enables extremely fast transistors, faster than most of the advanced nodes built today."Webcast interview with Maud Vinet (in French),Quantum hardware program manager at CEA-Leti - 6 May 2020. Maud Vinet was also a key driver in the research and development of FD-SOI, and was recently awarded the French Legion of Honor award.Dolphin Design Unveiling innovative Energy Efficient Platforms, complete turnkey solutions for competitive SoC designs - Dolphin Design announcement, 4 May 2020. The company is releasing 4 platforms in the coming weeks: SPEED Power Management, SPEED Processing MCU, SPEED ML/AI Processing and/or SPEED Audio.Silicon Catalyst Collaborates with Arm to Accelerate Semiconductor Startups - Silicon Catalyst press release, 29 April 2020.Arm joins as Strategic Partner and as In-Kind Partner - the first company to join the incubator in both roles. The partnership provides startups with no-cost access to a broad range of Arm® IP, tools and support.Mixel’s MIPI D-PHY IP Integrated into the Lattice CrossLink-NX FPGA - World’s first low-power FPGA to support D-PHY v1.2 with 2.5Gbps/lane. Mixel press release, 28 April 2020. The new CrossLink-NX FPGAs are built on Samsung’s 28nm FD-SOI technology.GlobalFoundries Dresden Certified to Manufacture Secure Products - GF Press release, 27 April 2020. The official BSI certification extends the ability to cost effectively manufacture secure, connected products to GlobalFoundries’ 22FDX (FD-SOI) technology.GlobalFoundries Qualifies Synopsys' IC Validator for Signoff Verification on 22FDX Platform - Synopsys press release, 16 April 2020. With IC Validator physical verification, customers striving to take advantage of the low-power and performance benefits of GF's FD-SOI technology can now quickly verify that their designs meet signoff requirements for manufacturability compliance and maximum yield. Signoff design rule check (DRC), design for manufacturability (DFM), layout vs schematic (LVS) and metal fill runsets and tech files are available today from GF.FDSOI and Migration - YouTube video by Thalia Design Automation, posted 14 April 2020. Founder/CTO Sowmyan Rajagopalan talks about why analog IP reuse is a big problem for semiconductor companies, who Thalia is and how they can help. RF SOI can Save $Billions in 5G mmWave Network Costs with Efficient PAs - cover story in Microwave Journal, 13 April 2020. Republished here in its entirety with permission. By GlobalFoundries, Mobile Experts Mixcomm. Compact Model Developed at CEA-Leti for FD-SOI Technologies Designated as a Chip-Industry Standard - Leti press release, 2 April 2020. This Is of Paramount Importance for Large Chipmakers And Positions CEA-Leti Among the Few Compact-Model Developer Teams Able to Develop and Support a Standard ModelLattice Semiconductor Joins Silicon Catalyst In-Kind Partner Ecosystem to Foster Broader Use of FPGAs - Silicon Catalyst press release, 2 April 2020.eNVM Technology Choices for Automotive, Industrial and Multi-market Solutions - Video posted April 2020 by GlobalFoundries and SemiWiki. Perceive Corporation Launches to Deliver Data Center-Class Accuracy and Performance at Ultra-Low Power for Consumer Devices - Perceive press release, 31 March 2020. Introduces breakthrough Ergo™️ edge inference processor, delivering 4+ TOPS sustainedand 55 TOPS/W, capable of processing large neural networks in 20mW. The company has partnered with the leading specialty foundry, GLOBALFOUNDRIES, to manufacture the Ergo chip on their 22FDX® platform.Photonic Solutions From Synopsys Support Advancements in Nanoscale Optics - Synopsys press release, 30 March 2020. This latest Photonic Solutions Portfolio accelerates design of AR/VR Systems, Optical Communications, and PICs. Additional details were given by Synopsys during the SOI Consortium's Japan Symposium.Casio Tips Its Hat to Renesas for Its Battery-Less, Solar-Powered Smartwatch. In All About Circuits, March 19, 2020. The GBD-H1000, a new member of Casio's G-SHOCK line of smartwatches, functions on harvested energy. It also features a heart rate monitor and GPS functionality. Casio says the new watch needs no battery since it can be completely solar powered. Casio Computer Co. chose the Renesas RE01 controller as the primary controller. Renesas’ RE01 Group products are extremely low-power devices based on SOTB (what Renesas calls their flavor of FD-SOI) process technology. (Note that Casio has been using FD-SOI based chips in their G-Shock watches since 2005.)Bluetooth IP migration and leveraging FDSOI back gate biasing feature - Thalia Design Automation blog, 16 March 2020. By Founder/CTO Sowmyan Rajagopalan. QuickLogic's eFPGA Qualified on GLOBALFOUNDRIES 22FDX® Platform for IoT and Edge AI Applications - QuickLogic press release, 11 March 2020.D R FDSOI IP SoC Day - Virtual IP Event - hosted by Design Reuse, 13 March 2020. View videos get presentations by SOI Consortium members ST, Soitec, Analog Bits, Dolphin Design, Leti and Thalia, as well as other industry experts.Analog FD-SOI : Body biasing techniques enable designers to trade speed and power - Thalia Design Automation blog, 9 March 2020. By Founder/CTO Sowmyan Rajagopalan. Soitec's engineered substrates for 5G - Soitec (press release, 4 March 2020)Working with GF: Why MixComm Chose GF's Industry Leading 45RFSOI Solution - GlobalFoundries, YouTube video posted 18 March 2020. TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate - Silvaco, by Graham Bell, 2 March 2020. GlobalFoundries Delivers Industry’s First Production-ready eMRAM on 22FDX Platform for IoT and Automotive Applications - GlobalFoundries (press release, 27 February 2020)NXP Announces Availability of i.MX RT600 Crossover Family of Microcontrollers – NXP (press release 24 February 2020). The i.MX RT600 crossover microcontroller (MCU) family, an ideal solution for ultra-low power, secure edge applications including audio, voice and machine learning [...] manufactured [on Samsung’s] 28nm FD-SOI process, optimized for both active and leakage power.Presentation at ISSCC 2020 Shows Role FD-SOI Can Play in Embedding Qubit Arrays with Classic Electronics to Build Large-Scale Quantum Silicon Processors - Leti (press release, 18 February 2020)CEA-Leti Presents High-Performance Processor Breakthrough With Active Interposer and 3D Stacked Chiplets at ISSCC 2020 - from Design Re-use, 18 February 2020. The prototype's 96 computing cores are organized in six chiplets in 28nm FDSOI. Toshiba: Reduction of Loss by the Latest High-breakdown-voltage SOI Processes (website post, January 2020) and Toshiba Introduces Cutting-edge Generation SOI Process for RF Switches and Low-Noise Amplifier ICs for 5G Smartphones (Toshiba press release, 27 Feb. 2020) Mentor collaborates with Arm on unique eMRAM test solution using Samsung FDSOI technology (Mentor press release, 16 Dec. 2019) Lattice Announces New Low Power FPGA Platform - Lattice Nexus Platform on Samsung Foundry 28 nm FD-SOI Delivers Solution, Architecture and Circuit-Level Innovations to Enable Low Power Edge Applications - Lattice Semi press release, 10 December 2019. Clients Turn to the 22FDX® Platform for Next-Generation Automotive Radar - GlobalFoundries/Foundry Files Blog, Nov 07, 2019. By Mark Granger, VP Automotive Business Development.VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GLOBALFOUNDRIES 22FDX® for Edge AI and IoT Applications (press release, 24 October 2019) The IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs enabling VeriSilicon to provide a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after the silicon's been manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost.Samsung-MOSIS Collaboration (MOSIS PR, Oct. 2019). USC Viterbi’s Information Sciences Institute and foundry business at Samsung Electronics announced a collaboration to design and fabricate integrated circuits through USC ISI’s The MOSIS Service using multi-project-wafer runs. The collaboration combines MOSIS’s industry-leading integrated circuit manufacturing expertise, with Samsung’s high-performance CMOS and FD-SOI fabrication technologies. It positions ISI and Samsung’s advanced technologies to lead a new era of high-performance microelectronic design and manufacturing for the U.S. and global integrated circuits community.sureCore PowerMiser Low Power SRAM IP Now on Samsung 28nm FDS Process Technology (Press Release, Oct. 16, 2019)Samsung Introduces Advanced Automotive Foundry Solutions Tailored to EMEA Market at Samsung Foundry Forum 2019 Munich - Samsung (press release, 10 October 2019)NXP Launches the GHz Microcontroller Era (press release, 2 Oct. '19). The NXP i.MX RT1170 family is built using advanced 28nm FD-SOI technology for lower active and static power requirements. It integrates a GHz Arm Cortex-M7 and power-efficient Cortex-M4, breaks the gigahertz barrier and accelerates advanced Machine Learning applications at the edge.The Fourth Annual FD-SOI Forum: MosChip stands out as the future of silicon solutions (MosChip PR, 22 Sept. 2019). MosChip has multiple SOC designs ongoing in multiple markets (IOT and Vision Processing) where FD-SOI technology is being adopted.Making New Memories: 22nm eMRAM is Ready to Displace eFlash - By Martin Mason, August 29, 2019, in GlobalFoundries' Foundry Files.Samsung Electronics’ Leadership in Advanced Foundry Technology Showcased with Latest Silicon Innovations and Ecosystem Platform - Samsung (press release, 15 May 2019)Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process - Samsung (press release 6 March 2019)Soitec and Simgui Announce Enhanced Partnership and Increased Production Capacity of 200mm SOI Wafers in China, Securing Future Growth - Soitec (press release, 19 February 2019). Companies redefine their manufacturing and licensing relationship to better serve the growing global market for RF-SOI and Power-SOI productsRF SOI Shines for 5G Power Amps - by David Lammers for GlobalFoundries' Foundry Files, February 11, 2019.FD-SOI: How Body Bias Creates Unique Differentiation - by Manuel Sellier (Soitec), in GlobalFoundries' Foundry Files, October 17, 2018.

SOI News spoke with Philippe Berger, CEO of chip silicon IP design / power management specialist Dolphin Design. Here’s what he told us about the work they’re doing on FD-SOI.SOI News (SN): Dolphin Design has been offering IP solutions for bulk technologies since 1995. What is your specialty, and why are you expanding your offering to FD-SOI? Philippe Berger (PB): Low power is part of Dolphin’s DNA since its inception and we work hand-in-hand with our customers to offer IPs that enable design of Energy Efficient SoCs while allowing our customers to focus their design activity on their core competencies. Technology scaling is no longer the only answer for the next generation of Energy Efficient SoCs. FD-SOI is one of the attractive technologies to address the upcoming energy efficiency challenges of next SoC generations, be it for IoT or automotive among several other applications. FD-SOI offers the opportunity to deal with a complex SoC architecture, made of multiple power domains, including RF, including digital processing with AI, and sensor interfaces, all together with a complete power management on a single chip. [caption id="attachment_33090" align="alignright" width="175"] Philippe Berger, CEO, Dolphin Design.[/caption] This is a great opportunity for Dolphin Design. Adding the deep expertise of our engineers in this technology and our turnkey design platforms, we can really help companies targeting FD-SOI implement easily, quickly and safely an energy-efficient SoC. We have two complementary offerings for companies that want to leverage FD-SOI: A sensor-centric MCU subsystem as a configurable RTL design platform. This design platform, named Chameleon, allows achieving the best energy efficiency by turning the CPU off whenever possible and by eliminating latency and congestions on the memory bus. A power management design platform as a total solution to implement fast and safely a power management network that leverages low power techniques to meet the energy efficiency targets. This design platform, named Spider, combines a library of configurable power management IPs, including adaptive body biasing, with a scalable power controller enabling to control power and clock activity autonomously, even with the CPU off. We can intervene at a very early stage of our customers’ design cycles thanks to our system-level utilities rather than just IP bits and pieces. The figure below describes the components of our Spider power management design platform which is a key turnkey solution to leverage some unique capabilities of FD-SOI, such as the capability to operate at a very low voltage with a decent speed or the capability to support as high as 5V input voltage. ASN: What’s driving that business? PB: The emergence of new IoT and automotive markets is driving the business forcing IC design teams to pursue tough objectives: zero power consumption in off modes while maximizing the performance in active modes at minimal power consumptions. Unfortunately, scaling down to the next technology node makes it even harder to reduce power in off modes and is an expensive choice - too expensive - for many applications to achieve the energy efficiency targets in active modes. As a result, design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the stringent requirements of the new IoT markets. This is particularly tricky in advanced IoT where near-sensor processing must be efficiently combined with RF connectivity, together with advanced power management. In addition, designers must confront the complexity of supporting high input voltage for interfacing with 4.2V/4.4V Li-Ion batteries or 5V USB charging mode that rely on 1.8V IO transistors. The need for solutions that enable to select fast and to implement safely the power management network which allows a seamless system-level integration while meeting power consumption targets in each SoC power mode -- that drives our business. SN: What do you see as the biggest benefits – and challenges – for designers moving to FD-SOI? PB: Its biggest benefit is its high integration capability. One of its key challenge is the ”so-far” relatively more complex design methodology that is required to take advantage of all FD-SOI characteristics, namely for example the biasing of the bulk to either reduce leakage or improve energy efficiency depending on working mode and technology centering. And ultimately, assuming the FD-SOI design flow is no longer a point of discussion, we need to get all designers “Thinking FD-SOI”. By that I mean to be aware of the breadth of FD-SOI advantages, so they are using it at every possible opportunity: in RF, in switches, in A/D converters (ADC) – in everything! FD-SOI’s double gate lets you think about more than decreasing noise and energy consumption. There are many opportunities for many blocks – especially analog. [bctt tweet="We need to get all designers “Thinking FD-SOI” so they’re using it at every possible opportunity: in RF, switches, ADC – in everything! Body biasing is usually thought of in the digital context, but it is also very useful in analog. – DolphinDesign CEO" username="soiconsortium"] SN: What does Dolphin Design offer designers moving to FD-SOI? PB: In order to ease these tasks, we developed the turnkey Spider platform based on power management IPs and system-level utilities. It speeds-up the design of energy efficient power management systems to weeks instead of months. Spider obviously exists in FD-SOI technology. It enables chip-architects to explore many power architectures and to select the best one to match the targeted PPA. It bridges the complexity gaps of designing fast and safely a power controller that can deal with numerous power domains and several operation modes for each domain and that can operate even when the CPU is off. Then, it bridges the gap between standard RTL and GDS flow, as it is able to generate the UPF backbone of the SoC. It offers a standardized and predictable power management flow, securing first silicon success. As an example, one of our key customers doing a ULP MCU shared that they have been able to design a complete power controller in less than one week instead of a couple of months. SN: You announced design kits with Adaptive Body Bias (ABB) solutions for GlobalFoundries’ 22FDX technology at the end of 2019. What challenges is that solving? PB: In the race for higher energy efficiency, digital designers face the impact of process variations. Chip designers have added margins all along their design to ensure the future chip will work fine whatever the technology centering after fabrication. Performance or size tradeoffs are necessary to cope with extreme variation cases (the so-called “corners”). At low voltage, SoC designers often use compensation techniques to limit the impact on the SoC energy efficiency. Through the control of transistor threshold voltage in FD-SOI technology, body biasing acts as a fantastic and automated control method to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the PPA trade-off up to 10x at low voltage. We have been cooperating with GlobalFoundries over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop. From standard-cell library to sign-off verification, our customers will continue to use their usual standard flow. For IoT on GF 22FDX, the design kits are available for production. For automotive, it will be in the next months. SN: Looking to the future, will there be a need for more application-specific FD-SOI IP? Where are the growth opportunities? Which ones will you be working on? PB: We anticipate new needs along the time as new applications will emerge in FD-SOI. We have a roadmap to enrich the catalog of power management IPs for addressing each market vertical with the most complete offering. But where we see the biggest growth for us is the growing adoption of power management IPs even by companies that were used to make voltage regulators on their own. Power management is no longer an issue of designing some good voltage regulators, like LDOs. Fabless companies face the challenge of dealing with the growing complexity of SoC power management network. It absorbs a significant portion of their design “energy”, in logic and in analog domains. They need to customize voltage regulators for each SoC and to maintain their design to keep them competitive. They also face the challenge of complex and sensitive power controller design. Finding the right design expertise to make such complex SoCs is a challenge in itself and in many cases power management complexity is the cause of a design respin. With the emergence of solutions such as Spider, that streamline and secure the selection and the implementation of the power management network, fabless companies start to question whether their core competency is power management IP design or if they can focus their design resources where they are the best at. The addition of body biasing into this picture makes it even more obvious for fabless companies that relying on a solid IP partner is a strong option. For Dolphin Design another opportunity for growth will mainly come from our capability to expand our offering for complementary design platforms for various FD flavors. We will communicate a lot in the coming months on our design platforms. We are also looking for diversification to other SoC functionalities. Processing is definitely an area in which we are significantly investing (MCU sub-systems and their associated DSPs), but energy harvesting and RF could also be good candidates in the future. SN: Dolphin Design is a member of the SOI Consortium. What do you see as the advantages of membership? PB: The 2019 Silicon Valley SOI Symposium was my first participation in an SOI Consortium event. [Note: you can get his full presentation here.] My first impression was good! I was positively surprised by the wide diversity of material shown. But really the key advantage was the opportunity to meet with so many different companies, all involved, from near or from far, with an FD-SOI tape out. It really helped me understand what I needed to put my teams to work on next!

With the CAGR for switches in cell-phone RF front-end modules running at 9% for the next five years, new players want to get in on the action, and established players want to up the ante. The specialists at Incize help wafer suppliers, foundries and fabless companies maximize switch performance starting at the substrate level. CEO Mostafa Emam explains how.SOI News (SN): Can you tell us about the role Incize plays in the RF-SOI ecosystem? [caption id="attachment_32519" align="alignright" width="140"] Incize CEO Mostafa Emam. (Photo courtesy: Incize)[/caption] Mostafa Emam (ME): Our clients are wafer suppliers, foundries and fabless companies. The services we offer are testing and modeling of substrates, with the vision of what will happen in the value chain. Based on what the customer will do with the substrates, we do testing and modeling to improve the technology and tune their processes. Although the big players have teams devoted to this, we can add a layer of characterization that they have no expertise in. Some of our customers are foundries that have been using bulk silicon, but now see opportunities in RF-SOI. But they’re starting from scratch and we help them to adopt the technology. We help them understand the physics behind the technology so they can migrate from bulk to SOI. We help them develop test structures and evaluate their technology. Then we create models for both fully-depleted and partially-depleted SOI with PD-SOI 130 nm or 60 nm technology dominating the RF front-end module market. We believe RF is an art and you need to see the whole picture. SN: Can you tell us a bit about the history of Incize? ME: The RF-SOI story started in the 1990s. Then came trap-rich RF-SOI wafers from Jean-Pierre Raskin’s team at UC Louvain, industrialized by Soitec. Our lab at UC Louvain became known for our expertise in RF-SOI, and in 2011 we created Incize as a spin-off. [Editor's note: for more background, see this SOI Consortium article about the birth of trap-rich substrates and the company’s founding.] At first our characterization services were very diverse, but by 2014 we focused mostly on RF-SOI because of the big demand. In 2015 we started doing radiation hardness tests for space applications and a new business unit was created. In 2016 we started our modeling and PDK activity, followed the next year by work on GaN on Si. In 2018, we started offering full support to RF-SOI newcomers, who were starting from scratch, usually smaller players in the RF market. It takes about two years to fully train the engineers, support the technology enhancements, design test vehicles, measure them and finally do the modeling and PDK. So some of these players are now fully established in the RF-SOI market and have contracts in place with big customers. SN: In your presentations, you often say there is room for all. What do you mean by that? ME: There is a big market for RF-SOI in the coming years. It can offer the low-power, the low-cost and the high performance. RF-SOI is the only mature technology that combines all of this today. It successfully competes with traditional III-V technology. More foundries want to employ RF-SOI. We show to them that it’s not black magic – you just need to know how it works. [bctt tweet="There is a big market for RF-SOI in the coming years. More foundries want to employ #RFSOI. We show them that it’s not black magic – you just need to know how it works. - Incize CEO Mostafa Emam #5G #semiconductors" username="@soiconsortium"] On our side, we have the knowledge and the infrastructure. Our added value is that we can do advanced tests the customers can’t do. So the foundry says there’s opportunities in switches, we’ll do this and develop it all with optimization for specific Ron and Coff [the figure of merit for RF switches]. The foundry develops an RF switch and aiming at certain performance (RonCoff). We help our customers during this development phase. Once the performance target is reached we start developing a model and a PDK. There is enough demand for RF-SOI, as even entry-level cell phones have SOI chips. Some opt for a fast and low-cost solution. Many target “good enough”, although some target to compete against the big players – it’s a question of their business strategy. And this is where our added value comes in. SN: Can you provide some more insight into how you see the RF market? ME: The Front End Module (FEM) is a fast growing market, with increasing demand in terms of volume and performance. This includes antenna switches, LNAs, tuners, filters, etc. Historically, III-V materials have been used for their high performance and high power handling. However, RF-SOI has become the material of choice, and the biggest driver is integration of the RF switch and LNAs in one chip. It’s not easy to integrate the power amplifiers (PAs) on the same chip (still being on III-V substrates). But as it decreases footprint and cost, there are those who’ll do it. There is no viable competition for SOI – nothing will replace it in the short term. There are other technologies, but they are long term. It’s a stable market with high demand. SN: For those of us who are not RF experts, can you help us understand the technology? ME: The switch is sort of the traffic light of the FEM, receiving and transmitting. The simplest RF switch can be composed of only four transistors. Transistors leak power so you need to determine your Ron Coff performance. [Editor's note: Resistance on vs. Capacitance off, the RF switch figure of merit, is measured in femtoseconds and should be as low as possible. Psemi has a good video explaining it.] When the Coff capacitance is small, the switch is really off. When the On resistance Ron is small, it means low losses, and the switch is turned On. Ron and Coff is a compromise. And as there are many frequency bands and antennas, the FEM becomes very complex. Another issue is power handling, since the switch is the first stage behind the antenna. And finally, there is the question of switch linearity. Trap rich SOI wafers suppress harmonics so you have less distortion originating in the substrate. You have to model this – the designer needs to know. In addition to single tone harmonics you also get intermodulation, where, two or more high power signals at two different frequencies create distortion at other frequencies. The danger is that these parasitic signals can be so close that the filter can’t reject them and the useful signals get distorted. This was a killer for the switch created on the bulk substrate. Trap-rich RF-SOI fixed this. So now 100% of switches are on trap-rich SOI substrates. While it’s still a niche market, there is demand from customers for increasing the number of bands – that’s driving this market. SN: And what happens as we move to 5G? ME: There’s more and more pressure on the specs. It’s an art when anything changes. Moving from 3G to 4G required complete upgrade of the [foundry’s] models. With 4G, the specs are severe and the FEM must be built on trap-rich substrates. But 5G is not well defined, so the RF industry is taking their best shot. What is clear: the performance requirements get more challenging. Once the technology is understood, it can be implemented. But the foundries and the fabless need our help to do it fast and do it well. We create more value working together. SN: How do you see things evolving? ME: The number of foundries today doing switches on RF-SOI is increasing, and this will continue for the next few years. We saw this opportunity and invested in it. Our company is just ten people, and we are self-funded. We are swimming in business, but we have fun. And we’re getting recognition. Any company with CMOS in place could adopt RF-SOI. But it’s a different mindset. We help with the transition. ~ ~ ~Click here to read more feature articles in SOI News.

The Compact Model Coalition (CMC) has selected Leti’s L-UTSOI as a standard model for FD-SOI in the industry. The CMC is a working group composed of the major semiconductor companies and is part of the Silicon Integration Initiative (Si2). The Si2 Compact Model Coalition announcement covers the approval and financial support of L-UTSOI. L-UTSOI is derived from the Leti-UTSOI compact model, which has been implemented in circuit-simulation software and used in industrial process design-kits for several years. Thierry Poiroux, head of CEA-Leti’s Simulation and Compact Model Laboratory, said the selection of L-UTSOI as a Si2-CMC standard model ensures that it will be supported as long CMC industry members use it. “This is of paramount importance for large chip makers who will use this model in the future,” he continued. “With a standard model, they are assured that a team of model developers is able to take care of the model improvements and/or bug fixes they need during the whole lifetime of their technology. It also positions CEA-Leti among the few compact-model developer teams able to develop and support a standard model.” The role of compact models Once a new or enhanced chip is designed, it must be simulated prior to entering the expensive manufacturing phase. This proof-of-concept step relies on compact models that are expressed through a set of equations implemented in a form ensuring accuracy, robustness and numerical efficiency. Such compact models are approved and supported by the standard-setting arm of Si2, the CMC, which is an international working group focused on standardizing SPICE device models. “As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer requests for model support as we continue to add value to their membership.” Standard models are developed by the world’s leading SPICE-model experts. They are used by designers working at the most advanced fabless semiconductor companies, foundries, and IDMs. Implemented in the industry’s top versions of circuit-simulation software and duly qualified, standard models give designers the assurance that their integrated circuits will perform according to the design specifications. Industry proven L-UTSOI was extensively proven by the industry and its standardization will ensure long-term access and maintenance in EDA tools for FD-SOI designers. Available to coalition members now, it will soon be implemented in major versions of circuit-simulation software, and its source code will be released publicly in June 2021. “CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.” As noted in Leti’s announcement (read the whole thing here), the FD-SOI transistor’s back-gate allows tuning of the device in a low-leakage and low-power operating regime or higher-performance operating regime. This unique capability offered by FD-SOI enables the fabrication of smaller, faster and denser chips than standard bulk CMOS technology. FD-SOI devices are widely used in wearable electronics, automobiles and IoT. Leti pioneered FD-SOI in 1992. Here at ASN we’ve been covering their FD-SOI compact model work for over a decade.