semiconductor industry

How Cool is That - Northrop Grumman’s “World’s Fastest Microchip” won the 2024 “Coolest Thing Made in California” contest, organized by the California Manufacturers Technology Association (CMTA). Public votes were cast for 138 California-made products in four rounds, culminating in this microchip—boasting speeds up to 1 terahertz—being crowned the winner. Manufactured in Redondo Beach, CA, the chip is 1,000 times faster than smartphone processors and represents California’s cutting-edge manufacturing sector. The contest and award ceremony were celebrated during CMTA’s MakingCA Conference, honoring manufacturing’s $310 billion contribution to the state’s economy. Doing the Green Wave - NIST scientists have successfully created a compact, full-spectrum laser covering the green-yellow-orange wavelengths, long considered challenging to produce. Traditional semiconductor lasers struggled with green wavelengths due to material limitations, so NIST turned to nonlinear optics, producing different wavelengths by adjusting silicon nitride device geometry and laser input. This breakthrough enables more precise, pure wavelengths ideal for quantum computing, medical devices, and underwater communications. Their method combines pump laser tuning and device adjustments, achieving 150+ wavelengths, demonstrating a significant advancement in accessible, high-quality lasers.Source: NIST’s Compact Green Semiconductor Laser - IEEE SpectrumEnergy Hero - At the 2024 ITF World conference, AMD CEO Lisa Su spotlighted a new goal: a 100x boost in computing efficiency by 2027. As shrinking transistor sizes yield diminishing returns, materials innovation has become essential for boosting performance and efficiency. Applied Materials has responded with advanced materials engineering solutions, harnessing exotic elements and 3D chip designs to improve efficiency. For instance, Applied’s Integrated Materials Solution™ combines six process technologies to reduce chip wiring resistance by 25%, a critical advance as semiconductor nodes shrink to the atomic scale. These methods promise breakthroughs in power efficiency across AI, personal electronics, and more. Building Automation of the Future - Imagine a future where every device in newly built structures— from HVAC systems and appliances to light switches and sensors—is equipped with a microprocessor and linked through a reliable communication network. This could transform how buildings operate, yielding substantial benefits across various sectors. Chip manufacturers would see new growth opportunities, while builders could offer smarter, more efficient homes. Consumers would gain convenience and comfort, as buildings could dynamically adjust to personal preferences and real-time needs. For instance, rooms would automatically adapt their temperature as people move through them, making manual thermostat adjustments obsolete. This automated approach wouldn’t just create a more comfortable environment but would also optimize energy use, potentially lowering costs and benefiting the environment.Source: Building Automation of the Future - EE TimesDo you have a fun fact to share? We invite SEMI members to share fun facts about the industry or their company. We’ll consider your tidbits for inclusion in future blog articles and or posting on social media. Complete our survey form or email [email protected]. Learn more about the SEMI Foundation and its initiatives to promote industry awareness and help provide a path for those interested in rewarding careers in microelectronics. Follow the SEMI Foundation on LinkedIn, Instagram, X and Facebook. Margaret Kindling is Senior Program Manager for Diversity, Equity, and Inclusion at the SEMI Foundation. She promotes inclusion and belonging via Women in Semiconductors, Semiconductor PRIDE and SEMICON West Workforce Development Pavilion programming.

In the rapidly-evolving semiconductor industry, maintaining a competitive edge is crucial. To position Europe at the forefront of global semiconductor innovation, imec is leading the NanoIC pilot line initiative. Aligned with the European Chips Act, this initiative is a strategic move to bolster Europe's leadership in key markets like high performance computing, automotive, and healthcare.SEMI spoke with Srikanth Samavedam and Jo De Boeck from imec, Belgium, to learn more about the NanoIC pilot line and to better understand its goals, challenges, and prospects. From transitioning to gate-all-around (GAA) nanosheet devices, to developing advanced memory technologies and interconnects, this conversation highlights the cutting-edge advancements made possible through collaboration across the industry’s value chain.SEMI: How is the NanoIC pilot line working to revolutionize the semiconductor industry, and what are its main objectives?Samavedam: The NanoIC pilot line is a European initiative aimed at bridging the gap between R D and industrial innovation. The project is creating a beyond-2nm system-on-chip (SoC) pilot line, developing advanced logic, memory, and interconnect technologies. This effort supports the European Chips Act's vision for leadership and competitiveness in global semiconductor innovation, particularly in critical markets like high performance computing, communication, automotive, energy, and healthcare. However, advanced technologies come with more complexity, and addressing these complexity challenges requires more mature module baseline flows. By improving baseline flow repeatability and variability while reducing defectivity, we can accelerate the development of future technologies. The NanoIC pilot line is working to provide access to these advanced technologies and baselines to develop future compute systems. This will help ensure European competitiveness across the industry – from semiconductor materials, equipment and design to systems and applications.SEMI: Who are the core partners involved in this initiative?De Boeck: Key partners of the pilot line include CEA-Leti, Fraunhofer-Gesellschaft, VTT Technical Research Centre of Finland, Tyndall National Institute, and the Center for Surface Science and Nanotechnology of the University POLITEHNICA of Bucharest. This project is also supported by the Flemish government, other participating states, and the Chips Joint Undertaking of the EU Chips Act.These institutions and organizations bring a wealth of knowledge and resources, and imec compliments their efforts by providing access to its global partnerships with key industry leaders. The NanoIC pilot line is helping strengthen Europe’s global semiconductor industry leadership while aligning efforts with other regional Chips Acts. SEMI: Can you elaborate on the significance of transitioning from field-effect transistors (FinFETs) transistors to GAA nanosheet devices in CMOS technology?Samavedam: The transition from FinFETs to GAA nanosheet devices is a significant advancement in CMOS device technology. FinFETs have been the backbone of CMOS technology from the 22nm to the 3nm node. But starting at the 2nm node, nanosheet devices will need to be introduced. Nanosheet devices, including variants like Forksheet devices, are expected to drive scaling and performance through three generations – 2nm, A14, and A10. Complementary FET (CFET) architectures are also expected to be introduced around 2031 at the A7 node, which will represent another major inflection point in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities using high numerical aperture extreme ultraviolet (high NA EUV) lithography – all of which will be implemented on the NanoIC pilot line. FIGURE PROVIDED BY IMEC │ SCHEMATIC ILLUSTRATION OF A FUTURE COMPUTE SYSTEM. THE SYSTEM IS MADE OF LARGE MULTI-DIE ELECTRICAL-OPTICAL INTERPOSER PROVIDING ELECTRICAL AND OPTICAL INTERCONNECTS BETWEEN THE VARIOUS CHIPLETS (CPUS, GPUS, HBM). ALSO SHOWN ARE CONNECTIONS TO PACKAGE SUBSTRATE, AS WELL AS FIBER CONNECTORS AND AN INTEGRATED LASER SOURCE. CENTRAL PROCESSING UNIT (CPU); GRAPHICS PROCESSING UNIT (GPU); HIGH BANDWITH MEMORY (HBM); PROCESSING UNIT THAT CAN INCLUDE CPUS, GPUS, AND OTHER SPECIALIZED PROCESSORS (XPU); APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); ELECTRONIC INTEGRATED CIRCUIT (EIC); FF-LEVEL: FEMTOFARAD-LEVEL; FIELD-PROGRAMMABLE GATE ARRAY (FGPA); GAAS QD: GALLIUM ARSENIDE QUANTUM DOT; INTEGRATED SILICON PHOTONICS PLATFORM 300MM (ISIPP300); REDISTRIBUTION LAYER (RDL); SILICON PHOTONICS (SIPHO); THROUGH PACKAGE VIA (TPV). SEMI: What are the key innovations necessary for advancing memory technology?Samavedam: As SRAM scaling slows, the exploration of novel, dense embedded memory concepts will become imperative. Technologies like spin orbit torque magnetic RAM (SOT-MRAM) and 2-transistor 0-capacitor (2T0C) embedded DRAM using deposited semiconductors like indium gallium zinc oxide (IGZO) are promising. These innovations address memory capacity and bandwidth challenges from new workloads in compute systems. Additionally, developing a 3D memory platform to explore future memory options will be essential for improving SRAM and DRAM. These advancements will help meet the demands of new applications like machine learning, augmented and virtual reality, and autonomous vehicles.SEMI: How do advanced interconnect technologies contribute to the future of semiconductor design?Samavedam: Advanced interconnect technologies, like chip-to-chip lateral (2.5D or interposer technologies) and vertical interconnects (3D technologies), play a crucial role in addressing memory capacity and bandwidth challenges. These technologies enable the partitioning of SoC functions into separate dies, allowing for more efficient and scalable designs. Advances like pitch scaling of micro-bumps and copper (Cu) hybrid bonding are facilitating this fine-grained partitioning of SoC functions. Additionally, optical interconnects and 3D interconnect-enabled co-packaging provide high-bandwidth and low-power connectivity at wafer scale. The rise of chiplet architectures and standardization will also increase the demand for low-cost, tight-pitch interconnect technologies like Cu/polymer redistribution layers.SEMI: How do your collaborators benefit from the NanoIC pilot line? De Boeck: One of the biggest collaborator benefits is the pilot line’s commitment to knowledge sharing through R D access and training. We invite foundries, IDMs, materials suppliers, equipment suppliers, and system companies/OEMs to jointly develop the materials, process modules, and integration flows to accelerate the development of beyond-2nm SoC technology pillars.Design pathfinding and system exploration process design kits (PDKs) will be available for start-ups, small- and medium enterprises, universities, and design and system companies to aid in prototyping and testing their designs. The NanoIC pilot line will also offer comprehensive training programs, including virtual PDK training, bootcamps for faculty, and internships and expert courses for students. To learn more, experts and key partners of the NanoIC pilot line will be presenting from 14 -16:40 at SEMICON Europa on November 12. imec’s program, ITF Chip into the Future, will highlight advancements in digital technology, capacity building through the European Chips Act, and the role of the NanoIC pilot line in accelerating beyond-2nm innovation. The conversation will also address industry requirements for pilot lines, emerging initiatives boosting Europe’s innovation and competitiveness, and perspectives on advanced materials and semiconductor equipment. Srikanth Samavedam, Senior Vice President of Semiconductor Technologies at imec, oversees programs in logic, memory, photonics, and 3D integration. Previously, he was a senior director at GlobalFoundries, leading 14nm FinFET technology into production and developing 7nm CMOS. Starting his career at Motorola, he worked on strained silicon and other advanced materials. He holds a Ph.D. in materials science and engineering from MIT and a master's degree from Purdue University. Jo De Boeck, Executive Vice President and Chief Strategy Officer at imec, oversees the company’s strategic direction and serves on its executive board. He joined imec in 1991 after earning his Ph.D. from KU Leuven and has since held various leadership roles, including head of imec’s Smart Systems and Energy Technology business unit and CTO. De Boeck is also a part-time professor at KU Leuven. Maria Daniela Perez / Communications Manager, SEMI EuropePhone: +49 160 2562977Email: [email protected]

Use of machine learning and artificial intelligence (ML/AI) is on an exponential rise across fields1 including all aspects of the semiconductor industry. In the last decade, the use of ML/AI exploded in the areas of speech recognition, facial recognition, smart phone features, search engines and now large language models like ChatGPT, Bard AI, and CoPilot. The ML/AI growth has been enabled by massive data storage capacity and increased compute performance, leading to projections for the semiconductor industry to reach over $1 trillion in annual revenue by 2030, with about 50% of the industry’s growth related to GenAI2. Figure 1: McKinsey Company on GenAI driving semiconductor industry growthAs semiconductor manufacturing drives toward Industry 4.0, SEMI member companies have a vision of Industry 5.0, truly adaptive manufacturing, integrating human creativity with robotic precision enabled by AI. Along that path, automation and data exchange in every step of manufacturing is essential, with data acquisition, data integrity and relevance, and operational Digital Twins3 as defined steppingstones to the factory of the future.Based on growing member interest in ML/AI, in 2019, SEMI assembled technology communities that quickly engaged in AI discussions and proofs of concept, discovering gaps in the path to Industry 4.0. Successful demonstrations of the value of AI in chip manufacturing process development and factory efficiency, not to mention GenAI uses in society, hastened the pace to produce faster, more powerful chips to accommodate the computation and communication requirements. Recognizing the industry opportunity and the mounting role AI plays in the semiconductor supply chain, SEMI initiated several thought leadership efforts, namely the Smart Manufacturing Initiative, Smart Data-AI Initiative, and the Future of Computing think tank.Smart Manufacturing According to the SEMI World Fab Forecast, over 100 new and expanded wafer fabs will begin volume production by 2027. This massive capacity expansion will need to achieve the highest possible operational efficiency and performance. To this end, the Smart Manufacturing Initiative is a technology community with over 120 member companies collaborating pre-competitively to transform manufacturing. The SEMI Smart Manufacturing Global Executive Committee (GEC), outlined a roadmap vision for the cognitive factory of the future based-on technology, sustainability and future talent. The GEC has been working with members to realize that vision. Figure 2 describes this vision in terms of the technology progression needed and the approximate timeline for implementation by most manufacturers. The proliferation of this vision through Smart Manufacturing Forums at SEMICON events around the globe, newsletters and blogs has garnered enormous interest and participation in the initiative and is central to the mission of connecting and raising awareness within the ecosystem. Figure 2: AI-Driven Smart Factory (Point Systems to Autonomous Solutions) To move the needle on this vision, industry experts in the initiative successfully created and launched the Industry 4.0 Readiness Assessment Model (IRAM) to help assess technology deployment progress. IRAM adoption is steadily growing. Modern front-end and back-end lines produce an extraordinary amount of multi-modal data from a variety of sources, and this is key to success in unlocking the potential of AI in manufacturing environments. The initiative’s global working groups on Data Architectures and Smart Control Room among others are working towards a holistic Cognitive Factory framework uniting the vertical and horizontal flow of information. Integral to the Cognitive Factory are smart manufacturing standards, that will accelerate the vision outlined above, and without which local solutions are unlikely to scale.In 2023, the Smart Manufacturing Initiative brought together industry leaders in a unique Digital Twin workshop to align on the state of semiconductor development and usage. The key takeaways from this workshop are captured in a white paper that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months. that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months.The GEC has identified critical interrelationships in addition to the technology focus. At the intersection with sustainability, the initiative has formed a collaborative task force with the SEMI Semiconductor Climate Consortium (SCC) to develop a bottom-up technology roadmap that can be used as a blueprint for device makers to meet their proclaimed sustainability goals faster. The task force organized a technical session at SEMICON West 2024 and will be releasing a white paper in the near future. Similarly, the initiative is working with the SEMI Foundation to identify necessary future skills and to make training available through SEMI University. Smart Data AI – Applying AI to Semiconductor OperationsSEMI’s Smart Data-AI Initiative started by assembling a group of interested companies to explore the pivotal role AI could play in the industry and to address the criticality of data. All stakeholders agreed that a formidable challenge was (and still is) the integrity of that data and the security of sharing that data, which is considered IP to most. The optimal implementation of ML/AI techniques can only be gained by access to the comprehensive data set which is owned by numerous supply chain partners. Consequently, semiconductor R D, process and design have not yet realized the full benefit of Data-AI advances. In response, the initiative developed a framework to create value for members and support industry progress. Four pillars underpinning the strategy are:Educating stakeholdersBuilding communitiesExecuting proof-of-concept projectsDeveloping industry standardsTo explore the data challenges the subject matter experts highlighted, a collaborative proof-of-concept (POC) project was proposed in 2019 and accepted by the initiative's partners at Army Research Laboratories4 along with academic and industry partners. The project has completed two phases and is starting on its third phase under the expert guidance of an Industry Advisory Council (IAC) comprised of leaders in the Smart Data-AI community.The POC project, being conducted by principal investigators at Cornell University, demonstrated significant accomplishments from the first two phases, including:An AI model to predict device geometry by optimizing photolithography and plasma etching processesInitial demonstration of secure data-sharing techniques with software-hardware co-optimizationInnovative metrology ideas to train AI algorithms rapidlyStudents trained in cross-disciplinary skills to address the industry’s critical talent shortageFurthermore, the visionary objectives laid out at the initial stages of the POC proved to be synergistic with the strategic goals of the CHIPS Act5, which articulates the need for “collecting, aggregating, and sharing data sets that enable benchmarking and operational improvements, tools development, the creation of digital twins, and training AI models,” and that “the NSTC could develop a methodology for the voluntary sharing of data that protects the proprietary component and national security while enabling access to appropriate performance data.” Phase 3, to be completed by August 2025, will advance the state-of-the-art toward the following specific objectives:A framework to create and integrate Digital Twins of semiconductor R D and manufacturing process toolsAbility to explore processes and generate virtual devices swiftlyDefined interfaces to combine models for each process module or toolAccurate AI-based models for executing virtual process flows to build virtual devicesAdvanced solutions for secure data-sharing across the ecosystem – for example, federated learning where raw data is protected for each entity by building models locally, and only the outputs of the local models are used to build flow-level AI modelsFoundation for future industry standards for secure data-sharing and for interfaces in the virtual innovation environmentSEMI continues to build the collaborative community for Data-AI and strives to synergize with broader efforts such as the Digital Twin Manufacturing Institute, NSTC, and NAPMP in the U.S., and international standards development. Smart Data AI – System-level Innovation for AI – Future of ComputingThe cross-collaborative and synergistic objectives of Smart Manufacturing, the Smart Data-AI proof-of-concept work, and SEMI Standards merge to advance the state-of-the-art. The objective is to help members realize the full value of technology and innovation. In addition to improving semiconductor operations using AI, the efforts also strive to enable SEMI members to participate in, and ultimately profit from, market growth opportunities. Continued progress in AI is crucial both for the industry’s march towards $1 trillion in annual revenue, and for continuing to realize AI’s benefits to society.There are some hurdles to overcome in such a dynamic market. AI models, and the data they process, are outpacing hardware advances, posing a major roadblock for continued progress. As GenAI becomes more pervasive, the performance and power challenges continue to multiply, and require significant innovation in both hardware and software. While individual companies will develop competitive products in this domain, the entire ecosystem needs to evolve in a synergistic manner. As a global industry association, SEMI can play an important role in ensuring this. SEMI started a series of workshops and technology sessions to develop the community and identify opportunities and challenges. The first in this series was a joint workshop with McKinsey Co., held in October 2023, with a focus on innovations in “Domain-Specific Architectures.” Strategically, it brought together thought leaders from three diverse communities - start-ups, investors, and SEMI member companies across the supply chain. This was followed by an overcapacity audience at the Future of Computing session at SEMICON West 2024, where we explored AI-specific hardware with leaders in academia and industry. The Initiative’s next planned event in October 2024 is a focused workshop that is designed to be highly interactive and bring together visionaries and thought leaders from across the value chain – materials, devices, architectures, algorithms, and critical enabling technologies such as photonics, chiplets, advanced packaging, and 3D and heterogeneous integration. The overarching goal is to identify pre-competitive collaborative actions that would help the entire industry. The “Future of Computing” is the broad path to the industry’s future success. While AI systems are the current major wave on this path, future waves may be about heterogeneous integration of photonics and other components, and ultimately, quantum technologies joining the mainstream. SEMI continues to monitor these future trends, strengthen the ecosystem and enable innovation through pre-competitive collaboration, and accelerate implementation through standards.SEMI is fostering today’s collaborations while helping the industry navigate the future of electronics.Melissa Grupen-Shemansky is CTO at SEMI, Pushkar Apte is a Strategic Technology Advisor and Leader of the SEMI Smart Data-AI Initiative, and Mark da Silva is Senior Director of the SEMI Smart Manufacturing Initiative.Definitions and References:1https://arxiv.org/abs/2405.15828 Eamon Duede, William Dolan, Andre Bauer, Ian Foster, Karim Lakhani2McKinsey Company3Digital Twins for semiconductor manufacturing operations are dynamic, predictive, data-driven virtual models of a physical asset, process, or an entire factory, constantly synchronized with its real-world counterpart through real-time data streams and analytics4Research was sponsored by the Army Research Laboratory and was accomplished under Cooperative Agreement Number W911NF-19-2-0345. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Laboratory or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.5“A Vision and Strategy for The National Semiconductor Technology Center (NSTC)” published by the CHIPS R D Office.

Presentations at this year’s FLEX Conference illustrated the ongoing development of manufacturing tools and processes, materials, and test and reliability evaluation techniques for the growing field of hybrid electronics, which includes printed electronics and flexible hybrid electronics (FHE). Additionally, the field includes the use of additive manufacturing processes for electronics packaging and system assembly, from die attach to flexible printed circuits.Hosted by FlexTech, a SEMI Strategic Technology Community, the conference provides an opportunity for the device making supply chain to connect to R D, design and manufacturing innovations. A review of some of the key developments highlighted in FLEX presentations follows.Innovations in Flexible Printed CircuitsTokyo-based Elephantech has been focused on using advanced inkjet systems to produce flexible printed circuits. Using additive methods instead of subtractive to produce PCBs can enable reductions in carbon footprint, copper usage and water consumption. In order to achieve these benefits, Elephantech has developed processes for combining inkjet printing of metals and electroless plating. The company synthesizes copper nano particles, which it uses to formulate metal ink. It has implemented artificial intelligence to increase print accuracy, showing the capability of average drop position error of less than 2μm, and depositing 20μm droplets into 40μm grooves and wells (Fig 1).Fig. 1. Elephantech inkjet results showing ~2μm precision and prototypes with 50μm line widthExamples of Elephantech’s use of flexible printed circuit technology include a set of switches for a curved monitor and a pressure sensor with reduced footprint and component count. The company intends to directly compete with larger, rigid PCBs, and is developing a mass-production system with 57,840 nozzles that can process sheet sizes of 500 x 830 mm.Traditional processes for component attach on PCBs include mass reflow ovens, thermal compression bonding, and spot laser reflow. Laserssel has developed laser selective reflow, which promises warpage- and damage-free bonding at increased processing speeds. In addition to improving the productivity of rigid PCB production, the laser selective reflow could also enable in-line processing of roll-to-roll flexible printed circuits, replacing the use of trays for bonding to flexible printed circuits.Scrona, which spun out from ETH Zurich, has developed MEMS-based printheads to improve electrohydrodynamic (EHD) printing. By using an electric field to pull droplets out of the print nozzle, EHD can enable much higher print resolution (sub-micron, compared to tens of microns), and enable the use of higher viscosity inks than would be possible with traditional inkjet heads. While EHD has been under development for some time, its application has been limited by crosstalk, in which the electric fields of adjacent nozzles interact with each other, and the requirement for the nozzle to be within tens of microns from the substrate to enable high print accuracy.Scrona’s MEMS-based nozzles address these EHD problems by shielding adjacent nozzles to prevent crosstalk and by creating a uniform electric acceleration field, which increases print distance to the order of a millimeter. The company has used its system to print a variety of inks on different substrates, as well as conformal printing on 3D surfaces (Fig. 2).Fig. 2. Example of printing silver wires across a polished glass edge; line pitch 25μm, glass thickness 1mmThe Rochester Institute of Technology (RIT) has been developing an additive technique called liquid metal droplet jetting, which can deposit metal traces functionally equivalent to solid wires. The process uses metal wire as a feedstock, which is a fraction of the cost of nanoparticle metals. While tin, zinc, and aluminum have been used, silver and copper are still under development. The wire is melted in a micro-crucible, which feeds a nozzle; metal droplets are then jetted on demand in an argon environment to prevent oxidation (Fig. 3, l). Upon hitting the substrate, the drops solidify into metal traces equivalent to solid wire, quickly enough to avoid melting flexible films, and without curing or drying.Several methods have been explored to eject the jets from the nozzle, including magnetohydrodynamic using electromagnetic pulses, piezo-actuated pistons, and pneumatic jetting using compressed gas (Fig. 3, r). These techniques range from high-jetting-frequency and high-cost to simple and low-cost but low-frequency. Higher frequency enables overlap of droplets, increasing conductivity, and reduced processing time.Fig. 3. Concept of liquid metal droplet jetting (l); pneumatic droplet ejection approach (r)In addition to ongoing development of deposition tools and processes, the material set for additively printed electronics continues to expand. Iris Light Technologies, which spun out of Argonne National Lab and Northwestern University, is developing photonic inks for wafer-scale production of active devices including photodetectors, LEDs, and lasers. The semiconductor-based ink can be deposited via aerosol jet onto silicon wafers. Iris Light is focused on 2D semiconductors, specifically black phosphorous, which has a wider spectral coverage than graphene, is tunable in emission and absorption, and has high mobility.An example of the broadening of the additive manufacturing supply chain, Kraetonics has developed software for creating slices to be used in designing 3D-printed structures and elements. The software enables manufacturing 3D volumetric circuits with reduced size, weight, and power compared to 2D PCBs. The process involves 3D printing of hybrid mechanical-electrical assemblies such as circuits and antennas.Innovations in Test and ReliabilityAn area of active interest in the hybrid electronics community is that of test and reliability. American Semiconductor, a developer of flexible circuitry, and Bayflex, a value-added partner of Japanese equipment company Yuasa, are conducting a project on dynamic harsh environmental FHE reliability testing. The goal is to identify root causes of FHE material and system failures.The companies are developing extended temperature and humidity tests to determine FHE system lifetimes and identify causes of failures from physically deforming FHE materials and systems in harsh temperature and humidity environments. Materials under consideration for testing include:Copper on polyimide substrate with a small outline package IC and surface-mounted componentsNobleflexTM, a multilayer substrate with gold on polyimide in development for medical devicesSilver on PET substrate, with small outline package IC.The team is soliciting other test devices and is planning to coordinate with ongoing development of FHE test standards coordinated by SEMI.Henkel reported on an investigation of accelerated temperature cycling test methods, in which the company applied different combinations of temperature range, stress, and frequency of mechanical force in an effort to reduce cycle time for testing component attach reliability. The study was able to achieve similar failure modes using an accelerated test method in the case of a bonding position shift in which cracking of the die attach film was the failure mode (Fig. 4, approach 4). The study found the greatest acceleration in the case of reduced thermal shock cycles (Fig. 4, approach 1).Fig. 4. Approaches evaluated for accelerated testing of component attach.Engineering consulting firm Exponent presented the results of a study on mechanical testing for characterizing fatigue performance of flexible electronics, conducted with continuous monitoring of fatigue for 6-pin flexible flat cables from seven different vendors. Exponent found that continuous monitoring during bending fatigue testing provided greater resolution in test results including detection of intermittent failure in each sample. The study also found that strain amplitude was a critical factor for determining fatigue life, and that flat flexible cables with larger pitches showed improved fatigue performance.About SEMI FlexTechFlexTech, a SEMI Strategic Technology Community, promotes the growth, profitability and success of the flexible hybrid electronics industry by developing educational forums, directing research, and promoting technology innovation.SEMI FlexTech members benefit from speaking and business networking opportunities, introductions to key industry players, research reports, technical funding, access to end users and industry advocacy at FLEX Conferences.Gity Samadi is Director of SEMI research and development funding programs and SEMI FlexTech and SEMI Nano-Bio Materials Consortium (NBMC). Paul Semenza is an advisor to SEMI on special projects. He was previously with NextFlex, the Flexible Hybrid Electronics Manufacturing Innovation Institute.

Athinia’s recent selection as a strategic advisor for SEMI Supply Chain Management (SCM) initiative will improve how data is shared and analyzed across the ecosystem with Athinia®’s platform as the foundation for secure data collaboration and continuous sharing of data between many companies.

I am passionate about supporting organizations committed to creating safe workplace communities for LGBTQ+ employees. One example is Out in Science, Technology, Engineering, and Mathematics (oSTEM), a nonprofit that is the largest chapter-based organization.

Women in Semiconductors (WiS) was initiated in 2016 to address the unique challenges faced by women in the industry and discuss how women can be supported better in their desire to move into leadership positions. The annual program is now managed by the SEMI Foundation.

SEMI spoke with Prof. Owen J. Guy, Head of Chemistry and Education Lead at the Centre for Integrative Semiconductor Materials at Swansea University, about the challenge of onboarding talent within the microelectronics industry and the importance of the SEMI Talent Forum ahead of the May 30 event.

This episode of Resilinc’s Rethinking Resilience supply chain podcast features industry insights from Bettina Weiss, Vice President of Business Development and Product Management at SEMI, George Thompson, Director of the Semiconductor Supply Chain Practice at Genpact.

Semiconductor Climate Consortium working groups provided updates on their work to reduce greenhouse gas emissions across the global chip value chain at the first SCC general meeting of 2024. In addition, Alaina Passavant of the Carbon Disclosure Project presented on emission reporting trends.