SEMICON Europa

SEMI spoke with Antoine Amade, Regional Senior Director EMEA at Entegris, about the challenges set by the car industry, and the concept of “zero defect” and the need for a collaborative approach ahead of his presentation at the Strategic Materials Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here.SEMI: The automotive industry is setting new challenges. This is very exciting source of growth for the global supply chain, but what are in your opinion the automotive requirements of the future?Amade: By 2030, 50% of the car cost will be electronics related. With the autonomous cars, there will be no tolerance for any type of chip defects because it will have a direct impact on human safety. With that in mind, higher reliability, increased efficiency and control across the supply chain will be the main requirements of the automotive industry.SEMI: Is the New Collaborative Approach the solution to overcome the challenges related to the automotive requirements of the future such as defects and contamination? What can you tell us about this approach?Amade: The automotive industry presents a great challenge to all of us, reaching the ppb level in terms of defectivity. In other words, this zero defects objective requires a collective awareness and understanding: Within an aging and more complex manufacturing environment, we all need to challenge the status quo and go for a new collaborative approach.SEMI: What does Entegris propose?Amade: We trust that contamination control has a major role to play to reach the zero defects. We are now in the 3rd generation of contamination control. After the focus on the cleanroom environment and equipment, materials are now at the center of the attention. With Entegris offering the broadest portfolio in terms of advanced chemicals, filtration and purification, and materials handling, we’re uniquely positioned to address precision, purity, integrity, and safety challenges.SEMI: How could this support fab managers in their daily challenges and mid-term future objectives?Amade: The new collaborative approach is a journey. It is a consultative process to provide a fresh set of eyes and expertise on the key areas of concerns in the fabs. It is a multidisciplinary approach with zero defectivity as the main goal. It is focused on base line improvement, better process control, more uniformity and prevention of excursions.SEMI: What do you expect from SEMICON Europa Strategic Materials Conference?Amade: It's the perfect platform to deliver our message in front of the whole ecosystem. It obviously concerns the fabs, but also material suppliers, and even carmakers. We expect this new view of collaboration will create an engagement from all parties. It is not a coincidence that this is called New Collaborative Approach. Antoine Amade joined Entegris in 1995 as an application engineer in its semiconductor business. In his current role as EMEA Sr. Regional Director, Mr. Amade manages a sales, customer service and marketing team responsible for growing the semiconductor business in Europe and Middle East.Mr. Amade held leadership positions at Entegris including gas microcontamination market management, strategical account management and regional sales management. He has a degree in Chemical Engineering from ENS Chimie Lille and is a member of Semi Electronic Materials Group for Europe. Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI spoke with Udo Gómez, senior vice president at Robert Bosch GmbH, about MEMS technology requirements relative to standard IC design and manufacturing. Gómez highlighted solutions to challenges of MEMS technology development and manufacturing ahead of his presentation at the 22nd Fab Management Forum at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here.SEMI: Regarding standard processes for MEMS, the situation used to be known as the MEMS law: "one product, one process." Today, the variety of MEMS sensors and their application requirements have drastically increased. What is the status of process standardization today?Gómez: Today, standardization in MEMS is certainly not as advanced as it is for conventional semiconductor processes and model environments. However, MEMS technology has developed very much in recent years. The understanding of the numerous interactions between mechanical, chemical and electrical parameters has grown enormously. Improved process tolerances and optimized simulation tools already allow the design of standard components and their manufacture using largely standardized processes and systems.This also enables standardized MEMS process platforms in foundries for fabless suppliers, since adapting process parameters to standard designs no longer means maximum effort. But the situation changes significantly if you want to implement more powerful MEMS components for demanding applications. In this case, much effort is still required in technology development to bring new and innovative designs to mass production readiness.SEMI: How does this situation interfere with the need for a fast, market-driven product development and production ramp-up?Gómez: The constant advancement of (MEMS) technology to new limits requires enormous efforts and time. Thus, fast product cycles in consumer electronics (CE) pose particular challenges. Close interaction between product and technology development is a key success factor here, as well as a deep understanding of the cause-effect relationships. This is the only way to identify and minimize process risks at an early stage.However, the steep product ramp-ups usually required in CE also offer advantages, since learning curves are run through at much shorter time-intervals than, for example, the comparatively slow ramp-ups in the automotive industry. In this way, automotive products benefit directly from the results of CE components. Conversely, CE products benefit from the higher requirements in the automotive sector, whose technologies can be developed and tested on longer time scales.SEMI: What are the critical and different design and manufacturing requirements for MEMS products versus standard IC products, which typically run in highly standardized processes?Gómez: A very special feature of MEMS devices is their multi-physics character – mechanical, electrical, magnetic, fluidic, and even chemical and/or optical effects may play a role. This is very different from standard semiconductors. Depending on the type of sensor or actuator, dedicated and often quite sophisticated models need to be developed to ensure proper function of the device – and not least to ensure full functionality after misuse. For example, shocks or drop events are usually not relevant for standard ICs but they may be extremely relevant for MEMS devices with their fragile mechanical structures.Similarly, the influence of packaging effects like bending or thermomechanical stress may be much more significant in MEMS devices than for standard semiconductors. And last but not least, a physical/magnetic/chemical/optical … stimulus usually needs to be applied when testing MEMS devices. All of this adds complexity to the manufacturing flow and requires dedicated know-how both during the engineering stage and in mass production.SEMI: BOSCH is working to extend the process platform to include complex 3D structures. What are the advantages and benefits of using 3D structures compared to standard 2D structures? Are there 3D structured products already in mass production?Gómez: We have recently extended our well-established surface micromachining process for MEMS inertial sensors (which basically uses one functional silicon layer for the movable MEMS device) to an advanced process using a second functional micromechanical layer. This opens up a large variety of design options and allows the realization of entirely new sensor topologies. For example, our most recent z-axis accelerometers for automotive and CE applications have 3D-like structures for the movable mass.This has several advantages: Firstly, the sensors can be further miniaturized as they now have fixed electrodes for capacitive readout above and below the movable mass, i.e. a larger capacitance per area. Secondly, due to their improved symmetry, these sensors have greatly improved immunity against several parasitic effects, e.g. mechanical stress from soldering or bending on a PCB. Overall, this technology enables us to offer better performance at still very competitive product size and cost. Both automotive and CE sensors are in high volume production for different applications and customers. SEMI: What do you expect from SEMICON Europa 2018 and why do you recommend attending the Fab Management Forum?Gómez: After our very positive impressions of SEMICON Europa 2017, we are convinced that SEMICON 2018 will again meet with widespread interest within the semiconductor industry. SEMICON is an excellent opportunity for us to meet our customers and partners. The Fab Management Forum, which ideally takes place parallel to SEMICON, is a highly valuable addition for us to exchange ideas with leading industry partners and to gain new insights into current trends and technical progress. Within that context, the Forum will make a valuable contribution toward strengthening the European position in semiconductor and MEMS manufacturing. As senior vice president of Robert Bosch GmbH, Dr. Gómez heads Sensor Engineering at Bosch Automotive Electronics (AE/NE-SE) in Reutlingen, Germany, the world’s largest MEMS supplier serving the Automotive, Consumer Electronics and IoT industry. Dr. Gómez started his career at Robert Bosch GmbH in 1999 at Corporate Sector Research and Advanced Engineering (MEMS technology) after completing his doctorate in physics. Before joining Bosch Automotive Electronics in April 2018, he worked in various management positions at Bosch and also held the position of Chief Expert for MEMS sensor technology. From 2013 to March 2018, he was Chief Technical Officer of Bosch Sensortec GmbH - a fully-owned subsidiary of Robert Bosch GmbH, responsible for research and development of micro-electro-mechanical sensors (MEMS) for consumer electronics, smartphones, security systems, industrial technology and logistics.Dr. Gómez has served as Deputy Chairman of the Board of VDE/VDI-Society Microelectronics, Microsystems and Precision Engineering (GMM) since 2014 has been a member of the GSA (Global Semiconductor Alliance) EMEA Leadership Council since 2015.Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI met with Heinz Martin Esser, managing director at Fabmatics GmbH, to discuss how existing 200mm semiconductor fabs can master the challenges of a 24x7 production under highest cost and quality pressure by implementing intralogistics automation solutions. The two spoke ahead to his presentation at the Fab Management Forum at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Looking at the latest production capacity data for 2018 – it is a 200mm fab boom. Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment. Do you think this trend will continue the next years or is it only a short term run on 200mm fabs?Esser: We at Fabmatics believe in a long-term trend. The emergence of the Internet of Things and growing digitalization in all areas of life will continue to increase demand for integrated circuits (ASICs), analog ICs, high-performance components and micro-mechanical sensors (MEMS) in the coming years. Many of these semiconductor elements should be produced in 200 mm fabs.SEMI: How does Fab automation contribute to increase capacity of existing, mature 200mm fabs?Esser: We are convinced that fab automation is one of the greatest potentials for older 200mm factories to effectively master increased demand, increasing efficiency, quality assurance and flexibility at the same time. In particular, material flow automation, which is often the missing link between existing equipment in different production areas, can help increase productivity in an elementary way.If you analyze how long valuable tools typically wait for loading and unloading, you can see a direct effect of the intralogistics automation system, which leads to a significantly higher utilization of process equipment by making the material flow independent from human performance. Additional side effects such as reduced cycle time, stable fab flow factor or flattened WIP shafts further increase the contribution of material flow automation to get the most out of existing mature factories. Older does not mean obsolete.SEMI: What are the biggest challenges for a successful implementation?Esser: There is no single challenge when you automate an existing mature fab. Instead, you face a whole variety of challenges you have to tackle, ranging from historically grown non-aligned fab layouts over non-linear material flows and older non-standardized equipment to “automation unfriendly” fab environment. Also you should not underestimate the efforts to overcome the practice manual fab operation people in the cleanroom are so familiar with for many years. Before doing automation you have to think automation, i.e. you have to question all processes to make them ready for automation.SEMI: What are the key drivers to automate a mature fab today: costs, process stability, quality or a combination of them?Esser: This question should be better asked to our customers, but we believe it is a mix of many impacts. Most likely everybody sees the cost reduction at first, but we get more aware of process and performance stability as well as quality requirements – and here our customers’ play the most important role – become more and more focused.SEMI: What do you expect from SEMICON Europa 2018 and why do you recommend attending the Fab Management Forum?Esser: This year SEMICON Europa will co-locate with electronica. So it`s going to be the greatest trade fair for electronics manufacturing in Europe. We will meet innovators and decision-makers across the whole electronics supply chain. The Fab Management Forum addresses a highly topical question that concerns all semiconductor manufacturers not only in Europe - how to handle complexity and enable the necessary flexibility to cope with customers' needs. High-ranking speakers will give an insight into the latest technologies and best practices. I am looking forward to the lively exchange with the participants and taking away new impulses for our business. Heinz Martin Esser is managing director at Fabmatics GmbH, responsible for sales and marketing, customer service and administration. He studied supply engineering at the University of Applied Sciences in Cologne and later earned a university degree in business administration. Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI spoke with Balaji Nandhivaram Muthuraman, Package and Material Simulation engineer at Dialog Semiconductor, about the state of reliability testing for wafer-level chip scale packages ahead of his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Since the beginning of package development reliability testing has played a key role in Wafer Level Chips Scale package (WLCSP) investigation. Lately, the role of simulation and predictive reliability significantly contributed in reducing package development time. To what extend can we predict potential failures for WLCSP packages in an early design phase by simulation?Muthuraman: Reliability testing is essential and crucial for the electronic packages. It is during the package development phase that several design iterations need to be considered and, in some cases, many feasibility studies for the package are executed. This means we require significant reliability test measurements, which could influence product-development time. For example, Temperature Cycling on Board (TCoB) reliability testing would take approximately 65-75 days for testing the package reliability subjected to 1500 temperature cycles. Each cycle involves exposing the device at hot and cold temperatures with a specified temperature profile. Executing such Board Level Reliability (BLR) tests for all feasible package designs is a tedious process that could lead to an increase in package development time. This is the stage where numerical simulation methodology helps us to foresee potential failures in Board Level Reliability. Predicting delamination or cracking of passivation/metal interface layers based on the WLCSP design layout and estimating the characteristic life of smart device subjected to temperature load are some classic examples of predicting WLCSP package behavior in an early design phase by simulation methodology.SEMI: We can definitely say that predictions occurring during the early stage are key to success. But how exactly can numerical simulation help estimating?Muthuraman: From a thermal reliability point of view, determination of the optimum material combination – bill of materials for device – is used to predict whether a heat sink is required for the device to meet thermal performance. This is not all. At an early design stage, the simulation methodology can be used to estimate device performance under varying thermomechanical loads. Numerical simulation at early package development phase helps the researchers by predicting the possible temperature contour field and stress contour field of the smart device under a given loading condition. The estimation accuracy of potential issues through numerical simulation depends on the material models implemented and consideration of realistic load condition under which the package operate in real life situation. For example, engineering judgements can be made using numerical simulation of Solder Joint Reliability (SJR) analysis to decide whether an Underfill material is required between the Package and the Printed Circuit Board (PCB).SEMI: Are all conditions tested during the reliability investigations specific to fit a certain type of applications or do these vary?Muthuraman: Reliability investigations are based on the end application of the electronic devices. For example, handheld device applications will be exposed to a reliability condition up to a maximum of +85oC, whereas smart devices designed for an automotive application would be tested with a typical temperature of +125 oC or up to +150 oC. In some cases, the testing conditions are customized based on specific customer requirements. Moreover, reliability conditions can also be customized to study some specific failure mechanism. SEMI: Can you describe for which one?Muthuraman: Thermal cycling profile is based on device application and/or specific requirement from our customer. For example, handheld devices use a typical temperature range of +85°C to -40°C with 20°C/min ramp time and 20 minutes of dwell time. There is possibility of adjusting the ramp and dwell time of the Temperature Cycling qualification test, provided such accelerated test does not lead to other failure modes.SEMI: What failure mechanism was the subject of the study in this specific case?Muthuraman: Electronic package reliability behavior without and with underfilled devices is explained in this study with the help of temperature cycling on board (TCoB) measurements and validated with numerical simulation. In the paper to be presented at SEMICON Europa, failure occurring at the interface of the solder and Under-Bump Metallization (UBM) structure is discussed. Behavior of such failure mechanism is illustrated with different WLCSP package sizes subjected to varying thermal load condition. One of the key aspects of the subject is the board-level reliability (BLR) measurement and simulation validation showing how the failure mode could be shifted from solder joint to the metal interface layers between UBM and interconnection to Silicon Chip, depending on the WLCSP design layout. The reasons for such shifts in Failure phenomenon are explained and necessary design optimization is suggested for improvement. Another key aspect of this study is determination of Fatigue Life Model for WLCSP family using the SACQ solder. SEMI: Are you currently working and experimenting on something particularly exciting?Muthuraman: Recently, we concluded our engineering analysis of thermomechanical reliability of Large Wafer Level Chip Scale packages. In September 2018, I presented this research work in an International Conference held in Dresden, Germany. Dialog Semiconductor GmbH was awarded the “Best Paper Presentation for the year 2018” for this work. This success is attributed to the entire team of Package and Material simulation experts at Dialog Semiconductor GmbH lead by Mr. Baltazar Canete and IC Package-Design Simulation group managed by Mr. Rajesh Aiyandra. We have started our investigation on the influence of Board Level Reliability of WLCSPs due to varying metal concentration of inter-metallic layer. We, at Dialog, are also working on possibility of thinner WLCSP. All these activities would include extensive Temperature Cycling on Board (TCoB) measurements, Statistical Analysis of measurement Data and would then be validated by Numerical Simulation. SEMI: What are your expectations for the future and why would you recommend attending SEMICON Europa Advance Packaging Conference?Muthuraman: SEMICON Europa is an important platform for Dialog Semiconductor GmbH to showcase the latest developments in the semiconductor industry. It is an opportunity to meet other industry experts, partners, and customers, and exchange various innovative ideas and to get new insights. Many semiconductor companies are based around the Munich area as well world-class universities. We are particularly interested in innovation, workforce and talent development themes. SEMICON Europa gives us a platform for greater interaction with the academicians and research scientists. This way, we bridge the gap between industry and University researches, thereby moving forward in innovative technologies. We, as Dialog Semiconductor GmbH, have also a development center near Munich (Germering). Our expectations for the future are very positive and vibrant. We are always ready to take up the industry challenges and demands and provide the best-in-class solutions to our product users. Dialog Semiconductor GmbH is certainly poised for higher growth in coming years. Balaji Nandhivaram Muthuraman BioBalaji Nandhivaram Muthuraman is a Packaging and Material Simulation engineer at Dialog Semiconductor GmbH, Germany. He has authored/co-authored conference publications including in the area of molecular dynamics simulation on assembly of carbon nanostructures; Analysis of thermoset material used in smart devices and reliability of wafer level packages. Recently, he has been awarded with the “Best Paper Presentation for year 2018” in the area of Board Level Reliability of Wafer Level Chip Scale Packages, in a recently held international semiconductor conference. His current areas of working interest include reliability investigation of electronic packages and developing fatigue models for reliability assessment of Dialogs products. He obtained his Bachelor’s degree in Aeronautical Engineering from Anna University, India and Master’s degree in Computational Mechanics of Materials and Structures from University of Stuttgart, Germany. Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.