advanced packaging

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

Presentations at this year’s FLEX Conference illustrated the ongoing development of manufacturing tools and processes, materials, and test and reliability evaluation techniques for the growing field of hybrid electronics, which includes printed electronics and flexible hybrid electronics (FHE). Additionally, the field includes the use of additive manufacturing processes for electronics packaging and system assembly, from die attach to flexible printed circuits.Hosted by FlexTech, a SEMI Strategic Technology Community, the conference provides an opportunity for the device making supply chain to connect to R D, design and manufacturing innovations. A review of some of the key developments highlighted in FLEX presentations follows.Innovations in Flexible Printed CircuitsTokyo-based Elephantech has been focused on using advanced inkjet systems to produce flexible printed circuits. Using additive methods instead of subtractive to produce PCBs can enable reductions in carbon footprint, copper usage and water consumption. In order to achieve these benefits, Elephantech has developed processes for combining inkjet printing of metals and electroless plating. The company synthesizes copper nano particles, which it uses to formulate metal ink. It has implemented artificial intelligence to increase print accuracy, showing the capability of average drop position error of less than 2μm, and depositing 20μm droplets into 40μm grooves and wells (Fig 1).Fig. 1. Elephantech inkjet results showing ~2μm precision and prototypes with 50μm line widthExamples of Elephantech’s use of flexible printed circuit technology include a set of switches for a curved monitor and a pressure sensor with reduced footprint and component count. The company intends to directly compete with larger, rigid PCBs, and is developing a mass-production system with 57,840 nozzles that can process sheet sizes of 500 x 830 mm.Traditional processes for component attach on PCBs include mass reflow ovens, thermal compression bonding, and spot laser reflow. Laserssel has developed laser selective reflow, which promises warpage- and damage-free bonding at increased processing speeds. In addition to improving the productivity of rigid PCB production, the laser selective reflow could also enable in-line processing of roll-to-roll flexible printed circuits, replacing the use of trays for bonding to flexible printed circuits.Scrona, which spun out from ETH Zurich, has developed MEMS-based printheads to improve electrohydrodynamic (EHD) printing. By using an electric field to pull droplets out of the print nozzle, EHD can enable much higher print resolution (sub-micron, compared to tens of microns), and enable the use of higher viscosity inks than would be possible with traditional inkjet heads. While EHD has been under development for some time, its application has been limited by crosstalk, in which the electric fields of adjacent nozzles interact with each other, and the requirement for the nozzle to be within tens of microns from the substrate to enable high print accuracy.Scrona’s MEMS-based nozzles address these EHD problems by shielding adjacent nozzles to prevent crosstalk and by creating a uniform electric acceleration field, which increases print distance to the order of a millimeter. The company has used its system to print a variety of inks on different substrates, as well as conformal printing on 3D surfaces (Fig. 2).Fig. 2. Example of printing silver wires across a polished glass edge; line pitch 25μm, glass thickness 1mmThe Rochester Institute of Technology (RIT) has been developing an additive technique called liquid metal droplet jetting, which can deposit metal traces functionally equivalent to solid wires. The process uses metal wire as a feedstock, which is a fraction of the cost of nanoparticle metals. While tin, zinc, and aluminum have been used, silver and copper are still under development. The wire is melted in a micro-crucible, which feeds a nozzle; metal droplets are then jetted on demand in an argon environment to prevent oxidation (Fig. 3, l). Upon hitting the substrate, the drops solidify into metal traces equivalent to solid wire, quickly enough to avoid melting flexible films, and without curing or drying.Several methods have been explored to eject the jets from the nozzle, including magnetohydrodynamic using electromagnetic pulses, piezo-actuated pistons, and pneumatic jetting using compressed gas (Fig. 3, r). These techniques range from high-jetting-frequency and high-cost to simple and low-cost but low-frequency. Higher frequency enables overlap of droplets, increasing conductivity, and reduced processing time.Fig. 3. Concept of liquid metal droplet jetting (l); pneumatic droplet ejection approach (r)In addition to ongoing development of deposition tools and processes, the material set for additively printed electronics continues to expand. Iris Light Technologies, which spun out of Argonne National Lab and Northwestern University, is developing photonic inks for wafer-scale production of active devices including photodetectors, LEDs, and lasers. The semiconductor-based ink can be deposited via aerosol jet onto silicon wafers. Iris Light is focused on 2D semiconductors, specifically black phosphorous, which has a wider spectral coverage than graphene, is tunable in emission and absorption, and has high mobility.An example of the broadening of the additive manufacturing supply chain, Kraetonics has developed software for creating slices to be used in designing 3D-printed structures and elements. The software enables manufacturing 3D volumetric circuits with reduced size, weight, and power compared to 2D PCBs. The process involves 3D printing of hybrid mechanical-electrical assemblies such as circuits and antennas.Innovations in Test and ReliabilityAn area of active interest in the hybrid electronics community is that of test and reliability. American Semiconductor, a developer of flexible circuitry, and Bayflex, a value-added partner of Japanese equipment company Yuasa, are conducting a project on dynamic harsh environmental FHE reliability testing. The goal is to identify root causes of FHE material and system failures.The companies are developing extended temperature and humidity tests to determine FHE system lifetimes and identify causes of failures from physically deforming FHE materials and systems in harsh temperature and humidity environments. Materials under consideration for testing include:Copper on polyimide substrate with a small outline package IC and surface-mounted componentsNobleflexTM, a multilayer substrate with gold on polyimide in development for medical devicesSilver on PET substrate, with small outline package IC.The team is soliciting other test devices and is planning to coordinate with ongoing development of FHE test standards coordinated by SEMI.Henkel reported on an investigation of accelerated temperature cycling test methods, in which the company applied different combinations of temperature range, stress, and frequency of mechanical force in an effort to reduce cycle time for testing component attach reliability. The study was able to achieve similar failure modes using an accelerated test method in the case of a bonding position shift in which cracking of the die attach film was the failure mode (Fig. 4, approach 4). The study found the greatest acceleration in the case of reduced thermal shock cycles (Fig. 4, approach 1).Fig. 4. Approaches evaluated for accelerated testing of component attach.Engineering consulting firm Exponent presented the results of a study on mechanical testing for characterizing fatigue performance of flexible electronics, conducted with continuous monitoring of fatigue for 6-pin flexible flat cables from seven different vendors. Exponent found that continuous monitoring during bending fatigue testing provided greater resolution in test results including detection of intermittent failure in each sample. The study also found that strain amplitude was a critical factor for determining fatigue life, and that flat flexible cables with larger pitches showed improved fatigue performance.About SEMI FlexTechFlexTech, a SEMI Strategic Technology Community, promotes the growth, profitability and success of the flexible hybrid electronics industry by developing educational forums, directing research, and promoting technology innovation.SEMI FlexTech members benefit from speaking and business networking opportunities, introductions to key industry players, research reports, technical funding, access to end users and industry advocacy at FLEX Conferences.Gity Samadi is Director of SEMI research and development funding programs and SEMI FlexTech and SEMI Nano-Bio Materials Consortium (NBMC). Paul Semenza is an advisor to SEMI on special projects. He was previously with NextFlex, the Flexible Hybrid Electronics Manufacturing Innovation Institute.

The FLEX Conference, held again this year in conjunction with SEMICON West 2023, provided numerous examples of continued developments in flexible, printed, and flexible hybrid electronics technologies applied to sensing, robotics, communications, and other applications.

SEMI spoke with Christian Driller, Vice President of Research and Development at Comet Yxlon, about opportunities to accelerate time-to-market and increase yield for advanced packaging manufacturers through x-ray inspection.

Focusing on applications that help assist movement in people with neuromotor disorders & aging muscle, Georgia Tech is developing a flexible system that uses sensory feedback through EMG to assess muscle and motor neuron health and augments strength through pneumatically actuated artificial muscle.

Atomic Layer Deposition (ALD) players are poised to seize a new growth opportunity after the chip shortage pushed manufacturers to announce fab capacity expansions worldwide. Driven by the wafer production volume increase, ALD solutions are now expected to grow and enter the MtM devices market.

The latest MEMS and sensors advancements in markets ranging from displays to biotech and in key areas of manufacturing including sensor devices and fabrication came into sharp focus at the 2022 MEMS & Sensors Technical Congress (MSTC) in late April as 120+ industry experts gathered in Berkeley, CA.

Anna Fontanelli, Monozukuri’s founder and CEO, is an expert in deep-submicron silicon technology and design tools shares her view on the state of Moore’s Law and challenges surrounding 2.5D integration, 3D chip stacking & advanced packaging, as well as the chip design industry’s startup environment.

As we pass the work-from-home one-year mark, most of us still work remotely and will do so for the foreseeable future. As live trade shows and technical conferences were cancelled one after the other, virtual events became the norm. And, teleconferencing became a way of life. While possibly overstating our role, we have the semiconductor industry – from system design through manufacturing and system integration – to thank for a long history of achievement that made the transition to working remotely relatively seamless and straightforward. The shift, in some cases, took some time to sort out as we set up a workable home office, moved to video conferencing with intermittent connections and settled into a routine. Nonetheless, many of us became more productive and, in some cases, even too productive. Each spoke in the global electronic products hub contributed through creativity and innovation with a pinch of ingenuity and grit. Of course, we could have worked remotely 10 years ago, but not nearly as efficiently. Over the last 10 years, the economy moved to the cloud, producing new opportunities across the global market. Many of these opportunities were made possible by the electronic system supply chain and combination of semiconductor technology, electronic product innovation and people who figured how to leverage it with software platforms to tie it together. Zoom, one of our teleconferencing lifelines, is a good example, as are Netflix, our ongoing source of entertainment, and Roblox, a platform to build games. Facebook, Twitter, LinkedIn and the like sourced the news for us and kept us in touch. Amazon delivered our online purchases and GrubHub brought us our takeout dinners. All rely on cloud computing with thanks to the semiconductor industry. Another great example are data centers powered by semiconductors and the amount of data they processed last year. According to International Data Corporation (IDC), 64.2 zettabyte (ZB) of data was created or replicated due to the dramatic increase in the number of people working, learning and entertaining themselves from home. (Its revised model for global data creation and replication predicts the CAGR will grow to 23% over the 2020-2025 forecast period, a sure bet that the semiconductor industry will address ways to manage the growth, possibly through new AI chips.) Our connectivity is driven by smartphones optimized for low power and the performance of more complex chips. Over the last 10 years, design tools have been enhanced and new methodologies have been introduced to respond to the needs of the increasing complex chips for applications that demand high bandwidth, low latency and reduced power consumption and area. Manufacturing is retooling for higher automation under smart manufacturing initiatives and packaging is even more sophisticated with increasing integration and the 2.5D and 3D packaging rollouts. Let’s take stock of our success. The semiconductor industry has a storied tradition of breakthrough technology since its inception. The consumer electronic product craze started when the first PCs were rolled out in 1971, notes the Computer History Museum. Primitive laptops that followed in 1986 gave way to notebooks in 2007 and the ubiquitous smartphone in 2002 – and the rocket fuel for much of this was the buildout of computer networks, hyperscale datacenters and the cloud. Nothing’s been the same since. The next time we turn on our laptop, click on the link for the latest teleconference from our remote home office in comfortable sweats sitting in our ergonomic chair, let’s take a minute to acknowledge our industry’s grand achievement. And, thank one and all for their contribution and consider what’s coming next. About the Author Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Strategic Association Partner. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Post-Conference Report: SEMI Heterogeneous Integration SummitDemand for high-performance computing (HPC) chips is exploding. These super-speedy chips are critical for data centers and cloud computing infrastructures to support new performance-hungry technologies such as artificial intelligence (AI) and 5G. The challenge is for the devices and their multi-core architectures to couple high bandwidth density with low latency and high energy efficiency. Heterogenous integration offers a potential answer as an advanced packaging technology designed to meet these skyrocketing performance demands on HPC chips and open the door to a whole new world of 3D integrated circuits (ICs).So important are 3D ICs that Intel and TSMC representatives speaking at the recent Heterogeneous Integration Summit hosted by SEMI Taiwan in Taipei declared that the packaging technology will all but dictate the future of the industry. All told, 12 speakers from government, academia and a broad range of leading international companies from sectors including advanced packaging, design, manufacturing, silicon photonics, equipment and materials shared forward-looking strategies, the latest technologies and potential heterogeneous integration market opportunities. Koushik Banerjee, vice president, TMG, Assembly, and Test Technology Integration, at Intel pointed out that using heterogeneous integration for a single SiP (system-in-package) will deliver what the industry has long wanted by enabling multiple process nodes, more diverse silicon IP (intellectual property) and chip functionality, and chips that pair low energy with high frequency. Intel plans to announce its first Forveros 3D packaging product combining a 10nm HPC chiplet with a low-energy 22nm base die and stacked with memory on top. When asked about the future of advanced packaging technology, Banerjee said it will be very much about the combination of Foveros and its very own Embedded Multi-Die Interconnect Bridge (EMIB).For its part, TSMC, will continue to upgrade its CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated Fan-out) and other 2.5D IC production solutions while developing 3D chip stacking technology such as SoIC and WoW (wafer-on-wafer). TSMC is ushering in a new age of 3D IC packaging, said Marvin Liao, Vice President, Backend Technology and Service Division, at TSMC. The company’s SoIC is based on Chip-on-Wafer concept, with the flexibility to support one-to-many or different process nodes, whereas its WoW integrates two wafers with solid yields that could be used for products of the same size or manufactured with mature process technology.Speakers also included representatives from ATOTECH, Lam Research, SPIL, Sigurd, Cadence, Grand Process Technology, ITRI (Industrial Technology Research Institute), Industrial Development Bureau, and Lee San-Liang, Distinguished Professor, Department of Electronic and Computer Engineering at National Taiwan University of Science and Technology all shared their perspectives on equipment, materials, and testing and how different industry value chains might contribute to the development of heterogeneous integration technology.Expected to be a key driver of the next wave of semiconductors, heterogeneous integration and related technologies – including 3D IC, FOWLP (Fan-out wafer-level packaging) / FOPLP (Fan-out panel-level packaging), silicon photonics, Micro LED, compound semiconductor, automated optical inspection and SLT (system level testing) – will be a key focus at SEMICON Taiwan 2019, September 18 to 20 in Taipei. The Heterogeneous Integration Innovation Zone – along with featured international programs such as SiP Global Summit, Strategic Materials Conference, the Smart Data Summit and the Smart Automotive Summit – will gather key industry players to reveal the latest technology breakthroughs and market trends.Emmy Yi is a senior marketing specialist at SEMI Taiwan.