22FDX

“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game. The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines. It was a full day of excellent presentations. In this post, I'll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”. Andes Technology As semiwiki noted a few years back, Andes Technology is “...the biggest microprocessor IP company you've never heard of.” Based in Taiwan, Mediatek is one of their big customers; they've got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF's 22FDX® FD-SOI technology. In his symposium keynote, CEO Frankwell Lin said that in the test chip they're doing with GF and Invecus, they're seeing a 70% power savings compared with what they'd gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they'll announce a core that runs on Linux. NXP “With FD-SOI we're enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP's i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It's better than any technology I've worked on in my 30 years in the industry,” he said. They're seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today's competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung. FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages. NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino. Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don't want to take the extra time for or don't have a connection to the cloud. iMX and FD-SOI enable scalable solutions, he concluded. Audi What's a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation. [caption id="attachment_11790" align="alignleft" width="300"] Audi Project Manager Andre Blum says SOI stands for Solutions, Opportunities and Innovation -- at the 2018 SOI Symposium in Silicon Valley.[/caption] Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they're needed. They'll create a cocoon around the car for the best driver experience. He showed a fun video Audi's made to illustrate their concept – it's the Invisible Man video, which you can check out on YouTube. But those new architectures can't up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors. Audi is one of 25 partners in a heavily funded ( 100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn't even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch! Airbus For Airbus, it's all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems. SOI has a long history in aerospace – in fact that's originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it. Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “...developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.” According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019. Sony For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They're getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers -- such the popular Amazfit line. Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn't). So Sony has partnered with triathalon teams and are seeing good results. With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018. And now they're using those FD-SOI chips in audio applications. You'll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “... is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.” Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There's a great info page with video here. https://youtu.be/1lKo9acJDPs So that's what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson's excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.

They've got initial silicon of Dream Chips' ADAS SoC fabbed in GlobalFoundries' 22FDX (FD-SOI) technology, and it's got record power efficiency (read the full press release here). The chip offers high performance image acquisition and processing capabilities and supports AI / Neural Network (NN) vision operation with a total of 1 TOPS at 500 MHz on 4 parallel engines. With all functions including quad-core Arm® Cortex®-A53, Tensilica DSPs, and INVECAS’ LPDDR4-Interfaces activated, the SoC shows single digit power dissipation without the need for forced cooling, which is of significant importance for embedding in automotive environments. [caption id="attachment_11538" align="alignleft" width="277"] Courtesy: Dream Chips Technologies[/caption] Targeting automotive computer vision applications, the SoC was created in close cooperation with Arm, ArterisIP, Cadence, GF, and INVECAS as part of the European Commission’s ENIAC THINGS2DO reference development platform, where about 40 partners in Europe cooperated to propel the FDSOI-Design Ecosystem. Of particular importance is the new and reduced power footprint of this SoC in 22FDX-technology from GF. AI/NN-operation for image recognition is available today, but most of the solutions need active cooling. Implementation of Dream Chip Technologies’ SoC on GF’s 22FDX platform demonstrated single digit Watt and cooling targets for designers managing power dissipation. If needed, the SoC bears the potential to increase the performance even further up to 2 TOPS at 1.0 GHz by applying GLOBALFOUNDRIES’s forward body-bias capabilities and other optimization techniques. The jointly developed ADAS SoC platform from Dream Chip Technologies is available now. Part of GF’s FDXcelerator™ Partner Program, Dream Chip is the largest independent German Design Service company specialized in the development of large ASICs, FPGAs, embedded software and systems with a strong application focus on automotive vision systems (ADAS).

FD-SOI has hit Q1 with terrific momentum, both in terms of visibility into products and in press coverage. In case you missed them, here are three articles you should definitely read: FD-SOI Adoption Expands – Technology shifts direction after years of competing directly with CMOS at advanced nodes (by Ed Sperling at Semiconductor Engineering) 22FDX Shows IoT Traction at MWC 2018 (by David Lammers for GF's Foundry Files) The Future of Silicon: An Exclusive Interview with Dr. Gary Patton, CTO of GlobalFoundries (by Ian Cutress at AnandTech) But, if you don't have time to read them all right away, here are some highlights to tide you over til you do. Expanding Adoption Ed Sperling at SemiEngineering sees FD-SOI adoption “... gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.” After recounting the advantages (with which ASN readers are well familiar), he notes that two things have changed in our industry. First, fewer and fewer companies can afford to design in the most advanced FinFET nodes. And second: there are enough emerging markets where power is critical, but there won't necessarily be the billions of units per chip needed to amortize exorbitant design costs. In particular, for FD-SOI adoption he cites, “...the inferencing stage of machine learning [note: that happens in “edge” devices], base-stations, IoT and IIoT, bitcoin mining, 5G, radar, and a variety of automotive applications.” (GF's Jamie Schaeffer makes the technical case in the article for NB-IoT and automotive if you want more info.) ST's Giorgio Cesana makes an interesting point about body biasing (that I hadn't hear before) re: uni-direction vs. bi-directional. Currently, he explains, body biasing is uni-directional – although you can use it now in such a way that is effectively bi-directional. However, after the 22nm node, it will become truly bi-directional, which will enable wider swings for power savings. (For those concerned about pre-mature chip aging, see the full article for explanations by experts from Soitec who explain why that's not a problem after all.) Cesana also points out that the kind of chips leveraging FD-SOI are not the kind of chips that will need to move to a new node every year. They're looking for power savings, not shrink. Sperling goes on to make an interesting observation about Intel/MobileEye and power savings vs. shrink – by all means read what he has to say about that.... In conclusion, Sperling asserts that we are now witnessing a shift in the semi supply chain essentially dovetailing with the expansion of FD-SOI adoption and its ecosystem, wherein “...as new markets open up, chipmakers are finding themselves much closer to the application than in the past.” All in all a great read – don't miss it. Products! David Lammers (who you probably know from SST) wrote about products on FD-SOI for GF's Foundry Files in 22FDX Shows IoT Traction at MWC 2018. A number of start-ups will be showing products on GF's 22FDX (FD-SOI) technology at Mobile World Congress. For example, Nanotel Technology is using 22FDX to “...reduce power consumption for its mixed-signal NB-IoT modem.” Lammers interviewed the company's CTO, Anup Savla, who explained, “We have a digital engine, a processor, designed around IoT applications, where the emphasis is on low power and low leakage. With 22FDX there are knobs that are available to turn down the power and leakage. The opportunities to do that are unparalleled, and you just don’t get that kind of opportunity from bulk CMOS.” A significant part to this design is analog – which of course really benefits from FD-SOI. [caption id="attachment_11520" align="alignleft" width="300"] Riot Micro CEO Peter Wong cites savings in power, area and TTM with 22FDX. (Courtesy: GlobalFoundries)[/caption] Riot Micro on the other hand, has designed an all-digital cellular modem for LTE Cat-M and NB-IOT. There's no DSP, and big parts of the chip can be shut down as needed to save power for long-term battery operation in the field (get more details in the full GF blog). Several major cellular carriers are on track to certify it this year, and a Middle Eastern customer plans to incorporate it into an emergency-alert system. The company's CEO, Peter Wong told Lammers, “With 22FDX, the value proposition for us is potential power and area savings.” They also leveraged the growing 22FDX IP ecosystem to accelerate TTM. Dream Chip Technologies, which as Lammers reminds us, showed their multi-core vision processor at MWC last year, says that now “...the design is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives.” Verisilicon, an SOI Consortium member and a major FD-SOI champion in China will be teaming up with GF show their dual-mode connectivity solutions (which we first heard about last year). GF and VeriSilicon have a suite of IP so that customers can create single-chip, low-power wide-area (LPWA) solutions that support either LTE-M (for the US) or NB-IoT (for Asia Europe). The IP covers integrated baseband, power management, RF radio and front-end components. Lammers also cited Anubhav Gupta, GF's director of strategic marketing and business development for IoT, AI Machine Learning. He said they've got customers taking older multi-chip designs and re-creating them as single-chip solutions in 22FDX for better performance and savings in area, power and cost. Gupta noted that with body biasing in digital designs, they can operate down to 0.4V with standby leakage currents of less than one picoamp per micron. And when embedded MRAM is used in tandem with on-chip SRAM, off-chip flash can be completely eliminated. Nice! Clear Winner In a wide-ranging interview (see part 7, which focuses on FD-SOI), GF CTO Gary Patton told Anandtech's Ian Cutress that, “FinFET is a great technology for [performance at any cost], but if you're looking for something that is more in the consumer space, you need to balance performance with power and cost, you know FD-SOI is a clear winner.” Patton told Cutress that they have working 12FDX devices in NY that are already close to reaching performance targets. They'll be in risk production in early 2019. Meanwhile in 22FDX, Patton talked about the different flavors, including RF, ULP, UL leakage and mmWave, and how well suited they are for target applications especially in automotive and IoT. Elsewhere in the interview he mentioned that potential customers in the cryptocurrency mining businesses are looking at 22FDX, and that ST will be using it to do some “incredible products”. All in all – products and press – it's a really fine Q1.

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.The talks, which are being given by a stellar line-up of experts, include: RF SOI, fabrication, materials and eco-system - Ionut Radu Director of Advanced R D, Soitec Fundamentals of RF SOI technology - Jean-Pierre Raskin, Professor, UCL 22nm FDSOI Technology optimized for RF/mmWave Applications - David L. Harame, RF CTO Development and Enablement, GlobalFoundries RF SOI technology and components for 5G connectivity - Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti Analog and RF design on SOI - Barend van Liempd, Senior Researcher, imec Techniques and tricks for RF measurements on SOI - Andrej Rumiantsev, Director RF Technologies, MPI Corporation FOSS TCAD/EDA tools for advanced SOI-device modeling - Wladek Grabinski, R D CM Manager, MOS-AK RF design flow for SOI - Ian Dennison, Design Systems Senior Group Director, Cadence The course is being organized by SOI Consortium members Incize and Soitec. BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs. EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.

With back bias,12nm FD-SOI beats 10nm FinFET on performance. This excellent news comes in by way of Peter Clarke of EETimes Europe (read the whole article here). Rutger Wijburg, GM of GloFo’s Dresden fab told him, "If you look at performance with back-bias 22FDX is the same or better than 16/14nm FinFET process. With 12FDX with back bias you get better than 10nm FinFET processes."

12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here). [caption id="attachment_9874" align="aligncenter" width="610"] (Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)[/caption] The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. "We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China," said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products." Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.” The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.” All About 12GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency. [caption id="attachment_9873" align="aligncenter" width="610"] (Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)[/caption] “Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.” Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here). 22 Design Plug ‘n PlaySimultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services. Initial FDXcelerator Partners have committed a set of key offerings to the program, including: tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features, a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements, platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX, reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market, resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology; and product packaging and test (OSAT) solutions. Additional FDXcelerator members will be announced in the following months.

By: Tamer Ragheb,Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT). GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day. [caption id="attachment_9473" align="alignleft" width="610"] Figure 1: Benefits of 22FDX body-biasing[/caption] The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode. [caption id="attachment_9474" align="alignleft" width="610"] Figure 2: 22FDX Body Bias Optimizes Performance and Power[/caption] In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include: Improved electrostatic control of the transistor acts as a performance booster and enables lower VDD (i.e., lower power consumption) while reaching significant performance Low variability and body-biasing capability that can achieve 0.4 volt operation Complete RF enablement with ‘knobs’ to reduce RF power by up to 50 percent Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs. There are four application optimized extensions available with 22FDX (Fig. 3). These are: 22FDX ULP- an ultra low-power extension that provides logic libraries and memory compilers that are optimized for 0.4 volt operation. 22 FDX ULL- an ultra low-leakage extension that brings in an expanded device suite capable of achieving one pico-amp per micron leakage. 22 FDX UHP- an ultra high-performance extension that leverages the overdrive capabilities and body-biasing features to maximize the performance of technologies in a turbo or a burst mode. It has high performance libraries and high speed interfaces and BEOL stacks optimized for competing architectures or applications. 22 FDX RFA- an RF and analog extension that brings in full characterization and enablement for RF applications, including optimized RF layouts and P cells, BEOL passives, and IP for Bluetooth LE and WIFI applications. [caption id="attachment_9475" align="alignleft" width="610"] Figure 3: 22FDX Platform and Extensions[/caption] GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications. GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction. Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include: Design Compiler® Graphical synthesis with IEEE 1801 (UPF) driven bias-aware multi-corner multi-mode (MCMM) optimization Formality® formal verification with bias-aware equivalence checking IC Compiler™ and IC Compiler II™ layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation StarRC™ parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF) PrimeTime® timing analysis and signoff including distributed multi-scenario analysis (DMSA) static timing and noise analysis, using AOCV and POCV technology IC Validator In-Design physical verification The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.