Arm

Editor's note: Arm and Samsung Foundry are extending their collaboration on FD-SOI, which they'll be highlighting at the SOI Consortium's Silicon Valley Symposium April 9th. In the meantime, Arm Senior Product Marketing Manager Umang Doshi described the range of projects in a recent Arm Community / Developer physical IP blog. We thank Arm for sharing this blog with ASN readers.~ ~~ Samsung Foundry and Arm FDSOI collaboration announced By Umang Doshi The challenge with designing at newer and more advanced process nodes is that things generally don’t get less complex and expensive, much as we might want this. Still, the upside to each new process node, generally, is that you can build more highly efficient and targeted devices to address more markets and applications in a timely fashion. For the complexity and cost challenges, however, there’s good news: Arm and Samsung Foundry just announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler at 18FDS (18nm FDSOI). In addition, the Arm offerings for 18FDS include three POP IP packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processor IP. The platform will help drive new leading-edge designs in power-sensitive applications in 5G, artificial intelligence (AI), automotive, Internet of Things (IoT), and other market segments. It’s the industry’s first, fully comprehensive physical IP platform that includes an eMRAM compiler at 18FDS. 28nm: Before the breakthrough One of the most widely embraced nodes, 28nm the so-called “forever node,” has done wonders for industry innovation over the years. However, leakage power is still challenging for planar transistors. Engineers deployed high-K metal gate (HKMG) at 28nm, to combat leakage, but it’s still an issue. That’s because the channel underneath the gate is too deep and too far from the gate to be well-controlled, which results in higher leakage power. Solutions for the leakage issue have prompted designers to embrace FinFETs and FDSOI (fully-depleted silicon-on-insulator) with thinner channels that enable greater control by the gate. Indeed, FDSOI is gaining traction in the market place. By construction, 28nm FDSOI enables much better transistor electrostatic characteristics versus conventional bulk technology. 28nm FDSOI offers: Wide Forward/Reverse Body-bias range and flexible Poly bias (PB) range to tradeoff power/performance. Better performance and power than bulk process technology. Better resistance to radiation and SER. Less sensitive to variability because there’s no channel doping. Ultra-low power voltage (operating at low voltages in the hundreds of millivolts range). Easy migration from bulk versus the previous SOI version, PDSOI (partially-depleted silicon-on-insulator), required unique timing and power models. What’s more, there are cost benefits today and more forecast for the future. Arm and Samsung Foundry extend FDSOI leadership from 28FDS to 18FDS In 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology. Since the announcement, Arm has engaged with several Samsung Advanced Foundry Ecosystem (SAFETM) partners on a landscape-changing collaboration to deliver the industry’s first 28FDS eMRAM-enabled IoT silicon system demonstrator telling the Arm IoT story on Samsung Foundry silicon. Coupled with Arm’s IoT ecosystem, Pelion IoT Platform and Platform Security Architecture (PSA) solutions, this 28FDS eMRAM-enabled IoT demonstrator will showcase a new-generation of secure and energy-efficient IoT edge devices which integrates software stacks offering secure boot, firmware updates, on-chip storage, chip to cloud communication and device/software provisioning. The combination of 28FDS and eMRAM non-volatile memory brings new opportunities for a new class of highly integrated and energy-efficient designs. We’re thrilled that Samsung Foundry has extended its successful collaboration on FDSOI technology from 28FDS process to 18FDS. With the new platform, 18FDS is a cost reduction solution with lower power and same back end of line (BEOL) as 14nm FinFET. It has RF and eMRAM support to enable the widest range of different applications. “18FDS is the next-generation node on Samsung's FD-SOI roadmap with enhanced power, performance, and area (PPA)," said Jaehong Park, executive vice president of Design Platform Development at Samsung Electronics. “The relationship between Samsung Foundry and Arm stretches back more than a decade and has helped put the right design technology in the hands of the world’s leading designers. The enhanced PPA from our 18FDS process combined with Arm cores and Artisan Physical IP will again bring the cost and time-to-market advantages to enable the competitive and differentiated SoC designs.” Highlights on Arm-Samsung 18FDS platform Includes seven memory compilers, three logic libraries, two (1.8 and 3.3V) GPIO libraries, three POP IPs and the eMRAM memory compiler. Supports automotive AEC-Q100 Grade 1 design requirements, and comes with ASIL-D support and a complete automotive safety package. Utilizes back biasing supported by the FDSOI technology to help achieve low leakage by using reverse body-bias technique or a performance boost using forward body-biasing. This is a key differentiation of 18FDS platform. Supports Logic Corner Generator (LCG) and Memory Compiler Corner Generator (MCCG). LCG and MCCG products allow designers to generate custom corners with body-bias voltages to take the maximum advantage of body biasing power-performance flexibility. 18FDS will help enable the development of new devices connecting consumers in entirely new ways, whether it’s in AI, 5G mobile, automotive or other areas. The platform will be available in late 2019. Arm's Physical Design Group has a track record of successful implementations with Samsung Foundry across multiple generations of process nodes and products. Besides 28/18FDS, Samsung Foundry and Arm also have 14LPP/LPC, 11LPP, 7LPP and 5LPE platform collaborations. Interested in knowing more about Artisan Physical IP at 28/18FDS? Come join us at SOI Silicon Valley Symposium on April 9 at Double Tree by Hilton, San Jose, California. During the event, you will have the opportunity to hear how Arm and other industry leaders work together to accelerate the adoption of FDSOI technologies including products and applications. Alternatively, you can also reach out to us with your inquiry.

That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point. Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings. The original goal of the panel was “...to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet 'always-on' market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.” (Update 2 August 2018: a complete video of this panel is now available on YouTube -- click here to view it.) [caption id="attachment_12035" align="alignnone" width="958"] #55 DAC Expert Panel: How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? Left to right: Brian Fuller, Arm (moderator); Scott Hanson, Ambiq Micro; Lauri Koskinen, Minima Processor; Mahbub Rashed, GlobalFoundries; Paul Wells, sureCore. (Organized by Jan Willis of Calibre Consulting)[/caption] The panelists included: Scott Hanson - Ambiq Micro Mahbub Rashed - GLOBALFOUNDRIES Lauri Koskinen - Minima Processor Paul Wells - sureCore Ltd., Sheffield Brian Fuller of Arm served as moderator. [caption id="attachment_12033" align="alignright" width="200"] Panel organizer Jan Willis, Calibre Consulting[/caption] Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on! #55DAC Expert Panel on Near-Threshold Voltage Sees Growing Opportunity Despite ChallengesFirst published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships Marketing Executive Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25. Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what's not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It's required innovating throughout the design process including test where Scott said they had create their own "secret sauce" to make it work. Later on in the panel, Scott described designers in near-threshold as "picojoule fanatics" to overcome the limitations in design tools which are geared towards achieving performance goals. Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design. Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield. Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor's note: sureCore's CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.] Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it's gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there's been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future. ~ ~ ~ This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original. * As explained by Rich Collins of Synopsys in the TechDesign Forum: "Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. [...] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on. Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. [...] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.

Per Arm, the industry's first eMRAM compiler IP is now on Samsung's 28nm FD-SOI technology. The announcement was made in a post by Kelvin Low, VP Marketing for ARM's Physical Design Group (read it here). He said that ARM has successfully completed their first eMRAM IP test chip tapeout. The Arm eMRAM compiler IP will be available from 4Q 2018 for lead partners. Samsung Foundry’s 28nm FD-SOI process technology is called 28FDS. eMRAM (which stands for embedded MagnetoResistive RAM) is a novel non-volatile memory (NVM) option positioned to replace incumbent NVM eFLASH, which has hit its limits in terms of speed, power, and scalability. Arm's new eMRAM compiler IP gives Samsung's 28FDS customers the flexibility to scale their memory needs based on the complexity of various use-cases, explains Low. “What drives the cost-effectiveness of this compiler IP is that eMRAM can be integrated with as few as three additional masks, while eFlash requires greater than 12 additional masks at 40nm and below,” he says. “Also, the eMRAM compiler can generate instances to replace Flash, Electrically Erasable Programmable Read-Only Memory (EEPROM) and slow SRAM/data buffer memories with a single non-volatile fast memory – particularly suited for cost- and power- sensitive IoT applications.” [caption id="attachment_11972" align="alignleft" width="300"] A key slide shown by Arm at the 2017 SOI Consortium's Silicon Valley Symposium (Courtesy: Arm and the SOI Consortium)[/caption] At the SOI Consortium's 2017 Silicon Valley Symposium, Arm said that they were stepping up their support of FD-SOI (read about that here) – and clearly they are! At that event, Arm VP Ron Moore gave a great presentation, which is freely available on our website: Low Power IP: Essential Ingredients for IoT Opportunities. Samsung, btw, has been offering 28FDS for about three years now. (ASN did a 3-part interview with Kelvin Low back in 2015 when he was a senior director of marketing for Samsung Foundry. It's still a useful read – you can get it here.) As of last fall, Samsung said it had taped out more than 40 products for various customers. And at the SOI Consortium's 2018 Silicon Valley Symposium, Hong Hoa, SVP said they'd already taped out another 20 this year (read about that here). https://youtu.be/EB14K8Gq5-w Samsung says the write speed of their eMRAM is 1000x faster than eFlash. They actually announced the industry's first eMRAM testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here). They also did an eMRAM test chip with NXP. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it above or on YouTube here.) As noted in ASN's Silicon Valley 2018 symposium coverage, the basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDS platform will be ready by the end of this year, and eMRAM beginning in 2019.

The MCU at the heart of Sony's new smart-sensing SPRESENSE™ for IoT is built on FD-SOI. Why? Low operating voltage and low power consumption, of course! Sony's got two cool new products going on sale in July 2018: the SPRESENCE main and extension boards for IoT applications, equipped with a smart-sensing processor (read the full press release here). A CXD5602PWBCAM1 camera board for sensing cameras will go on sale in August. All were on display at the SF Maker Fair '18, where they were an instant hit. [caption id="attachment_11931" align="alignright" width="300"] Here are the main features of Sony's CXD5602 MCU for IoT, which is built on FD-SOI. (Courtesy: Sony Semiconductor Solutions)[/caption] The main board (it's open source, btw) will run about US$50. You'll find the specs and main features here. Spresense is powered by Sony's FDSOI-based CXD5602 MCU (ARM Cortex-M4F × 6 cores), with a clock speed up to 156 MHz. The main board utilizes a multi-CPU structure equipped with Sony's state-of-the-art GNSS (Global Navigation Satellite System – which they talked about at the most recent SOI Symposiums in SF and Tokyo) receiver. A variety of systems for diverse applications, including drones, smart speakers, sensing cameras and other IoT devices, can be built by combining these boards and developing the relevant applications. The new board can be used to control a drone, for example, using GPS positioning technology and a high-performance processor, voice-controlled smart speakers, low-power consumption sensing cameras and other IoT devices, etc. It can also be combined with various sensors for use in systems that detect errors in production lines on the factory floor.

Some really innovative start-ups presented chips they're doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We'll cover those here in Part 3 of ASN's coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion. BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who's designing chips on FD-SOI, and VLSIresearch explained why. You can read that here. Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here. Start-upsIneda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They're using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes. In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud. Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN's coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor's talked about their roadmap. [caption id="attachment_11865" align="alignleft" width="300"] (Courtesy: eVaderis, SOI Consortium)[/caption] eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July '18. Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic. Simgui Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec's Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting. In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers acquisitions would not solve the problem, they've opened a second round, targeting another $160 billion. China's two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals. IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said. Panel Discussion [caption id="attachment_11866" align="alignleft" width="300"] SOI Symposium Panel Discussion: (left to right): Giorgio Cesana (Co-Director SOI Consortium), Dave Eggleston (VP GF), Tim Saxe (CTO, Quicklogic), Wayne Dai (CEO, Verisilicon), Samir Patel, (CEO Sankalp Semi), Kelvin Low (VP, ARM), Mahesh Tirupattur (EVP, Analog Bits)[/caption] The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists. QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you've got one set of IP, and you can decide at runtime where you're going for low power or high performance. With a lot of power domains, you see the benefits at the system level. GF VP Dave Eggleston said they're seeing early adopters of eMRAM, especially for wearables with RF and low power. ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores. Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”. It's not too late for FD-SOI: it's perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they're happy to focus on companies still on the older nodes. The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You've got more potential customers, and your volume runs can be bigger. In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day's three take-aways: power consumption is driving even systems companies FD-SOI is penetrating fields like MCUs and SoCs where more intelligence is needed China is still a really big opportunity.

They're calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It's NXP's new i.MX 7ULP general-purpose processor, and it's on 28nm FD-SOI. They've got a nifty video summing it all up – you can watch it here. [caption id="attachment_10388" align="alignleft" width="300"] NXP is first to market with a general-purpose processor on FD-SOI: the i.MX 7ULP. It's got both ultra-low power consumption and rich graphics for battery powered applications. (Courtesy: NXP)[/caption] With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.Hello, IoT!The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.With the i.MX 7ULP, NXP's targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it's designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)The detailsThe i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It's got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors. [caption id="attachment_10387" align="alignnone" width="834"] (Courtesy: NXP)[/caption] NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.Leveraging body biasing and moreNXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages: Large dynamic gate and body biasing voltage range Domain and subsystem optimization with custom standard cell library with mixed voltages Low quiescent current (Iq) bias generators Enhanced ADC performance with unique FD-SOI attributes Fail Safe I/O for simplified low power system design To that, add a note about security. As the chip's fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it's needed.Samsung fabs, Verisilicon adds IPTwo other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP's results.“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.-- By Adele Hars, ASN Editor-in-Chief