IP

In an era where technology permeates every aspect of our lives, the semiconductor industry serves as the backbone of innovation. From IoT devices to data centers, every piece of technology relies on integrated circuits (ICs) such as intellectual property (IP) cores and system on chips (SoCs). As these technologies become increasingly pervasive, the importance of hardware security assurance in the design and development of IP and SoCs cannot be overstated. Evolving cyber threats and sophisticated attacks make it essential for vendors to integrate advanced security measures into their workflows.Market Pressures Driving Demand for Enhanced Hardware Security The semiconductor market is projected to reach $1 trillion by 2030. At the same time, semiconductor devices and system designs are becoming increasingly complex. With that complexity comes the added difficulty and effort required to conduct thorough security analyses. Additionally, competitive pressure to reduce time-to-market means that vulnerabilities can be more easily overlooked or exploited, making it crucial for the industry to adopt automated security solutions. As more products are deployed in critical systems, from consumer electronics to national infrastructure, the stakes become even higher, underscoring the necessity for robust security measures.According to the SEMI Electronic Design Market Data (EDMD) report, in 2023, the electronic design automation (EDA), semiconductor IP, and related services market reached $17.1 billion, fueled by the increasing complexity of semiconductor designs and the growing emphasis on security. While the overall EDA market is growing at a 7.4% compound annual growth rate (CAGR), the semiconductor IP segment is expanding at 9.7%, and in comparison, the logic verification tools market alone is surging ahead at 24.2%. Deeper verification processes and tools are needed to not only handle the rising complexity of semiconductor designs, but also to support the growing emphasis on secure-by-design principles to ensure robust and reliable products in an evolving technological, security, and threat landscape. As a result, the market for logic verification tools — a key component of the EDA market — is surging. The Rising Cost of Cyber Threats from Data Breaches and Architectural Flaws Pavani Jella, Silicon AssuranceThe average cost of a data breach is $4.88 million1, encompassing lost business, regulatory fines, legal fees, and damage to brand reputation. As the semiconductor market grows, the potential financial impact of security breaches due to hardware vulnerabilities also escalates. Companies must invest in robust security measures to mitigate these risks and protect their financial health.Cyber threats from the exploitation of architectural flaws are another threat. Plundervolt is one example of an architectural flaw that could lead to hardware exploitation. Discovered by ethical hackers, Plundervolt is the name of an attack that exploited voltage fault injection to compromise the security of Intel processors. By manipulating the voltage supplied to the CPU cores, attackers could induce errors in the SGX enclave, allowing them to leak sensitive data or even bypass security protections intended by the enclave. This flaw was particularly concerning because it operated at the hardware level, making traditional software security measures ineffective. The attack leveraged the SoCs’ power management features, specifically dynamic voltage and frequency scaling (DVFS), to achieve its malicious objectives.Exploiting such a vulnerability could lead to the exposure of sensitive data, such as cryptographic keys and proprietary information, compromising the confidentiality of secure enclaves. This breach could erode trust in an IP or SoC provider’s security features, particularly in environments that rely on using the IP or SoC for protecting critical data. In cloud environments, a successful exploit could result in multi-tenant data breaches, impacting numerous users.The vulnerability also poses risks to secure applications, potentially leading to manipulated outcomes and decrypted communications. Businesses could face significant financial losses, operational disruptions, and regulatory consequences due to such an attack. It is a stark reminder of how architectural flaws in SoCs can be exploited, leading to severe security breaches that are challenging to mitigate without hardware-level fixes.Industry Believes Hardware Security Assurance Is a Key Priority A majority of security professionals from a diverse group across industry, defense, government, and academia rate hardware Trojan detection, IP piracy protection, and SoC vulnerability assessment as high priorities. This prioritization reflects the industry's awareness of the critical importance of security measures in maintaining the integrity and reliability of semiconductor products.As a result of this awareness, investments in cybersecurity are expected to reach $345.4 billion by 2026, growing at a CAGR of 9.7%2. This substantial investment demonstrates the global commitment to enhancing security measures across all industries, including semiconductors, to combat the escalating threat landscape.New EDA Tools and Investments Needed to Combat Cyber Threats The adoption of new EDA solutions is essential, despite the initial costs. Costs can range from $100,000 to $1 million per license for general EDA design and verification tools, depending on the complexity and capabilities of the software. Pre-silicon security EDA tools can detect vulnerabilities early in the design phase, significantly reducing the risk of exploitation and the need for costly post-production fixes while enhancing product reliability. Secure-by-design principles ensure that security measures are integrated throughout the development process, rather than added as afterthoughts.Integrating these new tools also requires investment in training and potential adjustments to existing workflows. However, the improved security and efficiency provided by these tools can offset these initial costs.While the costs of acquiring advanced EDA tools and deploying them in the workflow is significant, the investment is justified by the long-term benefits of enhanced security and reduced risk of costly breaches. Secure-by-design practices can prevent significant financial losses from security breaches, offering substantial long-term savings. Companies that invest in robust security measures are better positioned to demonstrate market leadership and build customer trust and loyalty, while avoiding the reputational and financial damage associated with breaches.ConclusionThe semiconductor industry is at a critical juncture where the application of advanced EDA solutions for hardware security is not just beneficial, but essential. The time to act is now.The increasing sophistication of cyber threats and the financial repercussions of security breaches make it imperative for IP and SoC vendors to adopt advanced EDA security assurance solutions to secure their designs. By investing in cutting-edge EDA tools and prioritizing security from the earliest stages of design, vendors can safeguard their products, maintain market competitiveness, and protect against the ever-evolving landscape of cyber threats.References1. IBM Cost of a Data Breach Report 20242. KPMG 2024 Global Semiconductor Industry OutlookPavani Jella is the Vice President of Business Development at Silicon Assurance, a member of the Electronic System Design Alliance (ESDA) a SEMI Technology Community. Silicon Assurance specializes in hardware security assurance solutions. With a strong background in the semiconductor and EDA industries, Pavani plays a pivotal role in driving strategic growth and fostering innovative partnerships. Passionate about the intersection of technology and security, she helps organizations adopt state-of-the-art solutions that ensure the resilience and trustworthiness of their hardware systems.

I recently spoke with Shi about his talk Looking Forward to the New Chip Cycle during the opening of the 2023 Design Automation Conference, collocated in July with SEMICON West in San Francisco.

Rick Eram, Excellicon’s VP of sales and operations, discusses ways for designers to compare the physical floorplan against the actual register transfer level (RTL) code and constraints, chip design trends and complexity, and a few of his predictions for the design and verification market.

Azeez Bhavnagarwala, Metis’ founder and CEO, speaks about advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors.

As a leading analyst covering the electronic system design segment, Laurie Balch is well steeped in identifying and analyzing technology trends and forecasting new market opportunities. Laurie is now President and Research Director at Pedestal Research.

Adnan Hamid, CEO, founder and visionary of Breker Verification Systems, an ESD Alliance member based in San Jose, Calif., once described his job in chip design verification at AMD as “breaking things.” When it came to naming his startup, Breaker was a natural choice. After some consideration, the “a” was dropped and the company became Breker. Now Hamid is breaking the most complex semiconductor designs and Breker, moving from a startup to a scale-up company, is a noted part of the functional verification space. Smith: Why does verification continue to take the most amount of time in a project cycle? Hamid: The project cycle for semiconductor design has changed. Design abstraction has been raised to a much higher level than the days when developers were connecting logic gates. Today’s developers are typing functions that don’t include lower-level implementation details. Designs incorporate more blocks of reusable IP. Both reduce design time. Meanwhile, designs are getting bigger with more blocks of IP stitched together, all in need of testing. As design complexity grows, the amount of testing and verification increases as a square of design effort. One block requires one functional verification effort. Four blocks of IP mean up to 16 functional interactions require verification. While design is moving up the abstraction level, that’s not the case for verification, where plenty of detail must be reimplemented. Verification has certainly evolved, but engineers still think at the level of independent stimulus, response and coverage, driving the need to allocate so much time for verification. Smith: Are chips targeting artificial intelligence and machine learning applications more difficult to verify? If so, why? Hamid: Yes, absolutely and it’s an interesting challenge, especially given that machine learning is based on massively connected processing element arrays. Attempting to verify the individual processing elements and the critical interconnects is complex. AI device arrays and, interestingly, verification test content operation may both be thought of as a mathematical graph of processing elements and interconnect. Their operation involves walking through the graph form to generate a result. Finding the optimum path through these arrays is key. To understand how these systems may be effectively verified, it is worth investigating planning algorithms. Originally proposed by IBM, these hold the key to this type of verification process. The AI- style algorithm starts backward at the end of the processing element array and tracks down the most optimal and likely paths through it. At Breker, we have used these planning algorithms extensively to drive our graph-based test content synthesis process. Smith: Does system integration require verification? Hamid: Yes, it does. In the past, most functional verification has been performed at the block level. However, with the increase in more specialized SoCs, functionality is spread across multiple blocks, as well as the software running on the processors, driving full system-on-chip (SoC) functional verification. In addition, new requirements such as security and safety must be validated. A system-level infrastructure such as cache coherency and power domain execution has become more complex and these must also be tested. The new frontier in verification is ensuring a fully operational SoC. Of course, given the size of these SoCs, hardware-assisted verification such as emulation is essential, and porting tests from block simulations to SoC emulations has become a requirement. This porting process is problematic and this in turn has driven portable tests, giving rise to the idea behind Accellera’s Portable Stimulus Standard (PSS), of which Breker was a major participant. Indeed, some companies are taking this to the next level by composing their system-level testbench at the same time as they commence SoC architectural design, and then developing the hardware design, software design and test content all in parallel, in the so-called “shift-left” manner. Smith: Is “shift-left” a growing trend that are you seeing in verification? Hamid: Yes. Shift-left is taking hold in hardware and software design, giving way to an increase in early test content composition. Then as individual blocks are finished and connected, their verification is driven from this same test content, saving a significant amount of time and effort. This is a huge verification and test generation change that was inevitable given the increased time-to-market constraints and SoC complexity. Figure 1: Shift-left is ushering in the next generation of SoC verification. Source: Breker Smith: As an entrepreneur, what advice would you give someone founding a startup or thinking about starting one? Hamid: Do not take the attitude “Build it and they will come.” My best advice for an entrepreneur or fledgling entrepreneur is to solve a specific customer problem, however narrow it might seem. Including services as part of a product offering and developing partnerships with other vendors helps with this and turns your company into a solution provider not a product developer. This is essential for getting the right products to market on time and within budget, and then ultimately scaling them across the market. The ESD Alliance and Accellera are hosting a two-part webcast series on the work-from-home experience titled Remote Work, Remote Chip Design: Building Chips During a Pandemic. The first panel, Wednesday, June 9, at 9:00am PDT, will feature a discussion led by Tom Fitzpatrick, strategic verification architect from Siemens EDA verification engineers through their experiences converting their home offices into verification test labs. The second panel in July will explore how executives managed a remote workforce and explain how they plan to bring employees back to physical offices. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

With IP the lifeblood of today’s globally integrated microelectronics supply chain, protecting confidential information is vital to electronics companies around the world. Additionally, the industry’s central role in ensuring the national security and economic competitiveness of every country ups the ante. Yet the supply chain is fraught with security risks. Malicious actors never rest in their work to infiltrate factory systems or human resources databases with the intent to steal IP, disrupt production or embed malicious software that can open the door to future attacks. Cyberattacks in the financial and retail sectors typically draw much more public attention than IT security breaches in the semiconductor industry. While large microelectronics companies are not immune to these threats, they tend to deploy some of the world’s strongest security systems and implement robust security policies and protocols to help mitigate risks. Many of their small and mid-sized counterparts with modest IT budgets and limited expertise, on the other hand, struggle to maintain a similar level of cyberhealth – a critical gap in the microelectronics industry, one of the most strategically important in the world. SEMI is out to help change that by collaborating with cybersecurity experts to help members strengthen their cybersecurity defenses. SEMI plans to increase cybersecurity awareness within the microelectronics workforce and offer cybersecurity assessments to member companies through a third-party provider as part of its SEMI Works® program. Working with experts, SEMI will add cybersecurity-related competencies to the SEMI Works® Skills Portal database to help ensure educational and training programs address these skills. As part of SEMI’s recently launched Curated Content Initiative, member companies will have access to workforce training courses on how to raise awareness of cybersecurity risks and mitigate them. Strengthening IP protections across smart technologies and industries driving the next wave of microelectronics industry growth such as artificial intelligence (AI), 5G, medtech and mobility starts in chip design and extends through fabrication to packaging and ultimately end-use applications. Helping to establish a baseline understanding and awareness of cybersecurity risks and how to mitigate them throughout the supply chain is critical. Bolstering cyber protections at small and mid-sized member companies is a key step in that direction. Commercial success, national security and the security of the ubiquitous IT infrastructures at the center of how we work and live depend on it. Mike Russo is vice president of Industry Advancement and Government Programs at SEMI.

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).

[caption id="attachment_15930" align="alignright" width="150"] Daniel Nenni, CEO Founder, SemiWiki.com[/caption] Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries' 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN. By Dan Nenni, CEO Founder, SemiWiki.com IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design. Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains. [caption id="attachment_15933" align="alignleft" width="1000"] (Courtesy: semiwiki.com and GlobalFoundries)[/caption] The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely. I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc...) to older vehicles is also heating up, especially in China. I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF's automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche. One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit. Mark provided a GF link for more information: Here is the link to our Automotive resources: https://www.globalfoundries.com/mark...ons/automotive One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely. Here is the press release: Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry's First Automotive Grade 1 IP for 22FDX Process Synopsys' Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ -- Highlights: Synopsys DesignWare IP for automotive Grade 1 and Grade 2 temperature operation on GLOBALFOUNDRIES 22FDX®process includes Logic Libraries, Embedded Memories, Data Converters, LPDDR4, PCI Express 3.1, USB 2.0/3.1, and MIPI D-PHY IP Synopsys' IP solutions implement additional automotive-grade design rules for the 22FDX process to meet reliability and 15-year automotive operation requirements Synopsys' IP that supports AEC-Q100 temperature grades and ISO 26262 ASIL Readiness accelerates SoC reliability and functional safety assessments Join Synopsys and GLOBALFOUNDRIES at Mobile World Congress in Barcelona, Spain on Feb. 25 for a panel on "Intelligent Connectivity for a Data-Driven Future" Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys' broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management. "Arbe's ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance," said Avi Bauer, vice president of R D at Arbe. "We need to work with leading companies who can support our technology innovation. GF's 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success." "GF's close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications," said Mark Ireland, vice president of ecosystem partnerships at GF. "The combination of our 22FDX process with Synopsys' DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets." "Synopsys' extensive investment in developing automotive-qualified IP for advanced processes, such as GF's 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality," said John Koeter, vice president of marketing for IP at Synopsys. "Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process." Resources For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF's 22FDX process: Foundation IP: Logic Libraries, Embedded Memories, One-Time Programmable Non-Volatile Memories (OTP NVM), and Embedded Test and Repair Data Converters LPDDR4 PCI Express 3.1 USB 2.0/3.1 MIPI ~ ~ ~ About the Author Daniel Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of "Fabless: The Transformation of the Semiconductor Industry", "Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices" and "Prototypical: The Emergence of Prototyping for SoC Design". He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.

GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019. As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone. The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs. “We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.” “In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.” As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of. ~ ~ ~ *A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago: Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off. For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering's Ann Steffora Mutschler from a couple years ago.