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Policymakers are increasing semiconductor manufacturing capacity to strengthen supply chains and meet growing demand for semiconductors through robust incentive packages totaling hundreds of billions of dollars. This global effort hinges on semiconductor manufacturing equipment (SME).

One of the surprising side effects that came out of the COVID-19 pandemic is the acceleration of the digital transformation of global economies, which has driven a structural shift and propelled the already mature semiconductor industry to record highs.

Azeez Bhavnagarwala, Metis’ founder and CEO, speaks about advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors.

From the need for more tech talent to fuel digital transformation across all industries to the great resignation and great retirement of workers en masse, the demand for tech talent continues unabated.

More than 4,000 participants convened in person at the four-day SEMICON Europa Expo in Munich, November 16-19. Attendees gathered at the Executive Forum for insights into the latest trends in the semiconductor industry and heartily welcomed the long-awaited return to in-person networking.

AEM Holdings Ltd, a Singapore-based multinational corporation, is listed in Forbes Asia’s 200 Best Under A Billion 2019 and 2020 spotlighting small and midsized companies in the Asia-Pacific region with sales under $1 billion. AEM clinched the Singapore Business Review Technology Excellence Award 2020 for Analytics-Semiconductor and the Singapore Business Awards Enterprise Award 2019/2020. These achievements are testament to AEM’s vision and innovation and the company’s contributions to the increasingly complex testing of chips in a rapidly evolving technological world. I spoke with AEM CEO Chandran Nair, a new Regional Advisory Board (RAB) member of SEMI Southeast Asia, about the company’s intelligent test and handling solutions, its role in digital transformation, the company’s key role in the smart manufacturing movement and the growth prospects for Singapore’s electronics sector. SEMI: AEM’s application-specific, intelligent system test and handling solutions for semiconductor and electronics companies serve the advanced computing, 5G and AI markets. How do you differentiate your solutions from those offered by competitors? Nair: A key differentiation for AEM is that we work closely with our customers to develop application-specific integrated test and handling solutions that meet their needs in a scalable manner from lab to production. We offer our customers customized, full-stack test and handling solutions that give them the agility to accelerate their delivery cycles and enhance product quality. Over the years, AEM has developed and acquired world-class technologies in instrumentation, test, automation, robotics, optical inspection, high-end thermal control, and software. These technology pillars, along with our deep know-how to customize test and handling solutions using the technology pillars as a platform, enable AEM to meet the fast-changing needs of our customers faced with the challenges of testing heterogeneous and complex devices. In addition to investing in technology, AEM has also invested in delivering application-specific solutions to meet customer demand. Our recently announced acquisition of CEI with its manufacturing capabilities in Vietnam and its specialization in low-volume, high-mix manufacturing increases our geographical reach and our ability to quickly turn application-specific test and handling solutions to be deployed. We have a unique and differentiated approach that enables our customers to test high-performance computing devices, automotive devices, and mobility devices with maximum test coverage, cost-effectively, in a manufacturing environment. Our experience in serving the high-performance computing market that traditionally drives advancements in thermal control also puts us at the forefront of delivering comprehensive thermal management, vision, and deep automation and test solutions for the computing, automotive, and mobility markets. AEM also has a strong instrumentation portfolio, including high-density digital instruments and mixed-signal and protocol-aware instrumentation that is well-suited for ATE solutions for SoC, high-power devices, and CMOS image sensors. Over the last few years, we have also established leadership positions in developing and deploying application-specific test solutions for MEMS devices and offering wafer and frame probing stations suitable for R D, wafer sort, and final test. We form strong partnerships with our customers, provide them with end-to-end support in product development, and take them through the entire life cycle process from concept to mass production. Chandran Nair and Goh Meng Klang, vice president of operations, at the AEM manufacturing site in Singapore. (Photo credit: AEM) SEMI: Digital transformation is powering strong growth of advanced computing, 5G and AI. Will AEM be expanding its AEM manufacturing plants in China, Malaysia and Singapore to meet rising demand for these technologies in the coming years? Nair: In regards to manufacturing, AEM currently has manufacturing facilities in Singapore, Malaysia, the U.S., Finland, and China. With our recently announced acquisition of CEI, we will add manufacturing capability in Vietnam and Indonesia. AEM will continue to expand manufacturing appropriately to give our customers cost-effective solutions while maintaining our proven track record of delivering on time and scaling rapidly in times of crises like the pandemic or geopolitical disruptions. As for advanced technologies, the three key factors that will bring the full potential of 5G to fruition are 1) cost-effective, high-powered processing devices at the edge, 2) easy access to high-bandwidth communications, and 3) cost-effective sensor technology. Semiconductors are the primary drivers of these three key success factors. As devices become more complex and our reliance on semiconductor-powered devices in all aspects of our lives deepens exponentially to include mission-critical applications, AEM’s role is to ensure that our customers' electronic and semiconductor devices are shipped thoroughly tested, safe to use, and highly reliable. It is imperative that, as a testing company, we find innovative ways to help our customers test their products with maximum coverage and minimum cost. To do this, we are focusing our R D efforts and investments to continue building on our key technology pillars to ensure that we stay ahead of the curve when it comes to test and handling solutions. We prepare our customers to test increasingly complex devices manufactured on the latest process node. SEMI: During your career you’ve driven projects in test and automation and more recently robotics solutions for ports, logistics warehouses and transport. With robotics and automation a key part of Industry 4.0, what role do AEM solutions play in powering the smart manufacturing movement? Nair: The smart manufacturing movement is powered by semiconductors, software and increasingly by artificial intelligence (AI). Test is at the heart of the process of ensuring that semiconductor and electronics devices reach the consumer well-tested for reliability. With our vision of enabling A Zero Failure World, AEM addresses the necessity for safe, highly reliable devices. The semiconductor companies themselves are adopting smart manufacturing methods. AEM’s tools are Industry 4.0-ready, and we continue to invest in machine learning and data analytics, which are integral to the future of test. Our tools are automated and feature embedded sensors to provide our customers with data about tool usage, the state of a machine’s health, and more. Our tools are connected to our customers’ manufacturing automation platforms. Additionally, we continue to invest in our ability to better slice and dice test data to understand trends and patterns to help our customers analyze data and make decisions faster. SEMI: You also have experience heading autonomous vehicle projects. With the COVID-19 pandemic hastening digital transformation, do you see an acceleration in the development of fully autonomous vehicles and smart manufacturing? Research and development efforts for autonomous vehicles (AV) continue at a fast pace worldwide. With shutdowns and restricted movement rules globally, the pandemic has hastened digital transformation in many ways. The delivery of goods and services is transforming, and AV will surely play a part, especially in secure environments for autonomous transport. The pandemic has accelerated the development of autonomous vehicles and smart manufacturing technology in automation-friendly environments like factories and ports. SEMI: At the recent Global Technology Summit hosted by SEMI, you spoke about testing innovations to meet the demands of highly complex devices. Please elaborate on innovative testing solutions versus traditional testing? Nair: AEM offers a disruptive and differentiated solution, one that is driving a paradigm shift to asynchronous, modular, highly parallel, smart testing solutions. ​ The traditional approach of ATEs to test increasingly complex devices on advanced nodes has reached a point of diminishing returns as it gets exponentially more expensive to increase test coverage to acceptable levels. Additionally, as devices get more complex and companies are rapidly adopting heterogeneous packaging technologies, the realization that System Level Test (SLT) is necessary is forcing a rethink of the entire test process. AEM’s provides asynchronous, modular, highly parallel test cell solutions that enable each test cell to run SLT, final test, or burn-in all in one system and its ability to handle hundreds of test cells independently with each test cell testing multiple devices. Our solutions suddenly make comprehensive testing of every complex device cost-effective. Freeing us from legacy ATE allows AEM to provide these innovative solutions to our customers. AEM engineering and manufacturing teams in Singapore at work on semiconductor test and handling systems for global deployment at world-class semiconductor facilities. (Photo credit: AEM) SEMI: Singapore seems to be in the sweet spot of digital transformation. Singapore’s industrial production grew 8.6% year-over-year in January 2021, an expansion driven mainly by a surge in sectors including electronics, and more growth is seen in the year ahead. Digital technologies such as 5G technology and cloud computing together with continued demand for work-from-home equipment is behind this growth. What are the growth prospects for the region’s electronics sector? Nair: Singapore is well-poised to benefit from the current digital transformation accelerated by the adoption of these technologies during the pandemic. Being a safe, well-governed country with strong IP protection, excellent infrastructure, and the rule of law, Singapore is in a great position to play a central role in cloud-based services, 5G, and the semiconductor industry. Singapore’s semiconductor sector output is at a record high, and the prospects for renewed growth in the region are very good. SEMI: As a new Regional Advisory Board member of SEMI Southeast Asia, how is your industry experience relevant to the scope of this role? What opportunities lie ahead for the region? Nair: I am honored to represent AEM in the SEMI’s Southeast Asia RAB. The SEMI RAB can influence policymakers with ideas and information on the current and future needs of the industry. I also believe that SEMI Southeast Asia can cultivate a strong innovative semiconductor ecosystem that helps regional and global growth. I look forward to working with other very experienced and accomplished board members. Bee Bee Ng is president of SEMI Southeast Asia.

Spend any time with Ansys’ John Lee, Rich Goldman or Marc Swinnen and you’ll hear plenty of optimism about the semiconductor industry even though they tick off a long list of looming design challenges. The need for reliable and effective electronic systems, they emphasize, is great and runs through high tech, aerospace and defense, automotive, IoT and 5G with communications being a common denominator. The three are especially bullish these days on changing market dynamics brought on by systems companies building company-specific bespoke, or custom, silicon. These systems companies are building chips with a different perspective and a fresh look at silicon design, a move away from the more traditional segment-specific silicon due to much more complexity. Ansys, a member of the ESD Alliance, a SEMI Technology Community, is a 4,100-employee company with a comprehensive portfolio of multiphysics engineering simulation software for product design, testing and operation products and services. John, Rich, Marc and I focused on Ansys’ semiconductor and electronics segment for our conversation. Smith: When did you notice the move by systems companies to build their own chips? What drives this trend? Lee: The inflection point was about three years ago when hyperscale data center and system companies recognized they needed an enterprise system design platform. They are designing bespoke silicon, driven to do this for cost efficiencies and to avoid relying on outside suppliers. They also want differentiation based on their specific platform needs so they can optimize compute power to their specific needs. Smith: What is driving the trend for multiphysics experience to ensure effective and reliable electronic systems? Lee: The increasing need for multiphysics analysis is acute. The physics of 3D IC, for example, brings in mechanical engineering with the convergence of mechanical and electrical as 3D emerges at the intersection of IC and System. As a result, physics becomes a necessity to analyze the stability of the chip in the package. Goldman: As well, the move to stacked chips, 3D IC and wafer-on-wafer requires thermal, electromagnetic and mechanical analysis in addition to the traditional analysis for function, performance and power. They all need to be analyzed together, not serially. It becomes multiphysics, not multiple physics. Smith: Two distinctly different disciplines – multiple physics and multiphysics – are needed for semiconductor design. How are they different? Why the need now? Swinnen: Multiple physics refers to the sheer breadth of physics that is now needed to analyze from the IC up to the largest system whereas multiphysics refers to the capability to analyze several physical effects concurrently, accounting for their impact on the design and interactions between various physics. Multiphysics are necessary to analyze the full context of the system environment – from nanometers to kilometers – for multi-chip packaging, chip-to-package-to-silicon and systems with multi-domain guidance. Goldman: A self-driving car, as an illustration, includes AI systems-on-chip, solid-state sensors, infotainment systems and radar/lidar detectors that must all work in the rain, the heat and the bitter cold. Smith: Why are design groups being reorganized to include expertise in mechanical and electromagnetic issues? Swinnen: Complexity has exploded, driven by a long list of technical requirements and, perhaps, mischaracterization. Goldman: Just consider the system on chip, mischaracterized by the semiconductor industry. The chip is never a system by itself. Rather, it is a complex component in a larger system and must be analyzed in that context. 3D IC is where this comes together and forces a recognition of physics outside the traditional scope of SoC design. 3D IC chips are much closer together on the board and it takes multiphysics embedded into the workflow of semiconductor design, packaging, system design and 3D IC to ensure they work reliably and efficiently. Smith: What is the solution? Goldman: It’s clear a specialized digital thread is necessary to move disparate groups with expertise in systems, physics and silicon together. Today, these groups or disciplines might not exist in the same company, whether it be a foundry, fabless or outsourced semiconductor assembly and test (OSAT) company. Lee: In order to unify the entire system design environment, a cloud-based, open and extensible heterogenous enterprise compute platform is required. It is similar to the SaaS-based business model and known as Simulation-as-a-Service (also SaaS). While vertical integration of design groups is already taking place at leading system design houses, there have also been advances in electronic design tools. These are starting to offer more comprehensive multiphysics capabilities including thermal, fluid dynamics (CFD), mechanical stress and reliability analysis in a single analysis cockpit. Today’s system designers face two platform challenges: First, they need an environment that is open enough to accept analysis results from multiple sources so that they can be overlapped and cross-analyzed. Second, the design platform must have the capacity to handle the enormous amounts of data generated by the latest 3-nanometer chips and 3D IC systems, and this implies an intimate coupling to elastic cloud computing. The days of an engineer writing Perl scripts and handing it off to someone else are gone. We believe that the industry is responding to this challenge with a new generation of design platforms that a cloud-native, open and extensible to allow heterogenous enterprise design. We are definitely at an inflection point in electronic design today, but the electronic industry has faced these before an we are confident it will master these challenges as well. About Rich Goldman Rich Goldman is director of marketing for the Electronics and Semiconductor Business Unit of Ansys. He holds a Bachelor of Science degree from Syracuse University and an MBA and Master of Science degree in Engineering Management. Moscow Institute of Electronic Technology (MIET)’s first honorary professor, he is also the recipient of honorary PhD degrees from Russian-Armenian (Slavnoic) University and State Engineering University of Armenia for contributions to the advancement of Armenia’s high-tech education and economic ecosystem. Rich served on EDAC’s board of directors. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University. About Marc Swinnen Marc Swinnen is director of product marketing for the Electronics and Semiconductor Division of Ansys. He holds Master degrees in Electronic Engineering and Industrial Management from KU Leuven, Belgium, as well as an MBA from San Jose State University. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

In a recent panel discussion, CARIAD SE, a Volkswagen Group company, Entegris, and SEMI shared their perspectives on how the automaker and other members of the automotive electronics ecosystem can collaborate to address new challenges facing the automotive industry.

U.S. consumers are flush with cash, the American economy is hurtling back from the depths of the COVID-19 pandemic, and the semiconductor industry is flying high on skyrocketing chip demand, with chip equities soaring since the initial outbreak in early 2020 as virus outbreaks worldwide supercharged demand for the digitization of everything from factories to home offices. “Wow, what a difference a year makes,” said Jennie Raubacher, Global Head of Semiconductor Electronics Investment Banking at Wells Fargo, speaking at a recent SEMI webinar. The two rounds of government stimulus payments in 2020 and 2021 gave many U.S. households the safety net to withstand the heaviest blows dealt by the COVID-19 pandemic and stoked consumer spending that has helped lift a hobbled economy. Durable goods spending in the U.S. has also seen a sharp rebound, surging more than 60% from its April 2020 trough, Raubacher said. The twin forces have driven a blistering U.S. economic recovery after GDP shrunk about 10% by the second quarter of 2020 only to bounce back in the first quarter of this year to roughly $19 trillion, regaining the lost ground to match the GDP charted at the end of 2019. With the U.S. economy continuing to gain steam, inflation has, as expected, edged higher, with price increases particularly acute in used vehicle and lumber markets. Despite surging prices, Wells Fargo sees inflation moderating as durable goods demand slows, easing pressure on interest rates, Raubacher said. Equity Valuations at Record Highs Heady semiconductor stock prices are not new. Over the past 15 years, equity prices of chip companies in the S P 500 have grown more than 460%, outpacing the 230% jump in value of the S P 500 index overall, Raubacher said. And chip stocks continue to shine. Since early 2020, when the spread of COVID-19 hit its rapid clip, the recognition of the growing importance of chips to economies around the world has exploded. That dynamic joined secular technology trends including autonomous driving development, industrial and factory automation, 5G infrastructure buildouts, data center expansions, and smart city and smart home innovation fueled by the Internet of Things (IoT) as key drivers of semiconductor stock valuations. With its price/earnings (PE) ratio now at more than 21x, the S P 500 is well above its historical average of 15x PE. “The S P 500 valuation is at record high any way you look at it, and valuation multiples across the board, currently at 3x Next Twelve Months revenue, have increased dramatically from historical averages,” Raubacher said. Semiconductor stock valuations are on similar trajectory, with the SOXX index now at 15x Next Twelve Months EBITDA (earnings before interest, taxes, depreciation and amortization). “While semiconductor stocks may seem highly valued compared to historical levels, the chip industry has grown faster and expanded profitability by a wider margin than S P 500 companies,” Raubacher said. With that differential, “semiconductor equities are not as expensive as they may seem at first glance.” Earnings expansion and valuation multiple increases for the chip industry over the past 15 years have translated into a more than 500% jump in market capitalization, compared to a 300% increase for the S P 500 excluding chip companies, she said. Chip company revenue growth in the first quarter of 2021 was predictably low due to seasonality, dipping 2.4%, though dropped less than the historical average, Raubacher said. Second-quarter revenue growth for the industry is expected to hew to the historical average of 6%. Semiconductor growth forecasts by market analysts for 2021 range widely from 6% to 17% year-over-year, she added. Chip Companies Raise Capital at Record Pace In 2020 and 2021, semiconductor companies have raised an unprecedented $82 billion in capital to finance maturing debt and acquisitions, a wave that will “likely catalyze further consolidation in the sector,” Raubacher said. None of the financing has stemmed from liquidity crunches. Since Raubacher joined Wells Fargo 10 years ago to lead its semiconductor practice, the group has executed more than 175 transactions including $40 billion in mergers and acquisitions and $360 billion of financing for its semiconductor industry clients. “With a strong macroeconomic backdrop and demand environment, relatively low interest rates, semiconductor companies showing strong business fundamentals and robust valuations, we expect a pickup in M A activity,” she said. Growth Forecast Across Most Semiconductor Applications The next four years will see the chip industry grow across most applications including wireless communications, consumer electronics, transportation and medical. Automotive and industrial/aerospace will lead the way, expanding at an expected compounded annual growth rate of 14% and 10%, respectively, from 2020 to 2025 to “drive a significant portion of the TAM expansion during that period,” Raubacher said. Across all applications, the semiconductor industry is expected to grow at a 6.8% CAGR from 2020 through 2025, adding $183 billion in revenue by the end of the forecast period, she said. ESG Rises in Importance For their part, investors now focus on more than pure business performance when valuing individual companies. The ability of businesses to reduce their carbon footprint, promote workplace diversity and take other steps to serve the greater good as part of Environmental, Social and Governance (ESG) programs are carrying more weight in valuation models. “Investors are paying more and more attention to ESG initiatives and targets,” Raubacher said. “On the debt side, we’re seeing things like green bonds and interest rate reductions tied to ESG targets. Only a few semiconductor companies have incorporated ESG measures into their financing, so it’s still early days. It really comes down to the metrics you can track in your companies and the goals and targets you can commit to. It will be a very company-specific approach rather than an industry standard.” In the chip industry, Raubacher noted that ESG targets are geared not only to manufacturing equipment and processes in fabs and other semiconductor facilities throughout the supply chain, but increasingly also to chips themselves. As technology innovation continues to spur the development of chips to power more electronics for consumers and businesses, their proliferation comes at a cost: greater energy consumption. The upshot is that semiconductor makers are becoming more focused than ever on power-efficient designs to bolster their ESG initiatives, Raubacher said. Many semiconductor players across the supply chain are reducing their carbon footprint by switching to energy-saving equipment and reducing water waste, Raubacher said. At the same time, more semiconductor executives are recognizing the rising importance of highlighting corporate achievements across all aspects of ESG. More Governments See Vital Importance of Semiconductors As shelter-in-place orders took hold in countries worldwide after the initial COVID-19 outbreak, work-from-home offices, online shopping, virtual classes and remote doctor’s visits became the norm. The electronics at the heart of this connectivity – born of both necessity and convenience – and the chips that power them took on outsized importance around the world. Geopolitical skirmishes intensified and supply chains across the semiconductor industry were reimagined and redrawn. Governments jockeyed for advantage in the race to build new semiconductor manufacturing facilities and upped their chip investments. An acute chip shortage that started in the automotive industry and quickly spread to other sectors magnified just how pervasive and vital semiconductors had become in making the world go round. “There’s no question that the semiconductor industry is vitally important to global and national economies as governments around the world now recognize its strategic importance,” Raubacher said. That puts the industry in an even stronger position to help lay the regulatory groundwork for its own future. “There’s a unique opportunity for semiconductor industry executives to shape the public policies that could impact the direction of the industry for the next 30 years,” she said. More than 750 people attended the June 2nd webinar, Surging Chip Demand, Digital Transformation, and the Pandemic – What’s Next?, sponsored by SEMI members Brooks Automation, Hitachi, JECT, KLA and TEL. Sven Smit of McKinsey Company also delivered his talk Leading in COVID-19 Exit at the event.

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected with me for a discussion about the chip design verification space. As he pointed out, verification and validation of systems is a fast-growing and important market segment to the electronic system design ecosystem. Smith: What trends do you see in chip design? What is driving these trends? Brunet: Chip verification costs continue to grow faster than design costs because of factors such as increasing design complexity, rising computing power, surging I/O traffic activity, increasing energy consumption and the widespread use of peripherals. These dynamics are being driven by new data center networking, communications/5G, autonomous driving, artificial intelligence (AI) and machine learning (ML), and storage applications. These trends also indicate the need for more powerful verification tools and expanded verification objectives that include power and performance analysis. Hardware-assisted verification tools are perfect for meeting these demands. Smith: Chip design verification consumes the most time in a project cycle. Why is this so? Brunet: The verification of designs reaching multi-billion gates and supported by voluminous software stacks is fraught with challenges. To exhaustively check every possible state in a billion-gate design with simulation alone would require up to trillions of verification cycles. That’s why hardware-assisted verification is one of the fastest-growing technologies in EDA. Given the complexity of today’s SoC design, it’s no surprise that verification is the largest undertaking in the entire project design cycle, consuming more than 50% of it. It also has the greatest impact on quality, cost and schedule because it prevents designs from failing at first silicon. While a respin of a large design taped out at a node below 10 nanometers could cost more than $10 million, delaying delivery of a new product for a few months in a highly competitive market may cost hundreds of millions of dollars. Smith: What other challenges do engineers face trying to verify a chip design will work as intended? Brunet: Verifying an SoC design is a massive undertaking and, in parallel, verification teams are trying to streamline and optimize verification cycles. SoC design groups are tasked with completing full system-level verification prior to creating production masks by thoroughly vetting all hardware blocks, interactions between those blocks, and the software developed for the end application before the chip is built. To alleviate this enormous pressure, they are starting to adopt a shift-left methodology for early functional verification as soon as individual blocks of a SoC design become available. It helps jump-start embedded software validation before full system validation is completed to save time and allow engineers to work in parallel, not serially. While it is an effective approach, it creates the need for a complete and integrated suite of hardware-assisted verification tools to verify and validate a design’s hardware and software components. Smith: How do you define hardware-assisted verification and how does it help solve these challenges? Brunet: A typical definition of hardware-assisted verification is special purpose hardware to accelerate verification. In other words, hardware emulation and FPGA prototyping. Hardware-assisted verification is a mandatory investment as single-die or multi-die chips get larger with more complexity and more interfaces, making hardware and software code integration critical early in the design cycle. Because software performance defines a chip’s success, the need to perform software workload-based analysis is acute, not just analysis of chip functionality, but also accurate performance and power consumption in the context of real-world applications. Hardware-assisted verification is the only option when hardware and software meet. By combining emulation, desktop FPGA prototyping boards and enterprise FPGA prototyping platforms to work on the same SoC design, a verification group can assemble a complete hardware-assisted verification system for thorough and exhaustive verification and validation. Smith: Where are the big opportunities for hardware-assisted verification? Brunet: New end-user applications are coming from computing and storage, AI/ML, 5G, networking and automotive. Recently released market data from the ESD Alliance shows that in 2020, hardware-assisted verification revenues exceeded $700 million. It is reasonable to assume that revenues of $1 billion will be within reach in the next few years given the amount of chip design activity at advanced nodes below 10nm. Smith: With the design/verification and manufacturing phases of the semiconductor supply chain more closely aligning, what role does hardware-assisted verification play? Brunet: Semiconductor manufacturing and the supply chain that supports it benefits greatly from the continued innovation in verification and validation tools and methodologies. With this innovation, designs are delivered to the manufacturing flow with a much greater chance of passing first silicon with success. This reduces friction in the semiconductor supply chain since IP and chips are available when anticipated. Hardware-assisted verification is a quick-moving, highly leveraged resource that helps a design and verification team to ensure chips are manufacturable and meet the functionality, power and performance requirements for the end-product application. Jean-Marie Brunet is the senior director of product management and engineering for the Scalable Verification Solutions Division at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron, among other companies. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at [email protected]. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.