ASML

Europe is facing an acute shortage of skilled microelectronics workers that undermines the growth potential of not only the electronics industry but the European economy as a whole. Nearly 1.1 million job advertisements for electro-engineering workers were placed in the EU between mid-2018 and the end of 2019 (CEDEFOP, 2020). The shortfall looms large as a skilled and diverse workforce that can continuously innovate is the oxygen of microelectronics. In light of the critical importance of microelectronics to Europe’s ability to fulfill its growth potential, SEMI Europe participated in the high-level roundtable hosted by Commissioner Nicolas Schmit and Commissioner Thierry Breton on October 5. The discussion’s key takeaway: The skills challenge facing the microelectronics industry is too complex for one organization to tackle, and reskilling and upskilling its workforce should be a common priority for Europe. Only with a diverse, substantial and skilled microelectronics workforce can Europe achieve its R D, design and manufacturing ambitions while ensuring its sovereignty in the digital age. The roundtable highlighted the EU Pact for Skills as a key means to narrow the industry’s skills gap.An ever-growing part of our lives, microelectronics, with their ability to run billions of computations per second and store vast quantities of data, are the brains of modern technology. The digital sovereignty of nations around the world today relies on advanced microprocessors to collect, transfer, analyze and store immense amounts of data used in key end-user sectors such as mobility, telecommunications, energy, security and healthcare. Information and communication technologies (ICT) enabled by microelectronics are helping much of the world’s population to work and study from home and remain safe during the COVID-19 pandemic.According to the Smarter2030 Report, further deployment of ICT, including electronic components in critical sectors such as transportation, manufacturing, agriculture, construction and energy, could eliminate the equivalent of 12.1 billion tons of CO2 per year globally. These are some of the reasons why nations worldwide are making large-scale investments to advance a homegrown microelectronics R D, design and manufacturing base. It is no surprise, then, that semiconductors are now at the center of the so-called global techno-trade wars.Clearly, Europe urgently needs to mobilize and pool resources to develop effective lifelong learning programs for all workers and continue investing in microelectronics innovation. We need to instill the passion for creating technology among current and future workforce, in particular women and people with challenged backgrounds, and build a highly diverse talent pool. Working together, we can better demonstrate how computing technologies, including quantum, high-performance and edge AI, provide solutions to grand societal challenges and attract talented people to the fascinating world of electronic components and systems.Against this backdrop, the microelectronics industry finds the Pact for Skills very timely and crucial to advancing the talent pool underpinning Europe’s deep digital ecosystem. The Pact will play an instrumental role in improving the scope and the quality of training partnerships at regional, national and European levels, sharing best practices and helping the microelectronics industry and workforce adapt to the effects of COVID-19.The microelectronics industry is committed to building on the momentum created by the METIS Erasmus+ collaborative project and to mobilizing our ecosystem and education partners for a successful Pact for Skills in Microelectronics starting this year.The High-Level Roundtable: Skills for Microelectronics was hosted by Commissioner Thierry Breton and Commissioner Nicolas Schmit. Participants included Paul Boudre, CEO, SOITEC; Lars Reger, CEO Germany and CTO, NXP; Frits van Hout, Executive Vice-President and Chief Strategy Officer, ASML; Françoise Chombar, CEO, Melexis; Emmanuel Sabonnadiere, CEO, CEA-Leti; Luc Van den hove, President and CEO, imec; Sabine Nietzsche, Board member, Silicon Saxony and Vice President, GlobalFoundries; Laith Altimime, President, SEMI Europe (coordinator of METIS); Yolande Berbers, President, European Society for Engineering Education (SEFI); James Calleja, President, European Forum for Technical Vocational Education and Training (EFVET); Ludovic Voet, Confederal Secretary, European Trade Union Confederation (ETUC).Emir Demircan is director of Advocacy and Public Policy at SEMI Europe. To learn more about SEMI Europe advocacy, contact Emir at [email protected].

Like so much else these days, career mentoring in the semiconductor industry has gone virtual. And, among hiring managers, for good reason: Chip companies are facing a new urgency to hire skilled workers as recent SEMI forecasts spanning packaging materials and fab equipment spending show strong growth in 2021 – a trajectory that puts even more pressure on an industry confronted with a worker shortage to attract and recruit new talent.Enter SEMI Korea, which early this month gathered nearly 4,000 sheltered-in-place South Korea university students to offer tips from semiconductor industry insiders on how to kick-start their careers in the chip business. In 14 sessions over three days, industry powerhouses offered guidance across topics ranging from educational preparation and job skills to resume writing and interviewing. Like last year’s on-site event, students from Seoul accounted for the bulk of those online for Campus Outreach On-Air. But this year saw a far higher turnout of students in provincial cities thanks to the ease and convenience of virtual communications – a silver lining in the age of COVID-19.Establishing a successful career in the semiconductor industry starts with a mix of soft and hard skills, according to Changjin Kang, CEO of SEMES, one of the top 10 global semiconductor equipment companies. Keynoting the event, Kang pointed to six key attributes in particular – caring, resilience, execution, analysis, tenacity and experience – under the acronym C.R.E.A.T.E.Caring means empathy for colleagues, understanding their unique work environment and challenges, and building strong relationships. To help cope with the stress that can come with working in the industry, workers must be also be resilient by managing the emotional demands of a job and getting enough rest. Execution comes down to thorough, methodical planning. Carefully analyzing information to make data-driven decisions is a critical aspect of successful outcomes, while having the tenacity to push through difficult technical challenges helps engineers develop the right solutions. And getting out from behind the desk to learn from colleagues is important in building experience.Human resources representatives and engineers from Applied Materials, ASML, Dongjin Semichem, EO Technics, Jusung Engineering, KLA, Lam Research, Merck KGaA, Darmstadt, Germany, PSK, SEMES, SK Siltron, TEL and Wonik IPS shared with the students the key competencies needed to forge a career in the semiconductor industry. Engineers pointed to the benefits of improving their English skills through language training and continuing their education by pursuing engineering certificates. Human resources representatives stressed the importance of a global mindset since, as part of the global semiconductor ecosystem, engineers and other staff often communicate via conference calls with colleagues around the world.In a post-event survey, the students – all digital natives – awarded the event 4.3 out of 5 points for overall satisfaction and made clear that they prefer online Campus Outreach to the on-site event.“Thanks to SEMI and the companies for providing a great opportunity to meet experts and HR managers,” one student pointed out in the survey. “It was very useful because it opened up opportunities for many students to communicate with semiconductor companies.”“It was nice to know what works semiconductor engineers do,” said another, “and how as university students they prepared for employment.”SEMI Korea thanks the nine semiconductor companies that sponsored Campus Outreach On-Air to help build the industry’s talent pipeline and the students for their invaluable participation.Jaegwan Shim is a marketing specialist at SEMI Korea.

Japan’s semiconductor industry has weathered the COVID-19 pandemic to post robust growth. Far from a temporary setback, COVID-19 will lead to enduring change in how we work and live. And just as automation has been a bulwark against the devastating business impacts of the virus outbreak, increasing digitization will lead to new efficiencies in our industry.These were some of the key takeaways from three SEMI Japan Members Day webinars in June and July that offered the latest updates on COVID-19 impacts to the semiconductor industry and restart strategies for SEMI members. More than 2,000 SEMI members across Japan’s islands attended the webinars featuring the following five speakers: Hideki Kanewaka, Marketing Director, Consulting Lead, Japan, Accenture Japan Ltd. Takayuki Komori, Manager, Marketing Engineering Dept, SUMCO Corporation Taketoshi Hamaguchi, Director, Manufacturing Industry, Microsoft Corporation Akira Minamikawa, Senior Consulting Director, OMDIA (Informa Intelligence LCC) Yuichi Koshiba, Managing Director Partner, Boston Consulting Group COVID-19 Impact on Japan Semiconductor Industry is ModestThe consensus view of the five speakers from various quarters of the industry – consultant, IT service provider, materials supplier, market analyst – was that the Japan semiconductor industry withstood the heavy blows COVID-19 dealt to other industries thanks to strong demand for chips. Shelter-in-place policies and lockdowns spawned by COVID-19 has accelerated the digital transformation rippling around the world as electronics sales have soared to support everything from remote work and education to healthcare and home entertainment including gaming.The rapid growth of cloud usage for video streaming, gaming and remote work is taxing communications network capacity and placing more bandwidth demands on servers, said Akira Minamikawa of OMDIA. According to a recent report by Nokia, communications network traffic has skyrocketed 300 percent for online meetings and 400 percent for gaming, bringing the networks closer to their capacity limits. Minamikawa sees server shipments increasing at 8 percent CAGR through 2024. For the broader chip market, he expects demand for notebooks, solid state and hard disk drives, and gaming to remain strong in 2020. He also predicts rapid 5G penetration for smartphones will boost semiconductor chip industry growth.Still, not all semiconductor segments are expanding, said Yuichi Koshiba of Boston Consulting Group. Chip shipments for end products in markets such as automotive, industrial equipment and aircrafts are on the decline. Slowing demand for chips that power automotive applications in particular could pare sales for some chip companies and distributors since the segment accounts for a high proportion of their overall revenue.State of the Semiconductor IndustryFrom SUMCO’s vantagepoint as a major silicon wafer supplier, the company’s Takayuki Komori sees a number of changes unfolding in the semiconductor industry: Smartphones are driving growing demand for process technology (smaller nodes) and 300mm wafers. Komori estimates the typical high-end smartphone sports 1,700 square millimeters of silicon. 300mm wafers account for 80 percent of that total while more than 50 percent of the devices use leading edge multi-patterning technologies. Smartphones will need more RF chips to support 5G’s high-speed communications and added frequency ranges. Substrates for RF switches and tuners have been shifting from gallium arsenide (GaAs) and other compound semiconductors to silicon. 5G smartphone penetration will accelerate as the cost of integrating CPUs and modem functions into a single chip sees a swift decline. While the sensitivity and resolution of CMOS image sensors have evolved to incorporate innovative backside illumination and stacking technologies, future advances will focus more on products for machine vision applications capable of sensing invisible light bands. Rising adoption of electric vehicles and robotics applications will drive growing demand for power semiconductors that control their motors such as IGBTs and MOSFETs as the production capacity for the devices expands and shifts to 300mm wafer lines. For memory fabs, Minamikawa said utilization remains high as a result of a spending slowdown by major chip manufacturers and will stay elevated even once additional capacity ramps to support robust demand. Foundry fab utilization also remains high despite the pandemic-driven cancellation of smartphone chip orders in March. Minamikawa also sees the utilization rate of micro rising with the surge in demand for notebooks, PCs and servers in the second half of 2020.Transition to New NormalAs people around the world start to settle into new ways of living and working, there’s a growing acceptance that the transformation will be long-lasting. And no area of people’s lives is changing more than their work. Boosted by government subsidies, many small and midsize companies in Japan have started to implement work-from-home policies, an area where major electronics and IT businesses had already instituted reforms, said Hideki Kanewaka of Accenture. A few examples: Nippon Telegraph and Telephone Corporation (NTT) announced that half of its employees will continue to work from home in the future. A five-year plan Toshiba launched in 2019 to allow all employees to work from home will likely accelerate. Hitachi plans to allow all employees to work from home starting in April 2021. dwango, a major internet-based entertainment company in Japan, announced it will allow in principle any employees to work remotely. In the critical area of remote sales, Kanewaka pointed to the importance of going beyond online business meetings, paperless transactions and virtual events to devise new ways to attract customers and close deals. Creating online communities and providing rich digital content are also important measures to consider, he said.Manufacturing's Digital TransformationTravel restrictions by most countries to curb the COVID-19 outbreak have also raised barriers to chip companies sending engineers overseas sites to service state-of-art equipment and provide other technical support. Microsoft’s remote assist system deployed by ASML is one tool semiconductor makers can use to overcome this challenge, said Taketoshi Hamaguchi of Microsoft.The system connects a remote equipment service expert with an onsite worker through the internet, allowing the technical expert to provide support through a goggle display with a camera worn by the worker. Guided by the expert, the worker can perform complex services. A Natural User Interface (NUI) helps give the factory worker a clear understanding of the often highly technical instructions.Using artificial intelligence (AI) to increase automation will also help reduce the reliance of semiconductor factories on onsite workers. For example, AI deep learning can be deployed to calibrate equipment autonomously and reduce downtime after scheduled maintenances, Hamaguchi said.Corporate Restart Strategies Beyond factory considerations tied to COVID-19, semiconductor companies will need to adapt their business strategies to new ways of operating. For example, global supply chains will shift to domestic sources and increase redundancy to ensure a steady supply, a change leading to higher overall costs, Koshiba said. Trade routes among regions will also be redrawn as the trade rift between the United States and China and other geopolitical tensions intensify. The total value of those routes is expected to recover by 2023.Koshiba advised companies to evaluate the supply chain trade-offs between stability and cost and factor in potential risks to improve their short-term resilience and drive mid- to long-term supply chain restructuring.After past recessions, 14 percent of companies restored sales growth, Koshiba said. He recommended investing aggressively in growth and seizing M A opportunities during the downturn. Chip companies must also adapt to supply chain changes faster than competitors.Become a SEMI MemberWebinars like the recent SEMI Japan Members Day series have become increasingly important in the mix of programs and services SEMI offers members to help them connect, collaborate and innovate in the microelectronics community. To become a SEMI member, please visit the SEMI website or contact your nearest SEMI office.Jim Hamajima is president of SEMI Japan.

What’s next for smarter, more connected electronics manufacturing - Part 3 The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco. While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development. “People don’t think of research and development as the first place to automate, but it’s where applying our digitization and simulation has first had impact,” says David Fried, Coventor vice president of Computational Products. He noted that insertion is easier in the lab than in the fab. Technology at 10nm and beyond is now so complex that companies at the leading edge must use process modeling to understand the effect of process variation on their designs. Learning cycles can now be accelerated during development by simulating 10,000 digital wafers instead of running 25 actual wafers during screening, Fried says. Applying structured analysis and machine learning to the data simplifies optimization across the 500 or more interrelated process steps. Coventor has recently introduced a statistical analysis package that aids the design and analysis of process variation experiments by using large volumes of data from its models. Fried says these models are next being used to accelerate the yield ramp in manufacturing. Digital simulation also could speed development of high-mix, lower value products While digital twins are best known for their use in complex, high value products like jet engines, the simulation technology could also enable the electronic manufacturing services (EMS) sector to reduce the time, cost and risk of developing its high mix of products. “The EMS sector’s use of digital twins will be vital for it to smooth the move of CAD/CAM digital design data for so many different products into manufacturing, and to accelerate validation testing of designs and products by doing more of it in the virtual world,” says Dan Gamota, vice president of Engineering and Technical Services at Jabil. Gamota also highlights the push for traceability from the automotive and healthcare markets, where the digital models could be used to quickly assure that the design was built exactly as specified. “In the past year, traceability has evolved from just ‘nice to have’ to ‘how to achieve,’” he adds. “Companies are expecting it, but aren’t willing to accept the cost and risk of doing it alone. We need the community to discuss realistic implementations, identify the most critical elements and bring together the ecosystem partners to build baseline reference architectures for key digital building blocks. The community also needs to assure the reliable flow of data among the electronic manufacturing segments from semiconductor to OSAT to EMS.” Predictive maintenance and virtual metrology applications could mature in next few years While predictive maintenance initially seemed a likely early application of machine learning in factories, it remains a challenge for the electronics sector. “The difficulty is that it’s not clear where to get the most bang for the buck,” says Tom Ho, president of BISTel America, noting that it may make the most sense to track the failure performance of a single expensive part, like an electrostatic chuck, since predicting the failure performance of a whole complex system like an etcher is much harder. “Collecting enough data from all failure types, including especially the rare events, is difficult unless you have a long history of a lot of tools,” adds Doug Suerich, PEER Group product evangelist. “The gain from collecting performance information from many tools across the industry could be big, but many companies still need to overcome concerns around exposing their IP.” Another big opportunity for prediction is virtual metrology – predicting the wafer outcome from the process or sensor data with enough accuracy to replace the physical metrology. “Virtual metrology is improving, and since metrology can be slow and expensive, any reduction could mean a huge potential savings,” says Suerich. “But it is still seen as too scary for many companies. Two to three years from now, companies will expand the practice from lower risk areas into processes that require more confidence in the results.” Moving beyond prediction to automated control needs digital models Once the results are predicted, the model can be used to control or automatically optimize a process and enable the system to learn by itself, usually by reinforcement learning on a digital model. The model can then independently make adjustments to optimize the manufacturing process. “Automated process development is getting close now. Instead of smart guys turning the knobs, deep learning is automating the smart tuning,” says Suerich, suggesting the industry could see widespread adoption in as little as two to three years. This type of machine learning needs a good digital model, and masses of data for learning. One approach uses human experts to build a physics-based model of the clearly understood parts of the process, then turns to deep machine learning to optimize the lesser-understood variables. The alternative, the data-first approach, runs a computer algorithm to suggest the solution purely from data, without human input, and then relies on the human to evaluate the usefulness of the results. Modeling digital twins of wafers could enable automated process control, chamber matching, and fleet matching, says Fried. If every wafer had its own virtual twin with all the upstream metrology and structural information needed to make equipment control decisions, it could feed forward that information to enable the seamless transition from one step in the process to another based on understanding their complex interrelationships. This could potentially improve uniformity across wafers and equipment, and reduce the need for metrology, he argues. Moving metrology sensors into the chamber will also require model-based algorithms to enable dynamic process control in close to real time, says Fried. These algorithms will be needed to acquire, parse, and process the data at high speed, and then to choose how to adjust the controls. “There will be a model behind collecting and interpreting the metrology data,” he notes. “That’s a really rich vein for improvements in process control.” “The end goal is to collect equipment data in real time, analyze it with AI, and send back controls to optimize manufacturing processes,” Jabil’s Gamota says. “This requires a robust architecture for communication between equipment and consistent formats for data collection and analysis. But the cost and complexity of this heavy lifting is too great for any one company to do alone. We need a consensus-based architecture for ingesting, analyzing and acting on the data.” SEMI tests data transfer protocols, benchmarks best practices SEMI is launching a smart data project to identify the various data transfer protocols needed for inter-company communications. The project will feature a proof-of-concept model in a development fab to produce verifiable results so SEMI can better understand how different approaches meet member needs. SEMI’s smart manufacturing technology communities and the Fab Owners Alliance are also benchmarking current smart manufacturing practices in the microelectronics industry to help SEMI members better understand the path forward and potential return on investment. Speakers over all three days at SEMICON West addressing these issues include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org. What’s next for smarter, more connected electronics manufacturing - Part 1 What’s next for smarter, more connected electronics manufacturing - Part 2 Paula Doe, SEMI

What’s next for smarter, more connected electronics manufacturing - Part 2The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.” Process complexity drives demand for feed-forward between silos with computational models ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized. “We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says. So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,” notes Niesing. Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 1What’s next for smarter, more connected electronics manufacturing - Part 3Paul Doe, SEMI

What’s next for smarter, more connected electronics manufacturing - Part 1The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI expands its smart manufacturing program with a Smart Manufacturing Pavilion with displays and three full days of talks to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.Autonomous autos’ demand for zero-defect systems and 100 percent traceability back to the manufacturing data for each die is driving a push to traceability across the chip sector. “Far more chips are being used by the automotive sector, and its very different requirements are driving demand for traceability,” says Tom Ho, president of BISTel America. “Our chipmaker customers are looking for traceability solutions and the trend is the same in backend packaging and assembly – automotive applications are driving the sector to traceability.”Traceability is also driven by the growth of systems in a package as fabless chipmakers look to connect back to the packaging companies’ fault analysis labs and die interconnect history to diagnose and fix the cases where known-good die are failing in the system, adds Mike Plisinski, CEO of Rudolph Technologies. Plisinski adds that makers of consumer products like phones that can also see harsh conditions are demanding higher quality and traceability as well. The electronic manufacturing services (EMS) sector also must establish an architecture for traceability to collect critical manufacturing-related data and to interface with OSATs and semiconductor fabs. The reason is that EMS companies are adding traditional OSAT processes such as assembly of products with bare die and complex optics modules requiring clean rooms. “A unified sand-to-smart-phone smart manufacturing roadmap should be established,” says Dan Gamota, vice president of Engineering and Technology Services at Jabil. “We need to identify protocols for manufacturing data communications that can be adopted across the supply chain.”To enable smart manufacturing, vendors need to collaborate on getting their production equipment to interoperate and support factory analytics and data management systems. Source: SEMI One big challenge, of course, is how to format this diverse data so it can be linked and used by various supply chain stakeholders. “Smart data needs to be contextual and it needs data standards across the supply chain so it’s easy to link from the front end to the back end, follow common lot IDs front and back end, and have a way to map streaming data from sensors to a discrete lot ID,” notes Ho. New approaches to metrology, analysis and test that increasingly exploit machine learning on simulations will also be needed to help predict which die and connections that test well now may fail in the future as conditions change.Another issue is how to securely share the needed data across companies without jeopardizing IP. “On the equipment side we collect data across customers on how the tool is running to improve the equipment,” notes Neal Callan, ASML VP Silicon Valley. “Next we need to integrate performance and reliability data that today is not as well shared.”The other big hurdle is how to pay for data sharing. “The challenge is that the final manufacturers reap the benefit of traceability, but since they expect their suppliers to deliver good die, they don’t want to pay more for it,” notes Plisinski. He suggests that over the next two to three years, traceability and predictive fault prevention will become the norm as the automotive sector is compelled to invest in it to assure safety. Meanwhile, fabless companies will face so much complexity in integrating different die from different suppliers in SiP that they will no longer be able to afford to simply use the cheapest supplier, potentially driving a fundamental shift in relations and division of labor among fabless chipmakers, OSATs and fabs. Standards extend across supply chainSEMI member committees are collaborating to build the infrastructure to enable these developments. Standards committees are updating standards for higher bandwidth data exchange and extending semiconductor-like vertical and two-way horizontal equipment communication standards to flow shops to enable assembly players to optimize and trace back results across players. The SMT/PCBA community is integrating its smart manufacturing work into SEMI standards, and the SEMI A1 standard was a key reference document in the development of the Japan Robotics Association’s Equipment Link Protocol.Speakers addressing these issues at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 2What’s next for smarter, more connected electronics manufacturing - Part 3Paula Doe, SEMI

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Diverging viewpoints on EUVL readiness for 5nmMike Lercel, Director of Strategic Marketing at ASMLASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of AmericaRenwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers' public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i's better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it's too early to say.Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It's unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIESLevinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.” Mask development for 5nmChristopher C. Progler, CTO Strategic Planning at PhotronicsProgler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.” More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.” Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; SOURCE: GLOBALFOUNDRIES Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.” How does the industry get to 3nm? ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame. Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. "We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.Debra Vogler, SEMI