microelectronics

“Virtual platform environments that combine the verification capabilities of emulation with the pre-silicon functionality insights available through verification intellectual property (VIP) are an increasingly popular way to get designs verified ahead of the curve of new standards,” Browy says.

Semiconductor device manufacturers are focusing on new sensing technologies that can increase wafer throughput, reduce downtime, boost yields and drive other production efficiencies by collecting data that provides insights not previously identified.

As part of bi-weekly meetings of the SEMI Environment, Health, Safety and Sustainability (EHSS) community to share information on the impacts of the pandemic, the EHSS COVID-19 Working Group recently revealed that companies are offering PTO to employees to get vaccinated.

Dr. Lanza, Managing Partner of Lanza techVentures and 2014 winner of the Phil Kaufman Award for Distinguished Contributions to Electronic System Design, addresses why he believes semiconductors in MedTech is about to become the next big thing.

SEMICON Europa, SEMICON West, SEMICON Japan, & SEMICON Taiwan welcome back exhibitors and visitors to show floors starting in mid-November as four of SEMI’s seven flagship events gather visionaries and industry leaders to explore the latest semiconductor trends and innovations by the end of 2021.

Demand for hi-tech manufactured goods is at an all-time high and is expected to grow significantly in our new digital age, COVID-19 economy. This is especially true for semiconductor chips. Chip manufacturers have been working to meet this demand by building new factories and by optimizing processes and equipment in existing fabs. While there is much media coverage about new factories planned by leading-edge chipmakers and government investments in the semiconductor sector, greenfield fabs entail significant capital expenditures and are sometimes fraught with complex political concerns. As a result, they can take several years to complete and reach their planned production capacity. Instead, the semiconductor industry needs to optimize existing factories in order to increase productivity and yield and meet growing demand by implementing smart manufacturing solutions. Smart manufacturing solutions will inherently reduce costs with more efficient and automated processes, and those savings can be reinvested for the next wave of solutions. Chip Industry on the Bleeding Edge Semiconductor manufacturers have always been focused on bleeding-edge technology to outflank strong competition and build the best products – faster and cheaper. Today, pioneering organizations are using data to optimize manufacturing processes and equipment, a practice known as Smart Manufacturing. While there are many definitions of Smart Manufacturing, the essence is maximizing the utility of big data generated in these factories by leveraging three pillars: Sensing, Connecting, and Predicting. It is not just the digitization in manufacturing, but it is also about turning the data into actions that generate value – an effort the SEMI Smart Manufacturing Committee is driving based on the three pillars. Optimizing return on investment is the ultimate goal. SEMI Smart Manufacturing Initiative activity is based on three pillars that support the goal of increasing ROI. Making the Right Decision, Faster Smart manufacturing practices enable organizations to make the right decisions and take action faster based on insights generated from real-time and historical data. This requires data management technologies and applications that can process, analyze, and act on information instantly. It has become ever more difficult to process and discern the relevant data or signal from the vast volume of data, perform analytics or develop new ML or AI analytic tools, and then make the critical decisions to solve problems as close to real-time as possible. Who’s Responsible – IT or OT? In the past IT (Information Technology) and OT (Operations Technology) were separate entities within organizations, with IT focused on storing large amounts of data for enterprise systems and OT concentrated on using data to perform specific functions. Smart Manufacturing often demands combining IT and OT, difficult in rigid organizations that operate the two organizations independently and lack the infrastructure to implement comprehensive solutions. Success requires executive leadership sponsorship, motivated technical personnel and, most importantly, a clear deliverable on the value in implementing Smart Manufacturing. Many organizations have introduced top-level leadership positions such as a Chief Information Officer or Chief Data and Analytics Officer to address this convergence and many of these leaders are embracing Smart Manufacturing practices. The SEMI Smart Manufacturing community includes many of these leaders and therefore has highlighted the importance in the return on investment for Smart Manufacturing solutions. Read more about IT and OT convergence and note that Smart Manufacturing is synonymous with Industry 4.0. The SEMI Smart Manufacturing Initiative covers the entire supply chain. Get Smart in Smart Manufacturing While new technologies and applications are being created to deal with mountains of data, it is the underlying methodologies and practices that are key to a successful Smart Manufacturing deployment. SEMI, the trade association representing the electronics manufacturing and design supply chain, is in a perfect position to evangelize Smart Manufacturing experiences and best practices for the entire manufacturing community. The more than 30 member companies participating in the SEMI Smart Manufacturing Initiative bring more than 500 years of collective experience and knowledge to the topic. Many segments of the supply chain participate in the SEMI Smart Manufacturing Initiative including packaging, assembly, SMT and PCB assembly, test, software, data management, sensor and material suppliers. Learn How to Manufacture Smarter SEMI SMART Manufacturing is hosting two great conferences in the coming months – the Global Smart Manufacturing Conference (GSMC) and the SEMICON West Smart Manufacturing Pavilion. As a leader of the organizing committee and chair for the SEMICON West Smart Manufacturing Pavilion, I encourage people who want to learn how to implement Smart Manufacturing or expand their knowledge of Smart Manufacturing to attend these events. The GSMC will feature keynotes highlighting the value of Smart Manufacturing, offer tutorials on the three pillars, and introduce several case studies for each of the pillars. Thirty-two organizations – ranging from global cloud providers, semiconductor factory operators, leading equipment vendors and software application solution companies – will present. See the full agenda here. The SEMICON West Smart Manufacturing Pavilion will compliment GSMC by showcasing a number of use cases that highlight the value of Smart Manufacturing. Panel discussions will deep dive into the challenges of implementing these best practices and the direction smart manufacturing is taking in the coming years. Our goal for these events is for you to take this knowledge back to your companies, implement and improve on the detailed solutions highlighted at the conferences, and return next year to share your success stories with the community. See you soon, in person or virtually! About the Author Bill Pierson is VP of Semiconductors and Manufacturing at KX, leading the growth of streaming data analytics in this vertical. Bill is also a chair for the SEMICON West Smart Manufacturing Conference and an active team member of the SEMI Americas Chapter. He has extensive experience in the semiconductor industry including previous experiences at Samsung, ASML and KLA. Bill specializes in applications, analytics, and control. He lives in Austin, Texas, and when not at work can be found on the rock-climbing cliffs or at his son’s soccer matches.

Today, AI algorithms are primarily run at large data centers-- in the cloud. For this intelligence to be used at the edge, data must be transmitted to the cloud, analyzed there, and the results transmitted back to the field of operation, such as a mobile phone, medical implant or autonomous vehicle.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.

Becoming a Certified B Corporation™ comes with many benefits, most of them extending beyond the walls of the company and into the hands of employees, community members, and industry partners. The designation makes the meticulous and rigorous process to certification well worth the endeavor. In 2021, Brewer Science announced that it’s the first company in the semiconductor industry to become a Certified B Corporation. Our journey to become a Certified B Corporation inspired us to share our top five reasons for meeting the high standards the designation sets for both environmental and social responsibility. 1. Pave a pathway for continuous improvement B Lab™, the certifying organization for B Corps, believes in continuous improvement, and B Corps must create an improvement plan to demonstrate the areas of social and environmental performance they focus on in the coming years. Brewer Science will hold B Corp certification for three years before submitting to a renewal process. In order to be recertified, a company must score higher on recertification than on the previous certification. The assessment evaluates all facets of the company, and it’s a learning process to help the company target and identify ways to improve business practices. Brewer Science has already identified improvement areas for the recertification. We’ve implemented several human resource initiatives that are not written into policy yet, such as flexible and expanded work options. Additionally, we have expanded our use of a cloud-based learning platform to provide employees with more training options and performance conversations held quarterly instead of annually. Brewer Science scored many points for community involvement and charitable giving. However, we are still expanding community engagement by supporting or donating to a new local organization each month. Brewer Science became Certified Employee-Owned in 2020, but since it was the first year of the ESOP and shares were not yet dispersed, B Lab didn’t fully recognize the program. 2. Share the values of your stakeholders In 2006, Brewer Science started externally reporting environmental, safety, and health performance every year through its annual Corporate Sustainability Report in order to be transparent with customers, suppliers, and employees. The impact of this report on all of our stakeholders motivated us to pursue other ways to promote sustainability and inclusion as a shared asset for our customers and suppliers. In 2016, Brewer Science became GreenCircle Certified Zero Waste to Landfill, an annual certification that we have achieved every year since then. Certified B Corporations are businesses that meet the highest standards of verified social and environmental performance, public transparency, and legal accountability to balance profit and purpose. The standard is highly respected standard, in part because of B Lab’s rigor with the questionnaire and certification process. Not only does becoming a B Corp show your stakeholders that you care, and that you are walking the walk, but it also allows you to show how much your company cares through your B Corp Impact Area. Brewer Science pursued the impact area of environmentally innovative manufacturing, a category that required detailed evidence of how Brewer Science manages the manufacturing waste and minimizes its carbon footprint. The B Impact Area Scores reflect the five areas where the business excels. 3. Be competitive in an industry that demands sustainability and social responsibility Sustainability is of growing importance in the semiconductor industry. A company can convey its commitment to sustainability by becoming a Certified B Corp. The B Impact Assessment requires benchmarking to other companies in the industry in areas of social concern, such as sustainability, inclusion, and diversity. While benchmarking was nearly impossible for Brewer Science since we rank high as an innovator in these areas, we were able to not only set the benchmark for ourselves, but other industry partners who pursue B Corp certification in the future through our collaboration with B Lab. 4. Connect with a community that cares Becoming a Certified B Corporation instantly opens companies up to a network of other B Corps across the world. The more than 4,000 B Corps in 150 industries and 74 countries enables makes it easy to network in the areas such as environmental initiatives, attracting top talent, and even just using business as a force for good in the semiconductor industry. Knowing that a business is actively trying to make a positive social change will help attract top talent looking to find meaning in their careers. B Corp certification validates a company’s employee-centric culture, which can help beef up employee retention. What’s more, an exclusive job posting board called B Work, sponsored in part by B Lab, helps connect job seekers with companies that share their values. Employees are connected through an exclusive B Corporation community platform, B Hive, enabling them to collaborate and share ideas with other B Corp employees. There is also a section within the B Hive where other B Corps can share benefits with other B Corp member employees. With such a diverse range of companies that are Certified B Corps, shared benefits can include anything from discounted clothing to travel deals or even free consultations. Additionally, employees of B Corporations can collaborate on local recycling events and community engagement. 5. The bottom line Companies don’t pursue the Certified B Corp designation to drive improvements to their bottom line. Yet by sharpening their focus on environmentally sustainable initiatives and diversity and inclusion, most companies could indirectly see significant return on investment. For example, having a pathway for continuous improvement, sharing the values of your stakeholders, being competitive in the industry, and connecting to clientele and employees that value social responsibility all enable your business to grow. In the long run, becoming certified as a B Corp can save a company money by giving companies access to community data that provides insights into cost-effective ways to be more sustainable. Plus, the certification process helps companies identify wasteful spending. For more information about Certified B Corporations, and to get started on your company's application, visit the Certified B Corporation website. Jessica Albright is a content marketer at Brewer Science, Inc.

As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Higher on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries are driving demand for advanced packaging technologies that address these issues but introduce challenges of their own such as efficient power delivery to all the different domains in a heterogeneous system. SEMI spoke with Kaladhar Radhakrishnan, Intel Fellow at Intel, about heterogeneous system integration trends and new developments in the semiconductor industry. Radhakrishnan shared his views ahead of his keynote at the SEMI Connecting Heterogeneous Systems Summit, 1-3 September 2021, an online event. Join the summit to meet experts from Intel and other key industry influencers. Registration is open. SEMI: What is driving the adoption of electronics and semiconductor devices nowadays and why is the development of new and innovative technologies important? Radhakrishnan: We are living in an increasingly data-driven world where devices have become an integral part of our lives. A recent study estimated that in the United States alone, 13.6 connected devices per capita consume an average of 300 gigabytes worth of data every month. In the workplace, COVID-19 has driven fundamental business changes that has sped up the adoption of digital technologies such as virtual conferencing, remote work, and e-commerce. Organizations are realizing that a high-quality video conference can be an adequate substitute for many in-person meetings. As a result, businesses are accelerating the digital transformation in order to adapt and thrive in this new environment. Five decades of sustained exponential growth in semiconductor performance has conditioned the average digital consumer to expect more from their devices. However, there are some headwinds ahead as traditional scaling slows down and power density rises. Because consumers and businesses are now generating data at a faster rate than they can consume it, technologists need to scale compute, storage, and bandwidth even faster to keep pace. Without investments in research and development of new and innovative technologies to address these challenges, the full potential of this data will go unrealized. SEMI: What forces are heightening the importance of heterogeneous system integration? What are the implications for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries? Radhakrishnan: The semiconductor industry increased transistor density and scaled performance through classical Dennard scaling until the turn of the century. By then, the gate oxide thickness had scaled down to atomic dimensions and the exponential increase in sub-threshold leakage signaled the end of scaling through traditional methods. Since that time, the chip industry has been relying on innovations in transistor materials and structures such as high-k metal gate, strained silicon, and FinFETs to keep pace with Moore’s law. However, this alone will not be sufficient to continue scaling and the industry needs to explore other vectors to augment improvements in transistor technology. Heterogeneous integration through advanced packaging is one key technology that can help drive these gains. Technologies like Foveros can enable device density scaling by creating a 3D stack of multiple die using high-density interconnects. Heterogeneous integration enables chipmakers to move from a monolithic system designed on a single large chip to a heterogeneous system comprised of a number of smaller chiplets. The main benefit of using smaller chiplets is that they improve yield and enable application based customization of the foundry processes. However, if the disaggregation to smaller chiplets is not accompanied by an increase in on-package bandwidth, the power and performance penalties associated with chiplet-to-chiplet communication will hobble system performance. This is why advanced packaging technologies that improve die-to-die communication are key enablers for heterogeneous integration. SEMI: What are some of the key technology challenges in developing heterogeneous systems? Radhakrishnan: The obvious challenge that most people focus on is the need for improved on-package bandwidth. However, as we rely on 3D stacking to continue device scaling at the package level, it is important to comprehend power delivery and thermal challenges as well. Power to the top die has to be delivered through TSVs on the bottom die, which not only adds resistance but also reduces the useful area available on the bottom die. This problem is further exacerbated when we stack more than two die. Excessive noise on the power delivery network can cause timing issues that limit the maximum operating frequency of the transistor. Similarly, when we stack multiple die, we must take into account associated thermal challenges. For example, each interface of the multi-die stack adds thermal resistance, which makes it harder to cool the chips at the bottom. SEMI: What are some of the key global market trends that driving demand for heterogeneous and system-level integration? Radhakrishnan: The number of artificial intelligence (AI) and machine learning applications have grown dramatically due to their ability to solve highly complex problems across a wide range of segments. AI and machine learning models require more memory bandwidth and compute capabilities that are difficult to achieve without some form of heterogeneous integration. Another market trend driving demand for heterogeneous integration is the increasing reliance on custom hardware accelerators. To combat the slowdown in frequency scaling and single-core performance, we have moved to multi-core architectures by tackling the inherent parallelism in our workloads. However, Amdahl’s law tells us that such an approach will hit a bottleneck when we reach the limits of the serial portion of the workload. As these constraints slow the performance of general-purpose processors, the reliance on custom hardware accelerators to boost performance for specific workloads is growing. Heterogeneous integration at the system level with a combination of CPUs, GPUs, FPGAs and other accelerators can optimize system power and performance. SEMI: What solutions is Intel developing to address these market needs? Radhakrishnan: Intel is actively involved in the development of the industry ecosystem for heterogeneous integration. We have developed a number of innovative advanced packaging solutions such as the EMIB and Foveros that are used in products today. Intel is also developing the next generation of advanced packaging technologies, Foveros Omni and Foveros Direct, which will dramatically scale the IO density by using direct Cu-Cu bonding technology. Foveros Omni is a crucial building block technology to enable high-voltage power conversion on the package for efficient power delivery. Intel is uniquely positioned to predict the design needs for future systems and deploy its resources to develop the technology building blocks needed to continue performance scaling. Our IDM 2.0 strategy enables us to leverage our leadership in packaging technologies to design the best products and use the best IP to deliver leading products across a broad range of categories. SEMI: What do you expect from your participation at SEMI Connecting Heterogeneous Systems Summit? Radhakrishnan: I’m hoping to shed some light on some of the new technologies we have been developing at Intel to enable heterogeneous system integration. I also want to bring awareness to the power-related challenges we are facing with heterogeneous systems. I also look forward to listening to what other industry leaders have to say on the topic. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He plays a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise include integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award, the highest Intel honor an individual or small team can receive. He has authored four book chapters, over 40 technical papers in peer-reviewed journals, and has been awarded 35 U.S. patents. He has also served as an adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after receiving his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Serena Brischetto is senior manager of marketing and communications at SEMI Europe.