semiconductor industry

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

China’s semiconductor sector has exploded to become one of the largest in the world and match the region’s prominence as the biggest consumer of chips. From 2015 to 2020 alone, revenue of China’s integrated circuit (IC) industry expanded at a rapid clip of 20% CAGR (RMB) to $128 billion.

Demand for hi-tech manufactured goods is at an all-time high and is expected to grow significantly in our new digital age, COVID-19 economy. This is especially true for semiconductor chips. Chip manufacturers have been working to meet this demand by building new factories and by optimizing processes and equipment in existing fabs. While there is much media coverage about new factories planned by leading-edge chipmakers and government investments in the semiconductor sector, greenfield fabs entail significant capital expenditures and are sometimes fraught with complex political concerns. As a result, they can take several years to complete and reach their planned production capacity. Instead, the semiconductor industry needs to optimize existing factories in order to increase productivity and yield and meet growing demand by implementing smart manufacturing solutions. Smart manufacturing solutions will inherently reduce costs with more efficient and automated processes, and those savings can be reinvested for the next wave of solutions. Chip Industry on the Bleeding Edge Semiconductor manufacturers have always been focused on bleeding-edge technology to outflank strong competition and build the best products – faster and cheaper. Today, pioneering organizations are using data to optimize manufacturing processes and equipment, a practice known as Smart Manufacturing. While there are many definitions of Smart Manufacturing, the essence is maximizing the utility of big data generated in these factories by leveraging three pillars: Sensing, Connecting, and Predicting. It is not just the digitization in manufacturing, but it is also about turning the data into actions that generate value – an effort the SEMI Smart Manufacturing Committee is driving based on the three pillars. Optimizing return on investment is the ultimate goal. SEMI Smart Manufacturing Initiative activity is based on three pillars that support the goal of increasing ROI. Making the Right Decision, Faster Smart manufacturing practices enable organizations to make the right decisions and take action faster based on insights generated from real-time and historical data. This requires data management technologies and applications that can process, analyze, and act on information instantly. It has become ever more difficult to process and discern the relevant data or signal from the vast volume of data, perform analytics or develop new ML or AI analytic tools, and then make the critical decisions to solve problems as close to real-time as possible. Who’s Responsible – IT or OT? In the past IT (Information Technology) and OT (Operations Technology) were separate entities within organizations, with IT focused on storing large amounts of data for enterprise systems and OT concentrated on using data to perform specific functions. Smart Manufacturing often demands combining IT and OT, difficult in rigid organizations that operate the two organizations independently and lack the infrastructure to implement comprehensive solutions. Success requires executive leadership sponsorship, motivated technical personnel and, most importantly, a clear deliverable on the value in implementing Smart Manufacturing. Many organizations have introduced top-level leadership positions such as a Chief Information Officer or Chief Data and Analytics Officer to address this convergence and many of these leaders are embracing Smart Manufacturing practices. The SEMI Smart Manufacturing community includes many of these leaders and therefore has highlighted the importance in the return on investment for Smart Manufacturing solutions. Read more about IT and OT convergence and note that Smart Manufacturing is synonymous with Industry 4.0. The SEMI Smart Manufacturing Initiative covers the entire supply chain. Get Smart in Smart Manufacturing While new technologies and applications are being created to deal with mountains of data, it is the underlying methodologies and practices that are key to a successful Smart Manufacturing deployment. SEMI, the trade association representing the electronics manufacturing and design supply chain, is in a perfect position to evangelize Smart Manufacturing experiences and best practices for the entire manufacturing community. The more than 30 member companies participating in the SEMI Smart Manufacturing Initiative bring more than 500 years of collective experience and knowledge to the topic. Many segments of the supply chain participate in the SEMI Smart Manufacturing Initiative including packaging, assembly, SMT and PCB assembly, test, software, data management, sensor and material suppliers. Learn How to Manufacture Smarter SEMI SMART Manufacturing is hosting two great conferences in the coming months – the Global Smart Manufacturing Conference (GSMC) and the SEMICON West Smart Manufacturing Pavilion. As a leader of the organizing committee and chair for the SEMICON West Smart Manufacturing Pavilion, I encourage people who want to learn how to implement Smart Manufacturing or expand their knowledge of Smart Manufacturing to attend these events. The GSMC will feature keynotes highlighting the value of Smart Manufacturing, offer tutorials on the three pillars, and introduce several case studies for each of the pillars. Thirty-two organizations – ranging from global cloud providers, semiconductor factory operators, leading equipment vendors and software application solution companies – will present. See the full agenda here. The SEMICON West Smart Manufacturing Pavilion will compliment GSMC by showcasing a number of use cases that highlight the value of Smart Manufacturing. Panel discussions will deep dive into the challenges of implementing these best practices and the direction smart manufacturing is taking in the coming years. Our goal for these events is for you to take this knowledge back to your companies, implement and improve on the detailed solutions highlighted at the conferences, and return next year to share your success stories with the community. See you soon, in person or virtually! About the Author Bill Pierson is VP of Semiconductors and Manufacturing at KX, leading the growth of streaming data analytics in this vertical. Bill is also a chair for the SEMICON West Smart Manufacturing Conference and an active team member of the SEMI Americas Chapter. He has extensive experience in the semiconductor industry including previous experiences at Samsung, ASML and KLA. Bill specializes in applications, analytics, and control. He lives in Austin, Texas, and when not at work can be found on the rock-climbing cliffs or at his son’s soccer matches.

In response to the PFAS Low Volume Exemption (LVE) Stewardship Program recently established by the U.S. Environmental Protection Agency (USEPA), the SEMI PFAS Working Group (WG) is focused on identifying strategies that minimize supply chain risks and impacts to downstream users.

Terry Tsao, Global Chief Marketing Officer at SEMI and President of SEMI Taiwan, recently discussed technology trends with Young Liu, Chairman of Hon Hai Technology Group (Foxconn), as a prelude to SEMICON Taiwan’s five online forums.

Today, AI algorithms are primarily run at large data centers-- in the cloud. For this intelligence to be used at the edge, data must be transmitted to the cloud, analyzed there, and the results transmitted back to the field of operation, such as a mobile phone, medical implant or autonomous vehicle.

As we round the corner on 2021, the microelectronics industry continues to face a severe talent crisis. With more than 34,000 jobs remaining unfilled at SEMI member companies in the United States alone, everyone is competing for the same talent pool. While the semiconductor shortage has received extensive media coverage, a critical talent shortage deserves equal attention. One way to address the talent shortage is to hold the line. Meaning, in addition to recruiting more diverse talent into the chip industry, we must retain the quality workforce we have. I believe that a key component of a diversity, equity and inclusion program must be retention. At Edwards, we feel so strongly about this that we have made retention a key part of our Diversity, Equity and Inclusion program – even changing the acronym to DEIR (pronounced DEER; diversity, equity, inclusion and retention) for emphasis. There are three overarching approaches we can take to promoting diversity-focused retention:Investment in on-boarding practices that allow time to hire appropriately and ensure a diverse pool of qualified candidatesEmbedded programming and policies that are learning and development (L D) based including career planning, succession planning, unconscious bias training, employee resource groups (ERG) and mentoringCorporate culture that respects employees through a healthy work life balance and promotes the well-being of society and the planetThis is a very important conversation. I asked Lubab Sheet-Davis, vice president of Strategy Innovation in the Office of the CTO at Lam Research, and Emerald Greig, executive vice president Americas at SurplusGLOBAL USA, to share their considerable experience and insight related to retention and DEI. Following is an excerpt from our conversation, which has been edited for clarity and brevity.Balaguer: In the context of DEI, why is employee retention so important?Sheet-Davis: In my view, there is a strong correlation between inclusion and retention. If people feel that their voices and perspectives are valued, they are more likely not only to stay, but also to perform at a higher level. Driving both inclusion and retention is having a seat at the table, having your voice heard, respectful treatment and fair opportunity. Retention is a core component of our inclusion and diversity strategy, which involves increasing representation by building a pipeline of diverse candidates, recruiting and retaining, fostering an inclusive culture (which supports retention) and open communication to share our progress.Balaguer: What role does data play in the drive to increase retention?Greig: Ours is a data-driven industry and I am surprised that we have not let the statistics drive us into action sooner. Clearly, diversity, equity, inclusion and retention all affect the bottom line. Millennials and Gen Zs already leave faster than any other generational group. The turnover rate in the tech industry averages around 13% with stays around 2-3 years.The cost to hire, train and integrate someone into a company is far more expensive than having a DEIR program in place to keep them. The Society for Human Resource Management (SHRM) reported that, on average, it costs a company 6 to 9 months of an employee's salary to replace them (which includes the costs of hiring, onboarding and training, L D and time to fill the role). For an employee making $60,000 per year, that comes out to $30,000 to $45,000 in recruiting and training costs.Sheet-Davis: Yes, which gives us all the more reason to move quickly! Given how central DEIR is to innovation, and that the challenges and opportunities facing our industry are bigger now than ever before, I believe we should be addressing DEIR with the same vigor that we address Moore’s Law.I worry if we keep saying DEIR will take time, it will take time. Granted many DEIR issues are cultural and culture is hard to change. However, this industry has demonstrated the capability to drive breakthroughs and to do so quickly. Let’s focus on DEIR with urgency while also ensuring the progress is sustainable.Balaguer: There is no doubt we need to move with a sense of urgency. I think a good way to keep the pedal to the metal is to create a DEIR roadmap that tracks our progress on multiple programs and helps us be accountable and stay focused. Meaningful retention strategies begin with solid diversity-focused hiring strategies.Balaguer: How does corporate culture inform retention?Greig: Let’s not forget: Employees, especially millennials, are looking for a corporate culture that demonstrates social responsibility as well as leadership and career development. In a recent study, 65% of employees said positive corporate culture has encouraged them to stay with their company. In fact, companies with strong cultures have seen a four-fold increase in revenue growth.We have raised a generation that strongly believes in being accepting of others and embraces equity and inclusion in their daily lives. They expect their employer to have this as part of their DNA. They believe in science, climate change, recycling, conservation, and similar sustainability issues and they want to know that they are making or doing something that makes the world a better place. If tech companies cannot convince millennials and Gen Z's that the companies are socially responsible and are doing all they can to embrace DEIR as part of their company culture, then the millennials will go elsewhere. Balaguer: How can employee resource groups be a building block for retention?Sheet-Davis: We support employee resource groups that are voluntary, employee-led and coalesce around demographic factors such as gender, ethnicity, sexual orientation or generation. Each has an executive sponsor, budget, plans and leadership structure. ERGs support inclusion by creating a sense of belonging, building comradery, and providing a safe space to raise awareness and help educate the rest of the company through a number of activities such as community service, holiday celebrations, guest speakers, networking, training courses and more. I serve as the executive sponsor of our Women@Fremont group, which is focused on accelerating the advancement of women in their early to mid-career at Lam’s headquarters. I know ERG members genuinely value the company’s support.Balaguer: What can we do during the hiring process to lay a strong foundation for employee retention?Greig: I believe that the work we do at the front end in terms of hiring practices are one of the main reasons we have a low turnover rate at SurplusGLOBAL. We have a policy to have three interviews for each candidate. Not three different people, but bring them in three times. Additionally, we have a 90-day trial and review period to make sure there is a good fit for both parties. Investing time up front ensures the right hire and the small size of our company allows us to know our employees. We can be nimble and quickly respond to employee needs as they arise.Balaguer: In what ways do you think mentoring can help improve retention?Sheet-Davis: Another aspect of building a more inclusive culture, and hence promoting retention, is through mentoring programs. Mentorship supports an employee’s development, growth and career planning. It’s a great way to get to know people, understand their ambitions and support their development. Hopefully, it results in sponsorship because that is what helps drive career advancement. Ultimately, I want to advocate for those that I mentor.Balaguer: At Edwards, we are refreshing mentoring as part of our DEIR program. I see mentoring as a program that can support employee retention in multiple ways including career planning, professional development, succession planning and promoting inclusivity. Encouraging and empowering personal development is key in growing a productive workforce and mentoring does all these things. Often overlooked is the fact that mentoring is a benefit to both the mentor and the mentee. I have personally mentored several young professionals at Edwards, and I can attest that I have learned as much from them as they have from me. Mentoring is definitely a two-way street.Balaguer: What’s your message to our readers about retention as an element of diversity, equity and inclusion?Greig: I am excited to see DEIR and especially, retention, gaining traction. The semiconductor industry has always tended to have a cyclical rhythm to it. A generation of potential employees have grown up witnessing the fallout from periodic down cycles and the inevitable reductions in workforce. I think there is an element of rebranding we need to do in this area to support our retention efforts. Sheet-Davis: If we only focus on recruiting and not retention, we tread water. Consistent with any other successful business strategy, a holistic integrated approach to DEIR that is prioritized, resourced and sustained over time is key. Balaguer: We all agree that retention is a key component in the war for talent. While this conversation has been more wide-ranging than we can share with our readers, the prime takeaways have focused on these elements: Follow the data. Execute with a sense of urgency. Hire right. Work hard on inclusionary programming such as ERGs, mentoring and sponsorship. Build a genuine corporate social responsibility program. Retention will result.Many thanks to Lubab Sheet-Davis and Emerald Greig. As always, comments, questions and suggestions are welcome. We can be reached at [email protected], [email protected] and [email protected]. I invite our readers to join the conversation, as well as review the recently released SEMI Foundation DEI Roadmap and Toolkit.Scott Balaguer is Vice President and General Manager, Semiconductor Division at Edwards Vacuum LLC and Chairman of the SEMI North America Advisory Board.

Becoming a Certified B Corporation™ comes with many benefits, most of them extending beyond the walls of the company and into the hands of employees, community members, and industry partners. The designation makes the meticulous and rigorous process to certification well worth the endeavor. In 2021, Brewer Science announced that it’s the first company in the semiconductor industry to become a Certified B Corporation. Our journey to become a Certified B Corporation inspired us to share our top five reasons for meeting the high standards the designation sets for both environmental and social responsibility. 1. Pave a pathway for continuous improvement B Lab™, the certifying organization for B Corps, believes in continuous improvement, and B Corps must create an improvement plan to demonstrate the areas of social and environmental performance they focus on in the coming years. Brewer Science will hold B Corp certification for three years before submitting to a renewal process. In order to be recertified, a company must score higher on recertification than on the previous certification. The assessment evaluates all facets of the company, and it’s a learning process to help the company target and identify ways to improve business practices. Brewer Science has already identified improvement areas for the recertification. We’ve implemented several human resource initiatives that are not written into policy yet, such as flexible and expanded work options. Additionally, we have expanded our use of a cloud-based learning platform to provide employees with more training options and performance conversations held quarterly instead of annually. Brewer Science scored many points for community involvement and charitable giving. However, we are still expanding community engagement by supporting or donating to a new local organization each month. Brewer Science became Certified Employee-Owned in 2020, but since it was the first year of the ESOP and shares were not yet dispersed, B Lab didn’t fully recognize the program. 2. Share the values of your stakeholders In 2006, Brewer Science started externally reporting environmental, safety, and health performance every year through its annual Corporate Sustainability Report in order to be transparent with customers, suppliers, and employees. The impact of this report on all of our stakeholders motivated us to pursue other ways to promote sustainability and inclusion as a shared asset for our customers and suppliers. In 2016, Brewer Science became GreenCircle Certified Zero Waste to Landfill, an annual certification that we have achieved every year since then. Certified B Corporations are businesses that meet the highest standards of verified social and environmental performance, public transparency, and legal accountability to balance profit and purpose. The standard is highly respected standard, in part because of B Lab’s rigor with the questionnaire and certification process. Not only does becoming a B Corp show your stakeholders that you care, and that you are walking the walk, but it also allows you to show how much your company cares through your B Corp Impact Area. Brewer Science pursued the impact area of environmentally innovative manufacturing, a category that required detailed evidence of how Brewer Science manages the manufacturing waste and minimizes its carbon footprint. The B Impact Area Scores reflect the five areas where the business excels. 3. Be competitive in an industry that demands sustainability and social responsibility Sustainability is of growing importance in the semiconductor industry. A company can convey its commitment to sustainability by becoming a Certified B Corp. The B Impact Assessment requires benchmarking to other companies in the industry in areas of social concern, such as sustainability, inclusion, and diversity. While benchmarking was nearly impossible for Brewer Science since we rank high as an innovator in these areas, we were able to not only set the benchmark for ourselves, but other industry partners who pursue B Corp certification in the future through our collaboration with B Lab. 4. Connect with a community that cares Becoming a Certified B Corporation instantly opens companies up to a network of other B Corps across the world. The more than 4,000 B Corps in 150 industries and 74 countries enables makes it easy to network in the areas such as environmental initiatives, attracting top talent, and even just using business as a force for good in the semiconductor industry. Knowing that a business is actively trying to make a positive social change will help attract top talent looking to find meaning in their careers. B Corp certification validates a company’s employee-centric culture, which can help beef up employee retention. What’s more, an exclusive job posting board called B Work, sponsored in part by B Lab, helps connect job seekers with companies that share their values. Employees are connected through an exclusive B Corporation community platform, B Hive, enabling them to collaborate and share ideas with other B Corp employees. There is also a section within the B Hive where other B Corps can share benefits with other B Corp member employees. With such a diverse range of companies that are Certified B Corps, shared benefits can include anything from discounted clothing to travel deals or even free consultations. Additionally, employees of B Corporations can collaborate on local recycling events and community engagement. 5. The bottom line Companies don’t pursue the Certified B Corp designation to drive improvements to their bottom line. Yet by sharpening their focus on environmentally sustainable initiatives and diversity and inclusion, most companies could indirectly see significant return on investment. For example, having a pathway for continuous improvement, sharing the values of your stakeholders, being competitive in the industry, and connecting to clientele and employees that value social responsibility all enable your business to grow. In the long run, becoming certified as a B Corp can save a company money by giving companies access to community data that provides insights into cost-effective ways to be more sustainable. Plus, the certification process helps companies identify wasteful spending. For more information about Certified B Corporations, and to get started on your company's application, visit the Certified B Corporation website. Jessica Albright is a content marketer at Brewer Science, Inc.

As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Higher on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries are driving demand for advanced packaging technologies that address these issues but introduce challenges of their own such as efficient power delivery to all the different domains in a heterogeneous system. SEMI spoke with Kaladhar Radhakrishnan, Intel Fellow at Intel, about heterogeneous system integration trends and new developments in the semiconductor industry. Radhakrishnan shared his views ahead of his keynote at the SEMI Connecting Heterogeneous Systems Summit, 1-3 September 2021, an online event. Join the summit to meet experts from Intel and other key industry influencers. Registration is open. SEMI: What is driving the adoption of electronics and semiconductor devices nowadays and why is the development of new and innovative technologies important? Radhakrishnan: We are living in an increasingly data-driven world where devices have become an integral part of our lives. A recent study estimated that in the United States alone, 13.6 connected devices per capita consume an average of 300 gigabytes worth of data every month. In the workplace, COVID-19 has driven fundamental business changes that has sped up the adoption of digital technologies such as virtual conferencing, remote work, and e-commerce. Organizations are realizing that a high-quality video conference can be an adequate substitute for many in-person meetings. As a result, businesses are accelerating the digital transformation in order to adapt and thrive in this new environment. Five decades of sustained exponential growth in semiconductor performance has conditioned the average digital consumer to expect more from their devices. However, there are some headwinds ahead as traditional scaling slows down and power density rises. Because consumers and businesses are now generating data at a faster rate than they can consume it, technologists need to scale compute, storage, and bandwidth even faster to keep pace. Without investments in research and development of new and innovative technologies to address these challenges, the full potential of this data will go unrealized. SEMI: What forces are heightening the importance of heterogeneous system integration? What are the implications for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries? Radhakrishnan: The semiconductor industry increased transistor density and scaled performance through classical Dennard scaling until the turn of the century. By then, the gate oxide thickness had scaled down to atomic dimensions and the exponential increase in sub-threshold leakage signaled the end of scaling through traditional methods. Since that time, the chip industry has been relying on innovations in transistor materials and structures such as high-k metal gate, strained silicon, and FinFETs to keep pace with Moore’s law. However, this alone will not be sufficient to continue scaling and the industry needs to explore other vectors to augment improvements in transistor technology. Heterogeneous integration through advanced packaging is one key technology that can help drive these gains. Technologies like Foveros can enable device density scaling by creating a 3D stack of multiple die using high-density interconnects. Heterogeneous integration enables chipmakers to move from a monolithic system designed on a single large chip to a heterogeneous system comprised of a number of smaller chiplets. The main benefit of using smaller chiplets is that they improve yield and enable application based customization of the foundry processes. However, if the disaggregation to smaller chiplets is not accompanied by an increase in on-package bandwidth, the power and performance penalties associated with chiplet-to-chiplet communication will hobble system performance. This is why advanced packaging technologies that improve die-to-die communication are key enablers for heterogeneous integration. SEMI: What are some of the key technology challenges in developing heterogeneous systems? Radhakrishnan: The obvious challenge that most people focus on is the need for improved on-package bandwidth. However, as we rely on 3D stacking to continue device scaling at the package level, it is important to comprehend power delivery and thermal challenges as well. Power to the top die has to be delivered through TSVs on the bottom die, which not only adds resistance but also reduces the useful area available on the bottom die. This problem is further exacerbated when we stack more than two die. Excessive noise on the power delivery network can cause timing issues that limit the maximum operating frequency of the transistor. Similarly, when we stack multiple die, we must take into account associated thermal challenges. For example, each interface of the multi-die stack adds thermal resistance, which makes it harder to cool the chips at the bottom. SEMI: What are some of the key global market trends that driving demand for heterogeneous and system-level integration? Radhakrishnan: The number of artificial intelligence (AI) and machine learning applications have grown dramatically due to their ability to solve highly complex problems across a wide range of segments. AI and machine learning models require more memory bandwidth and compute capabilities that are difficult to achieve without some form of heterogeneous integration. Another market trend driving demand for heterogeneous integration is the increasing reliance on custom hardware accelerators. To combat the slowdown in frequency scaling and single-core performance, we have moved to multi-core architectures by tackling the inherent parallelism in our workloads. However, Amdahl’s law tells us that such an approach will hit a bottleneck when we reach the limits of the serial portion of the workload. As these constraints slow the performance of general-purpose processors, the reliance on custom hardware accelerators to boost performance for specific workloads is growing. Heterogeneous integration at the system level with a combination of CPUs, GPUs, FPGAs and other accelerators can optimize system power and performance. SEMI: What solutions is Intel developing to address these market needs? Radhakrishnan: Intel is actively involved in the development of the industry ecosystem for heterogeneous integration. We have developed a number of innovative advanced packaging solutions such as the EMIB and Foveros that are used in products today. Intel is also developing the next generation of advanced packaging technologies, Foveros Omni and Foveros Direct, which will dramatically scale the IO density by using direct Cu-Cu bonding technology. Foveros Omni is a crucial building block technology to enable high-voltage power conversion on the package for efficient power delivery. Intel is uniquely positioned to predict the design needs for future systems and deploy its resources to develop the technology building blocks needed to continue performance scaling. Our IDM 2.0 strategy enables us to leverage our leadership in packaging technologies to design the best products and use the best IP to deliver leading products across a broad range of categories. SEMI: What do you expect from your participation at SEMI Connecting Heterogeneous Systems Summit? Radhakrishnan: I’m hoping to shed some light on some of the new technologies we have been developing at Intel to enable heterogeneous system integration. I also want to bring awareness to the power-related challenges we are facing with heterogeneous systems. I also look forward to listening to what other industry leaders have to say on the topic. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He plays a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise include integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award, the highest Intel honor an individual or small team can receive. He has authored four book chapters, over 40 technical papers in peer-reviewed journals, and has been awarded 35 U.S. patents. He has also served as an adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after receiving his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Serena Brischetto is senior manager of marketing and communications at SEMI Europe.

Spend any time with Ansys’ John Lee, Rich Goldman or Marc Swinnen and you’ll hear plenty of optimism about the semiconductor industry even though they tick off a long list of looming design challenges. The need for reliable and effective electronic systems, they emphasize, is great and runs through high tech, aerospace and defense, automotive, IoT and 5G with communications being a common denominator. The three are especially bullish these days on changing market dynamics brought on by systems companies building company-specific bespoke, or custom, silicon. These systems companies are building chips with a different perspective and a fresh look at silicon design, a move away from the more traditional segment-specific silicon due to much more complexity. Ansys, a member of the ESD Alliance, a SEMI Technology Community, is a 4,100-employee company with a comprehensive portfolio of multiphysics engineering simulation software for product design, testing and operation products and services. John, Rich, Marc and I focused on Ansys’ semiconductor and electronics segment for our conversation. Smith: When did you notice the move by systems companies to build their own chips? What drives this trend? Lee: The inflection point was about three years ago when hyperscale data center and system companies recognized they needed an enterprise system design platform. They are designing bespoke silicon, driven to do this for cost efficiencies and to avoid relying on outside suppliers. They also want differentiation based on their specific platform needs so they can optimize compute power to their specific needs. Smith: What is driving the trend for multiphysics experience to ensure effective and reliable electronic systems? Lee: The increasing need for multiphysics analysis is acute. The physics of 3D IC, for example, brings in mechanical engineering with the convergence of mechanical and electrical as 3D emerges at the intersection of IC and System. As a result, physics becomes a necessity to analyze the stability of the chip in the package. Goldman: As well, the move to stacked chips, 3D IC and wafer-on-wafer requires thermal, electromagnetic and mechanical analysis in addition to the traditional analysis for function, performance and power. They all need to be analyzed together, not serially. It becomes multiphysics, not multiple physics. Smith: Two distinctly different disciplines – multiple physics and multiphysics – are needed for semiconductor design. How are they different? Why the need now? Swinnen: Multiple physics refers to the sheer breadth of physics that is now needed to analyze from the IC up to the largest system whereas multiphysics refers to the capability to analyze several physical effects concurrently, accounting for their impact on the design and interactions between various physics. Multiphysics are necessary to analyze the full context of the system environment – from nanometers to kilometers – for multi-chip packaging, chip-to-package-to-silicon and systems with multi-domain guidance. Goldman: A self-driving car, as an illustration, includes AI systems-on-chip, solid-state sensors, infotainment systems and radar/lidar detectors that must all work in the rain, the heat and the bitter cold. Smith: Why are design groups being reorganized to include expertise in mechanical and electromagnetic issues? Swinnen: Complexity has exploded, driven by a long list of technical requirements and, perhaps, mischaracterization. Goldman: Just consider the system on chip, mischaracterized by the semiconductor industry. The chip is never a system by itself. Rather, it is a complex component in a larger system and must be analyzed in that context. 3D IC is where this comes together and forces a recognition of physics outside the traditional scope of SoC design. 3D IC chips are much closer together on the board and it takes multiphysics embedded into the workflow of semiconductor design, packaging, system design and 3D IC to ensure they work reliably and efficiently. Smith: What is the solution? Goldman: It’s clear a specialized digital thread is necessary to move disparate groups with expertise in systems, physics and silicon together. Today, these groups or disciplines might not exist in the same company, whether it be a foundry, fabless or outsourced semiconductor assembly and test (OSAT) company. Lee: In order to unify the entire system design environment, a cloud-based, open and extensible heterogenous enterprise compute platform is required. It is similar to the SaaS-based business model and known as Simulation-as-a-Service (also SaaS). While vertical integration of design groups is already taking place at leading system design houses, there have also been advances in electronic design tools. These are starting to offer more comprehensive multiphysics capabilities including thermal, fluid dynamics (CFD), mechanical stress and reliability analysis in a single analysis cockpit. Today’s system designers face two platform challenges: First, they need an environment that is open enough to accept analysis results from multiple sources so that they can be overlapped and cross-analyzed. Second, the design platform must have the capacity to handle the enormous amounts of data generated by the latest 3-nanometer chips and 3D IC systems, and this implies an intimate coupling to elastic cloud computing. The days of an engineer writing Perl scripts and handing it off to someone else are gone. We believe that the industry is responding to this challenge with a new generation of design platforms that a cloud-native, open and extensible to allow heterogenous enterprise design. We are definitely at an inflection point in electronic design today, but the electronic industry has faced these before an we are confident it will master these challenges as well. About Rich Goldman Rich Goldman is director of marketing for the Electronics and Semiconductor Business Unit of Ansys. He holds a Bachelor of Science degree from Syracuse University and an MBA and Master of Science degree in Engineering Management. Moscow Institute of Electronic Technology (MIET)’s first honorary professor, he is also the recipient of honorary PhD degrees from Russian-Armenian (Slavnoic) University and State Engineering University of Armenia for contributions to the advancement of Armenia’s high-tech education and economic ecosystem. Rich served on EDAC’s board of directors. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University. About Marc Swinnen Marc Swinnen is director of product marketing for the Electronics and Semiconductor Division of Ansys. He holds Master degrees in Electronic Engineering and Industrial Management from KU Leuven, Belgium, as well as an MBA from San Jose State University. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.