SEMI Voltage Sag Immunity Task Force Workshop held at SEMICON West
By Mark Stephens, EPRI, SEMI Voltage Sag Immunity TF Leader
On October 8, 2025 at SEMICON West's debut in Phoenix Arizona, the “Enhancing Voltage Sag Immunity” workshop, led by the SEMI Voltage Sag Immunity Task Force, brought together over 20 semiconductor manufacturers, utilities, tool OEMs, and researchers to address persistent downtime in fabs caused by voltage sags—even for equipment certified under the SEMI F47 standard. The workshop reviewed the history and limitations of SEMI F47, highlighting that while the standard addresses single- and two-phase sags, it does not require testing for three-phase events, which account for up to 20% of downtime incidents. Presentations from EPRI, GlobalFoundries and National Grid reinforced that real-world events—such as three-phase sags, repeat sags, and variations in event magnitude and phase—can still cause tool trips above the SEMI F47 curve, underscoring the need for more robust and representative testing methods.
Key Findings and Proposed Updates
Research conducted by the task force and analysis of fabrication data show that many instances of downtime are connected to a particular phase-to-phase test vector form—described as “easier to create” and denoted Acceptable Method 1 of IEC 61000-4-34). Method 1 was commonly used for compliance certification. However, the Method 1 test vector form does not match the phase-to-phase voltage sags observed in real situations. As a result, equipment passing certification with Method 1 may still fail during actual phase-to-phase voltage-sag events.
The workshop recommended shifting to a more accurate and realistic phase-to-phase test vector denoted Acceptable Method 2 in IEC 61000-4-34. Method 2 better reflects genuine voltage sag conditions. Consequently, IEC 61000-4-34 states that Method 2 is more representative of “real-world” phase-to-phase voltage sags and notes that outcomes can differ significantly depending on which testing procedure is used (Method 1 or Method 2). Findings from the voltage sag task force support this claim.
For these reasons, the task force suggests updating SEMI F47 to designate the realistic Method 2 test vector form as the preferred method, aligning standards with IEC 61000-4-34’s perspective for greater technical accuracy. The “easier to create” Method 1 could remain an option, but future test documentation must specify which vector was applied. Over time, it’s expected that buyers will increasingly request testing with the advocated realistic approach of Method 2.
For three-phase voltage sags, the proposal involves limited characterization testing as a recommended test but not mandatory for certification. The future revision of SEMI F47 will also benefit from enhanced standardization and documentation of test reports based on the valuable input from the Korean Task Force.
Next Steps for Task Force
The next steps are clearly defined: the task force is working to synthesize all workshop and stakeholder inputs into a draft revision of SEMI F47 by late February 2026. This draft is planned for submittal for balloting in March 2026. The group will continue to refine test methods, clarify guidance for tool power connections, and encourage the adoption of advanced sag generator hardware capable of realistic and comprehensive testing. These efforts aim to ensure that future versions of SEMI F47 more effectively reduce voltage sag-induced downtime in semiconductor manufacturing.
If you missed the workshop, you can find the recording and presentations here: Enhancing Voltage Sag Immunity: SEMI F47 Standard Updates & Insights Workshop
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December 8, 2025