SEMICON West

After two days of online pitches Startups for Sustainable Semiconductors semifinalists, the program’s organizing committee has selected nine finalists. These companies will present at the Sustainability Pavilion during the Startups for Sustainable Semiconductor session at SEMICON West.

With technological advancements driving our digital era, the demand for semiconductors is skyrocketing. The chip industry is projected to reach unprecedented heights of around $1 trillion in annual revenue by 2030. However, amid this remarkable growth, a daunting challenge looms: the shortage of skilled workers for semiconductor design and manufacturing. As the industry strives to keep up with the escalating demand, the scarcity of qualified personnel has emerged as a critical obstacle. To help the industry overcome this and other key issues, SEMICON West 2023 will explore Building a Path Forward to its future in the event’s inaugural CEO Summit keynote program. A recent SEMI announcement provides an overview of the keynotes and programs at the July 11-13 exhibition and conference at the Moscone Center in San Francisco. The event on July 13 will kick off with Path for Talent session keynotes focused on cultivating a strong talent pipeline, creating a diverse and inclusive industry, and building a career in microelectronics. Tom Sonderman, President and CEO of SkyWater Technology, will present the Path for Talent keynote titled Building the Future: Workforce Development in the Semiconductor Manufacturing Industry. In a podcast with Francoise von Trapp of 3D InCites, Sonderman previews his presentation, highlighting the talent challenges facing the U.S. semiconductor industry and potential solutions. He also shares a glimpse of some of the SkyWater recruitment and training programs designed to fill critical roles from fab technicians to lead engineers. The interview with Sonderman is part of the SEMICON West Podcast Series in the runup to and at the event. It follows the opening SEMICON West preview episode with SEMI Americas President Joe Stockunas in which he highlights a slew of new features that span keynote and conference programming, networking opportunities and even dining options. The CEO Summit keynote program features two additional critical industry topics each of the first two days of the event: Path to $1T – Tuesday, July 11 Luminaries will share insights on the chip industry’s progress towards $1 trillion in annual revenue including the importance of CHIPS Act funding. New semiconductor technology advances and growth segments that promise to boost the global supply chain’s financial performance will also be hot focus topics. Path to Net Zero – Wednesday, July 12 CEOs will share sustainability strategies and insights on the U.S. microelectronics industry’s position on international sustainability and climate agreements and legislation. SEMI offers a comprehensive workforce development program to aid the chip industry in narrowing the talent gap and promoting diversity, equity and inclusion. The program will be on display at the SEMICON West Workforce Development Pavilion hosted by the SEMI Foundation. The pavilion will offer new strategies for recruiters, students and job seekers and spotlight why microelectronics is a smart career choice. Discussions on building a diverse and inclusive workforce, and an interactive day with high school students to help spark their interest in microelectronics careers will be key features of the program. Registration for SEMICON West 2023 is open. Samer Bahou is director of Marketing Communications at SEMI.

The journey of the three twentysomethings was chronicled in Chip In, a new documentary from Roadtrip Nation, a nonprofit that supports road trips to capture empowering stories that help students find careers. Chip In was made possible by the SEMI Foundation.

In many ways it feels like we’ve turned back the hands of time. We are staying at home, playing board games with the family. Outdoors, we can view mountains not seen in decades – air pollution has dropped nearly 20 percent. Neighbors we haven’t met are out walking, a lot. Traffic is relatively sparse.We’re staying up late, sometimes even getting up early, for calls with all regions. Some of us have temporarily suspended our use of cleanroom masks – but now wear them everywhere we go outside of the house. And through virtual meetings, I see I’m not the only one who let the beard grow. Who would’ve thought we’d be able to so quickly and completely change our habits?Clearly, the usual distractions that fill most of our lives have given way to a temporary pause. We have time to reflect, and perhaps gain even greater perspective. I hope that’s been a good thing for you.Through virtual meetings, we seem to be getting access to people not typically in our circle of influence – both up and down the organizational ladder. This pleasant surprise seems to be helping to create a valuable acceleration in how the industry community interacts and progresses.As a testament to the strategic importance of our industry, the fabs continue to produce. This is due in great part to the standards, technologies and their resulting applications that enable those operations. Many parts of our industry supply chain became officially designated as essential businesses. Whether or not we stayed home from the office, we’ve continued to work on our roadmaps for growth beyond the current lull.Empowered by 50 years of technology legacy, we are again demonstrating the capability to manage disruption through collaboration. This is the signature of our industry’s highly regarded business culture. Among what we have learned is that this pandemic has made all of us more vulnerable in a variety of ways, and in turn has accelerated our unity as an industry community like never before.This month, as I brainstormed with a set of industry execs during one of countless Zoom meetings, it was clear that when they gather, they want more than a repackaged version of everyone else’s usual messages about this unusual year.While this type of year certainly wasn’t what we had in mind when we began to construct ways to mark this 50th year of SEMICON West, we’ve taken the bull by the horns and begun to blaze a new trail. The consensus within the industry is that SEMI’s constant, measured communication is netting an increased, and growing, level of trust among our collective, global group that may serve as one of the silver linings of this irregular year.As a result, we’ll lay a new road with the first – and possibly not the last – Virtual SEMICON West. For this inaugural digital format, we’ve secured a set of visionaries offering both legendary and evolutionary talents alike to reveal what we can expect during the next few years. It’ll be unlike any other such gathering before, and there’ll be something for everyone.Despite the pause in time we’ve experienced during our isolation of these recent weeks, the timeless value of collaboration marches on. I look forward to joining you at Virtual SEMICON West, July 20-23.Dave Anderson is president of SEMI Americas.

Did you miss the SEMI International Standards Reception at SEMICON West 2018? Not to worry, here are the highlights.SEMI honored two Standards industry leaders for their outstanding accomplishments in developing Standards for the electronics and related industries.Two awards were given recognizing the efforts of each member. The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.James Amano, Sr. Dr. International Standards, opened the reception with a few words. He noted that the total number of published SEMI Standards is nearing 1000, and that these documents serve as the backbone of modern day semiconductor manufacturing. SEMI president and CEO Ajit Manocha, speaking at the SEMI International Standards Reception at SEMICON West. Ajit Manocha, President and CEO of SEMI, reminisced how he was an active Standards Member, and how much he got out of SEMI Standards as a young engineer at Bell Labs. He passionately emphasized that SEMI Standards remain critical in this era of new materials and disruptive architectures and processes, calling them the "oxygen of the industry."Laura Nguyen is coordinator, International Standards, at SEMI.

The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-Tencor, a speaker at the TechXPOT, for insights about the readiness of inspection and metrology tools for EUVL applications at 5nm and 3nm. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-TencorSEMI: In general, how would you characterize the readiness of inspection and metrology tools intended for EUVL applications at 5nm and 3nm? In particular, what are some of the remaining research and development challenges that need to be addressed for each of these nodes?Neeraj Khanna: KLA-Tencor is working closely with its customers to qualify and ramp EUV. Our suite of inspection, metrology and data analytic solutions are being implemented to enable EUV infrastructure readiness including, for example, new reticle and resist qualification, scanner qualification, and EUV ramp preparation. These EUV integration activities require process control systems that support a wide range of applications, including hotspot discovery, lithography modeling, focus/dose process window qualification, reticle print check, mask blank inspection, and process and tool monitoring.As with any major technology inflection, it is critical to understand sources of process variation to enable ramp at optimal yield. For example, stochastics result in random pattern variations, which have a major impact on EUV yield. To manage stochastics, IC manufacturers are deploying process control solutions that support fast modeling of stochastic variations coupled with high-sensitivity, high-coverage wafer defect inspection. Another example is a methodology called hybrid scanner utilization whereby, when EUV scanners are implemented in production, they will only be used for a few layers, while all other layers will be patterned with 193i scanners. This technique requires tighter control and monitoring of overlay budgets.SEMI: How are you able to achieve this tighter control and monitoring?NK: To understand why hybrid scanner utilization requires tighter control and monitoring of overlay budgets, it’s important to outline how this differs from current scanner implementation. For critical layers in current process flows using 193i lithography, pattern layers for a given wafer are printed using the same stage/chuck on the same scanner. The overlay performance achieved using this lithography strategy is called dedicated chuck overlay (DCO). Use of a dedicated scanner and chuck for lithography reduces inter-scanner and inter-chuck distortion effects, resulting in DCO overlay error of less than 1nm. When EUVL is first implemented in production, it will be used for a few layers – likely, cut masks and contacts with eventual migration to metal 1 layers. All other layers will be patterned with 193i scanners. This hybrid scanner operation eliminates any possibility of using a dedicated scanner and dedicated chuck to support tight overlay performance specifications. Instead, fabs will be forced to optimize mix-and-match overlay (MMO), with the overlay performance obtained using different scanners for printing different layers on a given wafer.With overlay specifications for advanced DRAM and logic at ~2.5nm, fabs will need to implement strict 193i-to-EUV scanner matching strategies or risk consuming 60 to100 percent of the overlay budget on just MMO. To achieve tighter overlay control and monitoring required for MMO, fabs need to implement dense, in-field overlay error measurements that feed into scanner fleet management systems. KLA-Tencor’s ATL™ overlay metrology system supports a high measurement speed and the use of small in-die targets, enabling dense in-field overlay measurements with high accuracy. Our 5D Analyzer® data analytic and management system includes scanner fleet management capability that enables automatic product-based corrections to minimize MMO error, helping fabs reduce the risk to yield loss associated with a 193i-EUV mixed scanner implementation. SEMI: What other challenges do you see coming to the fore at 5nm and 3nm?NK: Overall, the 5nm and beyond design nodes will face challenges associated with new lithography technology, potential new device structures and smaller pattern pitches. IC manufacturers will require process control solutions that not only identify process windows, but also monitor patterning parameters and defectivity at multiple points to identify process shifts. To monitor dynamic processes at these advanced nodes, inspection and metrology tools will need to have both sensitivity to critical parameters/defects and robustness to process variation in order to provide IC engineers with smart feedback for efficient control of their processes.SEMI: Could you elaborate on what will be required to monitor patterning parameters and defectivity at multiple points? How different will the techniques be at 5nm/3nm vs. at say, 7nm or 10nm?NK: As an example of monitoring at multiple points, consider the transition to EUV lithography. With EUV, the cost per scan goes up dramatically. Thus, IC manufacturers will monitor parameters at multiple points to maximize yield and minimize risk: EUV reticle qualification requires inspection and metrology throughout the entire flow from mask blank manufacturing, to the mask shop, to the IC fab. For the advanced design nodes associated with EUV, wafer qualification requires monitoring and control of wafer defectivity, shape and geometry throughout the wafer manufacturing process. It also requires control of fab incoming wafer qualification while ensuring that fab-wide processes are meeting defect and shape standards necessary for printing smaller feature sizes. EUV resist characterization and qualification requires comprehensive lithography simulation, wafer defect inspection, and film thickness and uniformity measurements to help reduce development time and prepare the litho stacks for production ramp. As EUV scanners are ramping, fabs are faced with finding any unknown particle sources within the new scanner chambers. This situation is driving the need for tighter and more frequent PWP (particles per wafer pass) chamber monitors to ensure scanner cleanliness. In addition, EUV scanner qualification requires reticle front and backside particle checks, and hotspot discovery and process window qualification using optical wafer defect inspection and e-beam review. EUV process monitoring encompasses overlay error monitoring, focus/dose monitoring, critical dimension (CD) and 3D device shape monitoring, and continuous process window monitoring. EUV inline defect monitoring and tool monitoring is important for reducing baseline defectivity in the litho cell for faster ramp, and for early identification of litho excursions in production. A critical part of this monitoring strategy is inline after develop inspection (ADI) monitoring, which is defect inspection on patterned wafers after printing and development of the resist ADI. Inline ADI innovations that find yield-critical defects allow fabs to reduce process issues, prevent at-risk wafers early in the process, and enable rework when excursions are found in production. As with past technology transitions, the implementation of multiple monitoring steps as part of a comprehensive process control strategy will be critical for a fab’s successful ramp of EUV.Debra Vogler, SEMI

What’s next for smarter, more connected electronics manufacturing - Part 3 The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco. While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development. “People don’t think of research and development as the first place to automate, but it’s where applying our digitization and simulation has first had impact,” says David Fried, Coventor vice president of Computational Products. He noted that insertion is easier in the lab than in the fab. Technology at 10nm and beyond is now so complex that companies at the leading edge must use process modeling to understand the effect of process variation on their designs. Learning cycles can now be accelerated during development by simulating 10,000 digital wafers instead of running 25 actual wafers during screening, Fried says. Applying structured analysis and machine learning to the data simplifies optimization across the 500 or more interrelated process steps. Coventor has recently introduced a statistical analysis package that aids the design and analysis of process variation experiments by using large volumes of data from its models. Fried says these models are next being used to accelerate the yield ramp in manufacturing. Digital simulation also could speed development of high-mix, lower value products While digital twins are best known for their use in complex, high value products like jet engines, the simulation technology could also enable the electronic manufacturing services (EMS) sector to reduce the time, cost and risk of developing its high mix of products. “The EMS sector’s use of digital twins will be vital for it to smooth the move of CAD/CAM digital design data for so many different products into manufacturing, and to accelerate validation testing of designs and products by doing more of it in the virtual world,” says Dan Gamota, vice president of Engineering and Technical Services at Jabil. Gamota also highlights the push for traceability from the automotive and healthcare markets, where the digital models could be used to quickly assure that the design was built exactly as specified. “In the past year, traceability has evolved from just ‘nice to have’ to ‘how to achieve,’” he adds. “Companies are expecting it, but aren’t willing to accept the cost and risk of doing it alone. We need the community to discuss realistic implementations, identify the most critical elements and bring together the ecosystem partners to build baseline reference architectures for key digital building blocks. The community also needs to assure the reliable flow of data among the electronic manufacturing segments from semiconductor to OSAT to EMS.” Predictive maintenance and virtual metrology applications could mature in next few years While predictive maintenance initially seemed a likely early application of machine learning in factories, it remains a challenge for the electronics sector. “The difficulty is that it’s not clear where to get the most bang for the buck,” says Tom Ho, president of BISTel America, noting that it may make the most sense to track the failure performance of a single expensive part, like an electrostatic chuck, since predicting the failure performance of a whole complex system like an etcher is much harder. “Collecting enough data from all failure types, including especially the rare events, is difficult unless you have a long history of a lot of tools,” adds Doug Suerich, PEER Group product evangelist. “The gain from collecting performance information from many tools across the industry could be big, but many companies still need to overcome concerns around exposing their IP.” Another big opportunity for prediction is virtual metrology – predicting the wafer outcome from the process or sensor data with enough accuracy to replace the physical metrology. “Virtual metrology is improving, and since metrology can be slow and expensive, any reduction could mean a huge potential savings,” says Suerich. “But it is still seen as too scary for many companies. Two to three years from now, companies will expand the practice from lower risk areas into processes that require more confidence in the results.” Moving beyond prediction to automated control needs digital models Once the results are predicted, the model can be used to control or automatically optimize a process and enable the system to learn by itself, usually by reinforcement learning on a digital model. The model can then independently make adjustments to optimize the manufacturing process. “Automated process development is getting close now. Instead of smart guys turning the knobs, deep learning is automating the smart tuning,” says Suerich, suggesting the industry could see widespread adoption in as little as two to three years. This type of machine learning needs a good digital model, and masses of data for learning. One approach uses human experts to build a physics-based model of the clearly understood parts of the process, then turns to deep machine learning to optimize the lesser-understood variables. The alternative, the data-first approach, runs a computer algorithm to suggest the solution purely from data, without human input, and then relies on the human to evaluate the usefulness of the results. Modeling digital twins of wafers could enable automated process control, chamber matching, and fleet matching, says Fried. If every wafer had its own virtual twin with all the upstream metrology and structural information needed to make equipment control decisions, it could feed forward that information to enable the seamless transition from one step in the process to another based on understanding their complex interrelationships. This could potentially improve uniformity across wafers and equipment, and reduce the need for metrology, he argues. Moving metrology sensors into the chamber will also require model-based algorithms to enable dynamic process control in close to real time, says Fried. These algorithms will be needed to acquire, parse, and process the data at high speed, and then to choose how to adjust the controls. “There will be a model behind collecting and interpreting the metrology data,” he notes. “That’s a really rich vein for improvements in process control.” “The end goal is to collect equipment data in real time, analyze it with AI, and send back controls to optimize manufacturing processes,” Jabil’s Gamota says. “This requires a robust architecture for communication between equipment and consistent formats for data collection and analysis. But the cost and complexity of this heavy lifting is too great for any one company to do alone. We need a consensus-based architecture for ingesting, analyzing and acting on the data.” SEMI tests data transfer protocols, benchmarks best practices SEMI is launching a smart data project to identify the various data transfer protocols needed for inter-company communications. The project will feature a proof-of-concept model in a development fab to produce verifiable results so SEMI can better understand how different approaches meet member needs. SEMI’s smart manufacturing technology communities and the Fab Owners Alliance are also benchmarking current smart manufacturing practices in the microelectronics industry to help SEMI members better understand the path forward and potential return on investment. Speakers over all three days at SEMICON West addressing these issues include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org. What’s next for smarter, more connected electronics manufacturing - Part 1 What’s next for smarter, more connected electronics manufacturing - Part 2 Paula Doe, SEMI

What’s next for smarter, more connected electronics manufacturing - Part 2The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.” Process complexity drives demand for feed-forward between silos with computational models ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized. “We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says. So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,” notes Niesing. Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 1What’s next for smarter, more connected electronics manufacturing - Part 3Paul Doe, SEMI

The Scaling Technologies TechXPOT at this year’s SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00pm-4:00pm) will explore traditional scaling as the industry marches toward 3nm and beyond, as well as technologies that enable 3D architectures, die stacking, and interconnect scaling. The session will also provide an update on how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked Priya Mukundhan, director, Technology Development and Applications, at Rudolph Technologies, and a speaker at the TechXPOT, to provide her insights into challenges associated with metrology and inspection.For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way. Priya Mukundhan, director, Technology Development and Applications, Rudolph TechnologiesSEMI: What are the key challenges that need to be addressed to provide the kind of metrology and inspection solutions that will be needed by the industry as scaling – in all its forms (e.g., traditional, 3D ICs, interconnect, and different transistor architectures) – is pursued at 5nm and then at 3nm? Priya Mukundhan: With respect to metrology needed to scale FinFETs, the following will be key: Gate critical dimension (CD) at the fin sidewall, gate height, gate profile Fin CD, height and profile Dopant profiles Stress measurement in the fin Composition in thin film and interface These challenges are currently being handled using in-line CD solutions, CD scanning electron microscopy (CD-SEM) and CD atomic force microscopy (CD-AFM), along with optical critical dimension (OCD) measurements. There is no single technology that can take all of these measurements, and determining the right solution is application-dependent[1].Issues associated with inspection and scaling include the following: Bright-field inspection lacks the sensitivity to detect defects smaller than those found at the 20nm node Detecting defects that are 5nm or smaller is achieved using electron beam inspection tools, but these single-electron beam inspection systems are prohibitively slow and cannot meet the high-volume manufacturing (HVM) requirements for defect inspection Buried defects Void detection in 3D SiP structures, front and backside inspection Sidewall crack detection in packaging SEMI: Can you provide a summary of the R D roadmap for metrology/inspection tools that you see emerging in order to get to 3nm? PM: Hybrid metrology is currently in use, especially for CD metrology. To support the development efforts, techniques that provide complementary information as well as those that eliminate uncertainties will be required. Researchers at imec[2] have started exploring technology combinations to gain insight into how new structures function. Some of the findings in imec’s study include the following: The combination of transmission electron microscopy (TEM) and scanning probe microscopy (SPM) provides a unique approach of imaging combined with a functional analysis capability In situ SPM could potentially determine composition (SIMS) as well as functional properties (electrical) Fast Fourier transform scanning spreading resistance microscopy (FFT-SSRM) is a novel technique that measures carrier profiles in semiconductors. This overcomes the current SSRM limitations of signal distortions due to parasitic resistances while measuring on small volumes such as FinFET and nanowires Multi-electron beam inspection can be used for HVM for sensitivity to smaller SEMI: How will metrology and inspection be impacted beyond 3nm? What kinds of tools will be needed by that point in time?PM: There are several different transistor options that have been identified by leading edge wafer fabs and consortia looking beyond the 5nm node roadmap[3,4]. Some of the options on the table include the following: 1) Extension of the current FinFET in the form of gate-all-around FET2) Creating them with new materials by adding ferroelectrics (e.g., negative capacitance FET, or NC-FET) 3) Complementary FET4) Vertical nanowires and nanosheet FETsThese possibilities bring new challenges and require characterization at the material level. Also, the industry as a whole will have to redefine what it means to do composition at the nanometer level. This could be the beginning of a trend towards array-based metrology, i.e., measurements on an array of devices to gather statistically significant data[2].Regarding metrology needs at 3nm, it is too early to determine what kind of tools would be needed only for R D and how many of them would need to be extended to high-volume manufacturing (HVM). From an inspection perspective, there will be a continued migration towards computer aided design (CAD)-based inspection, as well as having the ability to deal with large image data sets (petabyte, big data). Furthermore, inspection algorithms should be improved, along with better staging for better image stitching.References Bunday, E. Solecky, A. Vaid, A. F. Bello, X. Dai, “Metrology capabilities and needs for 7nm and 5nm logic nodes,” Proc. Of SPIE, Vol. 10145, 101450G, pp. 1-41, 2017. Imec roadmap and imec magazine. Intel roadmap. https://semiengineering.com/transistor-options-beyond-3nm/ Debra Vogler, SEMI

The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Mary Ann Hockey, director for Advanced Emerging Lithography at Brewer Science Inc., and a speaker at the TechXPOT, for insights into the status of directed self-assembly (DSA) as it applies to the industry’s march to patterning for the 3nm node and beyond. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Mary Ann Hockey, director for Advanced Emerging Lithography at Brewer Science Inc.SEMI: What is the current status of materials development for DSA?Hockey: We are currently working with strategic customers to implement high-quality DSA chemical material solutions. We are both addressing near-term implementation of standard PS-b-PMMA block copolymers (28-30nm Lo) by leveraging our strategic partnership with Arkema, France, and building a library of high-chi block copolymers for long-term device requirements (Figure 1). SEMI: How do those developments prepare the technology for 5nm, 3nm or beyond?Hockey: We have engaged the strategy of engineering a library of novel high-chi block copolymer (BCP) platforms for next-generation DSA technology requirements of 3-5nm devices. One key objective is a global focus on easing implementation into a manufacturing environment. This objective requires large process windows for guided alignment (accommodating pitch and guide size target variability), minimizing BCP microphase anneal times (short anneal time supports high throughput), and streamlining the total number of process steps required for volume production (Figure 2).SEMI: How will industry’s use of DSA be intertwined with immersion lithography?Hockey: We envision immersion lithography as the foundation enabler with strategic use of optical lithography for generating consistent critical dimension (CD) sizes of DSA guides/templates for low cost of ownership.SEMI: What about the combination of DSA and extreme ultraviolet lithography (EUVL) to fabricate devices at 5nm, 3nm, and beyond?Hockey: EUVL and DSA can potentially work in harmony to support next-generation device technology. DSA can be made with the capability of lithography rectification or enhancing EUVL photoresist sidewalls and targeting low line-edge roughness and line-width roughness (LER/LWR) values.Debra Vogler, SEMI