Constant coverage of an invigorating topic like machine intelligence in the media often urges us to consider its use in EDA technology. As is often the case, there are many myths and falsehoods that consume our time and effort when trying to apply machine intelligence to EDA. This article aims to uncover the myths and to provide helpful advice on applying machine intelligence to your EDA project or product.Value PropositionFirst, there needs to be a clear value proposition for adding machine intelligence to an EDA product. Using machine intelligence to create a me-too product adds no value. EDA customers are too busy to understand or care about an EDA tool’s underlying technology. They just want to use the tool and get results. If the tool delivers value, if it delivers tangible benefits, then they’ll use it. Otherwise, they won’t.Currently, EDA tool developers are already experimenting with AI and machine intelligence without considering this fundamental truth – without a higher-end objective. AI must deliver something better or new, whether a speed advantage, a performance advantage, new features, new insights, or perhaps even something pleasantly surprising. Before you write a single line of AI-enhanced code, you need to clearly understand how AI will enhance the product. What is the value proposition?Use ModelThere’s a major barrier to customer adoption of AI and machine intelligence technology for EDA tools: EDA users are averse to make decisions based on probabilistic results. Instead, half a century of EDA tool use has conditioned them to expect deterministic outcomes from their tools.Back in 2003, a prominent visionary and EDA investor was quoted in an interview, saying: “If I open my eyes five years from now, all static analysis in VLSI will be statistical.” Many EDA luminaries have been proven wrong over time for betting that EDA users will accept statistical results. As enthusiastic as I am about using machine intelligence to improve EDA tools, I must urge caution based on the history of EDA failures that employed a probabilistic use model. Decision-makers and EDA tool users want to see deterministic answers to questions about yield or slack, not probabilistic ones.Our experiences at Paripath in developing the PASER (Paripath Accelerated Simulation Environment) tool also bear this out. We discovered that delivering results 50x faster but with 92% accuracy was simply not good enough for end users. EDA users only started to use PASER when its answers became 98+% accurate. To be adopted in the production flow, the tool had to deliver 99% accuracy.Data EngineeringThere are specific ways to achieve these accuracy goals. The first is data engineering. Machine intelligence is a new approach to EDA tool development and it needs to be trained on a data set. If the data is poor or incomplete, training will create an inaccurate model. Fundamental software-development rules still apply. Garbage in, garbage out.Without good training data, there’s no way for you to build good neural-network models. If you train a model with garbage data, you’ll get a garbage model. You must cleanse the data before you use it for training. Otherwise, the model will draw inaccurate conclusions and customers will not use your tool. The model is not to blame here. The model’s not wrong. The problem lies in poor data engineering, poor data cleansing, and a lack of discipline to prepare input data.High DimensionalityNext, machine intelligence has a unique ability to quickly solve problems of high dimensionality. Pure EDA problems often have high dimensionality. Over the years, EDA developers have perfected the art of segmenting the problems into sequencing solutions with lower dimension. Machine intelligence technology can handle problems with thousands of dimensions, but you need to be careful when tackling problems that have high dimensionality. Too many dimensions can produce confused or inaccurate results with AI and deep-learning technology.It helps to visualize the problem and to analyze the data set before using the data to train an AI-enhanced EDA tool. Several visualization methods can help. For example, t-SNE (t-Distributed Stochastic Neighbor Embedding) lets you reduce a data set’s dimensionality from a very large number to a much lower number. Figure 1 shows a high-dimension dataset with a dimensionality of 2000, which has been reduced to a low dimensionality of 3. Figure 1: Visualizing the Data Set with Lower Dimensionality Reducing the dimensionality of a data set to 3 using t-SNE and visualization allows you to quickly see whether the data set defines an easy or a difficult problem. If the problem is difficult, you’ll likely need to lower the problem’s and the data set’s dimensionality before using the data to train a neural network.Technology SelectionOne factor that determines whether it will be easy or difficult to incorporate machine intelligence into your EDA tool is your choice of AI development tools. AI researchers have developed a long list of frameworks, libraries, and languages that they use to develop AI and machine-learning software. Frameworks and libraries such as TensorFlow, Caffe and MXNet are most popular for developing deep-learning models.However, these tools are not yet popular with the EDA development community. The languages of choice in the EDA community are traditionally C and C++ for development and Tcl for prototyping and creating user interfaces. The rest of the software world has moved on to newer development languages such as Python, Java, R, and such. Moreover, machine-learning development segments into two distinct processes: training (i.e. generating the model) and inference (i.e. using the model).Another question to consider is where to generate the model – at the vendor site or the customer site?Consequently, fitting AI and deep-learning development into EDA development environments can feel like fitting a square peg into a round hole. You may need to create corners in your hole.EDA is a very small player in the overall software market. Relatively few software developers are familiar with writing EDA tools. It’s best to select AI and deep-learning development tools that can provide some sort of interface that’s compatible with EDA’s development tools of choice. Some AI frameworks have lower-level C and C++ interface layers that provide a familiar entry point for experienced EDA developers.At Paripath, we chose TensorFlow for exactly this reason. TensorFlow has a lower-level C/C++ interface. Although the resulting development path becomes a longer one using this approach, it’s a more familiar path for EDA developers and therefore it’s a path that can ultimately lead your EDA development team to success. An elaborate study of comparing these frameworks has been published in the book Machine Intelligence in Design Automation.Integration into Legacy SystemsWhen you understand the value that you expect machine intelligence to add to your new EDA tool, when you’ve cleansed and then analyzed the data set, and when you have selected an appropriate set of development tools, you’re finally ready to add machine intelligence to your EDA development. There are two use models for AI-enhanced EDA tools. The first uses a trained model to guide the EDA tool’s decision-making. In this use case, the trained neural network doesn’t change. The software’s accuracy doesn’t improve with use unless the company that developed the EDA tool retrains the underlying neural network. This use case follows the familiar, existing use case associated with EDA tools developed using deterministic algorithms.For the second use case, the end user is able to retrain the underlying neural network, which allows the EDA tool to produce better, more accurate results over time. This use case produces a win/win situation because end users are able to hone their tools and improve them over time, without help from the EDA tool vendor’s application engineers. If the retrained models are also sent back to the EDA developer for incorporation into newer versions of the tool, all users benefit from other users’ training data.It’s not clear how you’d support this second use case in the current EDA business environment where most data sets are proprietary and are carefully guarded. Most large EDA tool customers want to keep their data in house under tight control. Even with this somewhat restrictive situation, however, EDA tools benefit from the incorporation of machine intelligence because each EDA tool customer can customize the tool and improve its results.Machine intelligence has much to add to EDA tools’ capabilities. Only time will tell if the customers want and will accept these new capabilities. Rohit Sharma, founder and CEO of Paripath Inc., is an engineer, author and entrepreneur. He has published many papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna - an advanced characterization software for modern nodes. Sharma has written a book titled “Machine Intelligence for Design Automation.” You can download code examples and other information here.Note from SEMI-ESD Alliance: ESD Alliance’s Interoperability Committee brings together the industry to discuss interoperability. By focusing the efforts of the electronic system design community onto key compute operating systems, the Interoperability Committee seeks to define a stable, interoperable environment for tools and streamline the resources required to support these environments. The EDA Industry OS Roadmap presents guidelines to EDA vendors and customers for compute platforms to target for design starts. Learn more and view the OS Roadmap overview at our website.

This year, SEMI ISS covered it all – from a high-level semiconductor market and global geopolitical overview down to the neuro morphic and quantum level. Here are key takeaways from the Day 1 keynote and Economic Trends and Market Perspectives presentations.In the opening keynote, Anne Kelleher from Intel pointed to the huge growth of data, with fabs collecting more than 5 billion sensor data points each day. The challenge, Kelleher noted, is to turn massive amounts of data into valuable information. Moore’s law is not dead. New models of computing benefit still from Moore’s law and advances in Si/CMOS technologies for conventional, deep learning, neuro morphic and quantum computing.With customers expecting continual improvements in applications, the question is whether the chip industry is moving fast enough to meet these expectations, Kelleher said. A broad supply chain, equipment and materials innovations, and attracting the “best of the best” college graduates to fuel innovation is key, she said.In the economic trends session, Nicholas Burns (ambassador ret.) from Harvard University pointed out that we will see a major shift in power. The U.S. will remain the major world power over the next 10 years, but we will see a major shift in power in the next coming decades as the gap with countries like China, Russia and India continues to narrow.Duncan Meldrum from Hilltop Economics said that we are passing the peak growth of economic cycle. He warns that a more likely outlook is that a global growth recession is developing. Although semiconductor MSI growth will see a noticeable slowdown in 2019 and 2020, the semiconductor industry is still healthy over the longer term.Bob Johnson from Gartner sees demand shifting from consumer to commercial applications with higher ROIs and budgets. AI, IoT and 5D are the major enablers. He sees structural changes in the semiconductor industry especially for memory but also for Moore’s law with increasing costs and fewer players.The DRAM markets shows volatility and NAND market may be negative in 2019 but non-memory are expected to accelerate mainly because of increasing content and some price hikes.Overall Gartner expects good long-term growth with a CAGR (2017 to 2022) of 5.1%, outpacing 2011 to 2016 CAGR of 2.6%. After a strong 2018 with 13.4% revenue, he forecasts a slower 2019 with 2.6% growth followed by a 8% growth in 2020 and negative growth rate in 2021.Andrea Lati of VLSI went “Back to fundamentals” in his presentation about the industry. VLSI sees a downside bias due to slowing global economy, tariffs, and trade wars. Future drivers are data economy, cloud, AI and automotive.As memory leads the 2019 slowdown, analog, power, logic and other sectors remain in positive territory. VLSI lowered its semiconductor equipment forecast for 2018 from 20% (Jan. 2018) to 14% (Dec. 2018) but increased its sales outlook from 8% to 15% in 2018. VLSI expects revenue to slow into the first half of 2019 but increase to over 4% in the second half of the year, resulting in total 2019 drop of 2.7%. Semiconductor equipment sales are expected to drop from 14% in 2018 to -10% in 2019.Michael Corbett of Linz Consulting, covering wafer fab materials in the years of 3D scaling, sees these as good times for the industry. His outlook for wafer fab materials is bullish based on strong MSI and because wafer fab materials suppliers are getting bigger because of M As.In the Market Perspective session, Sujeet Chand of Rockwell Automation pointed out that as more and more data is generated, the problem is how to get value of all the data collected. There is a need to create the right architecture for machine learning and AI and big data is increasingly being replaced by contextual/structured data. He expects Industry 4.0 to drive foundries to become smaller, more flexible and more productive.In the Technology and Manufacturing session, Aki Sekiguchi of TEL addressed process challenges in the age of co-optimization. The semiconductor industry continues to expand, driven by massive growth of interconnected devices, with heavy demand for processing power and storage. He expects an exponential increase of data from about 40ZB in 2018 to 50ZB in 2020 to 163 ZB in 2026.Major technologies such as DRAM, 3D NAND and logic are dealing with scaling challenges. The density of DRAM (Mb/chip) is plateauing according to 2015 to 2020 trend data, with DRAM is in need of EUV. Memory capacity demand is leading to increasing layers and higher aspect ratios that is concern for 3D NAND and mainly for plasma etch. With Logic already implementing 3D structures, it appears to be in a solid position. Buddy Nicoson of Micron talked about his 50 years in the industry and looked ahead to the next 50. The anchors – quality, cost, scale and speed – won’t change. It has been a great journey so far with unprecedented opportunities and challenges ahead of us. We are getting into a convergence (specialization, integration) and solution-based phase. We will see some inflection points in the coming years, with the best yet to come.Christian G. Dieseldorff is senior principal analyst in the Industry Research and Analysis group at SEMI in Milpitas, California.

New SEMI Taiwan Testing Committee to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.Mobile, high-performance computing (HPC), automotive, and IoT – the four future growth drivers of semiconductor industry, plus the additional boost from artificial intelligence (AI) and 5G – will spur exponential demand for multi-function and high-performance chips. Today, a 3D IC semiconductor structure is beginning to integrate multiple chips to extend functionality and performance, making heterogeneous integration an irreversible trend. As the number of chips integrated in a single package increases, the structural complexity also rises. Not only will this make identifying chip defects harder, but the compatibility and interconnection between components will also introduce uncertainties that can undermine the reliability of the final ICs. Add to these challenges the need for tight cost control and a faster time to market, and it’s clear that semiconductor testing requires disruptive, innovative change. Traditional final-product testing focusing on finished components is now giving way to wafer- and system-level testing.In addition, the traditional notion of design for testing, an approach that enhances testing controllability and observability, is now coupled with the imperative to test for design, which emphasizes drawing analytics insights from collected test data to help reduce design errors and shorten development cycles. Going forward, the relationship among design, manufacturing, packaging, and testing will no longer be un-directional. Instead, it will be a cycle of continuous improvement.This paradigm shift in semiconductor testing, however, will also create a need for new industry standards and regulations, elevate visibility and security levels for shared data, require the optimization of testing time and costs, and lead to a shortage of testing professionals. Solving all these issues will require a joint effort by the industry and academia. "With leading technologies and $4.7 billion in market value, Taiwan still holds the top spot in global semiconductor testing market," said Terry Tsao, President of SEMI Taiwan. "When testing extends beyond the manufacturing process, it can play a critical role in ensuring quality throughout the entire life cycle from design and manufacturing to system integration while maintaining effective controls on development costs and schedules. Taiwan's semiconductor industry is in dire need of a common testing platform to enable the cross-disciplinary collaboration necessary for technical breakthroughs."The SEMI Taiwan Testing Committee was formed to meet that need, gathering testing experts and academics from MediaTek, Intel, NXP Semiconductors, TSMC, UMC, ASE Technology, SPIL, KYEC, Teradyne, Advantest, FormFactor, MJC, Synopsys, Cadence, Mentor, and National Tsing Hua University to collaborate in building a complete testing ecosystem. The committee addresses common technical challenges faced by the industry and cultivates next-generation testing professionals to enable Taiwan to maintain its global leadership in semiconductor testing.The SEMI Taiwan Testing Platform spans communities, expositions, programs, events, networking, business matching, advocacy, and market and technology insights. For more information about the SEMI Taiwan Testing platform, please contact Elaine Lee ([email protected]) or Ana Li ([email protected]). Emmy Yi is a marketing specialist at SEMI Taiwan.

SEMI and imec are joining forces to drive innovation and deepen industry alignment on technology roadmaps and international standards while adding technology depth to SEMI’s five vertical application platforms including Smart Transportation, Smart MedTech and Smart Data.Under a Memorandum of Understanding announced today at ISS 2019, the two organizations have set their sights on bringing together key industry players to advance cutting-edge technologies including Internet of Things (IoT), artificial intelligence (AI) and machine learning that enable new capabilities across healthcare, automotive and semiconductor manufacturing. The partnership also aims to speed the time to better business results for SEMI and imec members and partners. SEMI brings to the partnership access to the $2 trillion global electronics manufacturing supply chain and imec its global research and development (R D) and innovation leadership in nanoelectronics and digital technologies.Under the MOU, the two organizations will co-produce SEMI Think Tanks, extend SEMI’s International Standards platform to non-CMOS technologies, identify and fill gaps in technology roadmaps, and tighten imec’s engagement with SEMI in European workforce development efforts.Bettina Weiss is Chief of Staff at SEMI.

Region’s Fab Capacity Expansion Picks up PaceUnwavering in its drive to build a strong, self-sufficient semiconductor supply chain, China plans more new fab projects than any other region in the world from 2017 to 2020, and its expansion of fab capacity recently picked up pace on the strength of new foundry and memory projects from both domestic and foreign companies, according to SEMI’s 2018 China Semiconductor Silicon Wafer Outlook report. China’s installed fab capacity is forecast to grow at a 12 percent CAGR from 2.3 million wafers per month (wpm) in 2015 to 4 million wpm in 2020, faster than all other regions.Well known for its semiconductor packaging prowess, China in recent years shifted its focus to front-end semiconductor fabs and a few key material markets. In 2018, the region’s surge in fab investment thrust it past Taiwan as the second largest capital equipment market in the world, behind only Korea. However, China’s semiconductor manufacturing growth faces strong headwinds. Chief among them is the tight supply of silicon wafers over the past two years due in large part to the sector oligopoly’s firm control of global production, with the top five wafer manufacturers accounting for over 90 percent of market revenue. In response, China’s central and local governments has made the development of its domestic silicon wafer supply chain a key initiative, funding multiple silicon wafer manufacturing projects.According to the 2018 China Semiconductor Silicon Wafer Outlook report, many of China’s domestic silicon suppliers capably provide wafers 150mm in size and smaller. And the while the region lags peers in 200m and 300mm processing technology and capacity, strong domestic demand and favorable policies have fueled progress in 200mm and 300mm silicon manufacturing with some Chinese suppliers having reached key large-diameter manufacturing milestones.However, it will take these new suppliers several years before they can meet capacity and yield requirements of the larger-diameter silicon wafer market. Company plans and announcements indicate that by the end of 2020, total silicon supply capacity in China will reach 1.3 million wpm for 200mm, possibly leading to a slight oversupply, and 750,000 wpm for 300mm.China’s equipment suppliers, particularly crystal furnace vendors, are also investing in the development of 300mm wafer manufacturing, and domestic tool suppliers have developed most of the necessary tools for wafer manufacturing, except for inspection.While China’s silicon wafer suppliers continue to lag international peers in manufacturing capabilities, the region’s silicon manufacturing ecosystem is maturing and becoming better integrated. The sector’s growth is driven and accelerated by significant domestic market demand and favorable policies.About the China Semiconductor Silicon Wafer OutlookSEMI’s 2018 China Semiconductor Silicon Wafer Outlook is a comprehensive research report with a Microsoft Excel® workbook containing in-depth analysis of China’s silicon wafer manufacturing ecosystem as it relates to the global semiconductor wafer industry. The report covers the latest developments in China’s silicon wafer supply chain, including details on the rise of China’s silicon manufacturing, polysilicon, and silicon wafer-related equipment companies. The report also examines policies, funding and their implications for China’s silicon wafer supply chain.Clark Tseng is director in Industry Research and Statistics at SEMI.

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.Based on this work, the SCIS Seals Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).The second document published by the Seals Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)The Seals Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1. Figure 1: Elastomer seal test jig developed by the SCIS Seals Valves Group.The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.Figure 2 illustrates how the jig is connected to the gas sources. Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line. The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.Developing just a test jig is not sufficient. The Seals Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.At this point, the Seals Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.Currently, the SCIS Seals Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

I really don’t know clouds at all. – Joni MitchellThe semiconductor industry is finally on the cusp of joining the cloud revolution. The cloud has offered the promise of greatly expanded resources for years, but adoption has been slow due to lingering concerns. The biggest contributing factor for the concern over moving from on-premise EDA servers to cloud-based servers is, surprisingly, the rise of third-party IP. In the old days, if you were developing 100 percent of your own IP, and if you put that IP on a public cloud, and it somehow leaked out, well shame on you. That would certainly be bad for business. It might hurt your reputation a bit. But these days, with so much third-party IP being embedded into chips, if that third-party IP leaks out, that’s a lawsuit-fest in the making.Consequently, semiconductor companies now have even more incentive to protect IP with advanced security. Surprisingly, cloud-based security is far, far better than on-premise security. Why? Because keeping customers’ data secure is the central mission of cloud service suppliers, so they’ve developed a rich set of security tools to protect the data that’s entrusted to them by their clients. In many ways, you can maintain much better security in the cloud than you can with on-premise tools. Image credit: Markus Spiske temporausch.com from Pexels Amazon Web Services: Exemplifying the benefits of cloud computingTake Amazon Web Services (AWS) as an example. (Note: AWS is not the only vendor in the cloud space, but it’s one I’m very familiar with.)AWS has developed the concept of security groups – firewalls that you throw up around any network interface to allow only specific traffic into that secured network. You can do that for just one server or for a fleet of servers, in just seconds. Most on-premise server networks won’t let you work that quickly, or as easily, or with such fine control because most such networks lack the security tools to do this.In addition, AWS allows you to encrypt every bit of data stored on and flowing through its cloud-based storage systems. You can encrypt data at rest in on-premise storage but it’s a lot harder to encrypt data flying through the on-premise network. Amazon’s Elastic File System (EFS), a managed NFS file service, offers the ability to easily encrypt NFS traffic on the wire, a difficult feat at best with an on-premise solution.AWS built-in encryption key-management service can rotate encryption keys automatically. The cloud also allows you to have key policies that are easy to implement and maintain.Internal corporate networks rely heavily on perimeter firewalls for security. Perimeter defense just cannot deliver sufficient security against determined hackers and everyone realizes this. We’ve built big, open, on-premise networks that are just not well-suited to implementing adequate security protocols. Trying to retrofit these network architectures with additional security is time-consuming and costly, and it hurts engineering productivity. Moving to the cloud gives you a greenfield opportunity to right some of the wrongs of the past.Continuing with AWS as an example, here are some additional advantages of EDA in the cloud: AWS provides physical security that’s far above and beyond on-premise security. It doesn’t publish the physical locations of its data centers. It also has professional security staff 24/7, keycard access, and additional security features that far exceed typical on-premise physical security. AWS automatically manages security patches and access controls for their managed services such as database services. AWS gives you plenty of security tools to automate security processes, audits, and so forth to protect your data. AWS gives you so much flexibility that you can get yourself in trouble in you are not careful. If you want, you can create the same sorts of security holes that already exist with on-premise networks. You shouldn’t of course, but you can if you’re not thoughtful about things. You just need to hire the right people to implement and maintain your cloud security.Here are five very big differences between AWS (cloud-based) and on-premise server networking: Elasticity: Cloud-based systems enable you to scale up in minutes. That ability has pluses and minuses depending on how disciplined you are. On the plus side, you can quickly grow your EDA infrastructure as big as you want and then shrink it back down when you no longer need the additional capacity. All you need to do is tell the cloud service that you need more capacity and it will bring that extra capacity online for you in minutes – and will charge you for it. (That’s the minus side.) When you’re done, you can turn off the extra capacity (and stop paying for it) with the same speed. If you want to provision more EDA capacity for your on-premise network, you’ll need to beg, borrow, or steal existing capacity from someone else on your network, or you can order more servers, get the vendor to build and ship them, install them in your server room, provision them, and bring them online. That will take months. Fault tolerance: On-premise networks rely on large, monolithic service architectures, which saddle EDA vendors with more than 30 years of technical debt. The cloud operates on a different model, one that’s based on containers and microservices. This is inherently a redundant, fault-tolerant computing model if you write your code correctly. The difference between redundancy in the cloud and in on-premise networks is night and day. There’s no comparison. No private networks can match the available and growing redundancy of cloud systems, which have redundant servers inside of a data center and redundant data centers in multiple, worldwide geographic locations, which protects your data from natural and man-made disasters. Network segmentation: Many semiconductor developers have several design centers distributed around the world and there may be IP in use on a project that cannot be shared with certain geographic locations either by law or by contract. Cloud networks are already set up with automated tools for network segmentation that can enforce geography-specific rules through VPCs (Virtual Private Clouds), which are easy to set up. VPCs allow you to set up subnets with restrictions based on routing tables so that IP management and control become highly automated. Removal of single points of failure: The typical EDA grid configuration has several built-in single points of failure. For example, a central job dispatcher generally runs on one single node. If that node dies, all EDA work halts. The same is true for EDA license servers and for configuration-management and version-control servers. Again, because cloud networks are based on the microservices concept, the cloud simply doesn’t need to have the same single-point-of-failure vulnerabilities that on-premise networks have. On-premise networksTo get these same advantages with on-premise networks, the grid architecture must fundamentally be changed, starting with the replacement of NFS. EDA systems need to replace huge, monolithic file systems specifically developed for EDA with object storage. That's a tall order – one that requires the rewriting of fundamental assumptions that serve as EDA software’s foundation.In the 1980s, 1990s, and early 2000s, small EDA startups appeared to fill gaps in the offerings of the large EDA players. If they succeeded and grew, they’d eventually be gobbled up by a larger EDA vendor. That flowering of EDA startups seems to have damped down. The market has really matured.Next wave of EDA startups to offer cloud-first toolsGoing forward, I expect the next wave of EDA startups will be offering cloud-first tools that are not burdened by three decades of technical debt. They’ll be able to architect their tools specifically for the cloud.We’re starting to see this happen. For example, Metrics, a Canadian EDA startup, offers a pay-by-the-minute, cloud-based simulator and verification manager. Although one job on one cloud server might run slower than a monolithic simulator running an on-premise server, Metrics has architected its tools so that you can throw more servers at the problem, allowing you to run all of your jobs at once. Here, multiple simulation jobs running concurrently on multiple servers will ultimately finish faster than running the jobs serially on one slightly faster on-premise simulator.That’s the kind of innovation that we’re going to see. That’s the future of EDA.Derek Magill is executive director and president at HPC Pros. Derek has 20 years of experience supporting semiconductor engineering functions. His main focus has been in system architecture and technical management, but over the years he has been involved with technologies such as EDA licensing, ClearCase, HPC architecture, IP management and engineering software support. Derek spent 15 years at Texas Instruments in various technical and managerial roles. He is currently a senior manager, IT at Qualcomm managing the Global License Infrastructure team as well as the lead technical architect for the company's engineering cloud activities. The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, is the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. As an international association of companies providing goods and services throughout the semiconductor design ecosystem, it provides a forum to address technical, marketing, economic and legislative issues affecting the entire industry. The ESD Alliance also stages events that promote networking, learning and collaboration among member companies. To learn more about the ESD Alliance and how to join the group, visit www.esd-alliance.org or contact Bob Smith at [email protected].

We are living in a digital world where semiconductors are taken for granted, AI is bringing semiconductors back into the deserved spotlight, and now we are witnessing the dawn of the Cognitive Era enabled by semiconductors,” SEMI president and CEO Ajit Manocha said to an audience of more than 500 during his presentation – Rebirth of the Semiconductor Industry – at the First Global IC Entrepreneur Conference.Speaking at the Shanghai event in mid-December, Manocha recalled how, when he first entered the semiconductor industry in the 1980s, semiconductors revenue topped out at about $10 billion. Now, with sales having swelled to a staggering $450 billion, the industry is on a much faster growth track. Revenue could reach $500 billion by the end of 2020 and trillions of dollars by 2030. Over the past two decades, chips have given rise to social media and e-commerce powerhouses such as Google, Facebook, and Alibaba. All rely on heavily on chips, the engines of data centers across all industries. Wave after wave of technology innovation have been powered by semiconductors – from mainframe computers in the 1970s, personal computers in the 1980s, the Internet in the 1990s, and mobile and social networking in the early 20th century, to the current shining stars of technology such as IoT, big data, new memory, virtual reality, autonomous driving and artificial intelligence, Manocha said. New applications across areas such as smart manufacturing and digital healthcare are stoking the latest round of semiconductor growth.The rise of AI, like all the technologies before it, has renewed the semiconductor industry once again with its promise to drive growth of all industries worldwide, Manocha said. Five years ago, IoT was but a gleam in a technologist’s eye, more hype than reality with doubt about its viability running deep. Today, with about 60 percent of people in the world connected to the Internet, the enormous promise and potential of IoT is flowering. Industry growth will explode as the melding of AI and IoT birth countless applications and innovations in SMART transportation (0 emissions; 0 fatalities; 0 congestion), smart sensors (agriculture, infrastructure, healthcare) and SMART “Everything” (people, devices, homes, cities, industries, and the list goes on). Indeed, AI is now widely recognized as a chief growth driver of the semiconductor industry well into the future, with semiconductor technology at the core of AI innovation, he said. Semiconductors are thrusting the fifth industrial revolution into the fast lane. China’s much-anticipated rise as an industry powerhouse over the next few years will only accelerate industry growth, turning current disruptions into future opportunities as SEMI China continues to cultivate connection, collaboration and innovation in China’s fast-growing semiconductor sector.Cherry Sun is a marketing manager at SEMI China.

Five young dancers bathed in a striking rainbow of colors with their silhouettes cast in the background dazzled SEMICON Japan 2018 attendees at the opening ceremony in mid-December. Gone were the standard opening keynotes and ribbon cutting, replaced by live performance and media art set against a dramatic black backdrop. There was no mistaking the wide-eyed looks of wonder in the audience.In its sheer vibrance, the opening ceremony thrilled with an excitement that seemed to embody the extraordinary growth expectations for the global semiconductor supply chain over the next five years, with the industry poised to double sales from $2 trillion to a staggering $4 trillion – a phenomena SEMI president and CEO Ajit Manocha has called The Rebirth of the Semiconductor Industry. Driving this unprecedented growth will be SMART applications that are transforming industries and applications worldwide, powered by artificial intelligence (AI) and Internet of Things (IoT) technologies.The dramatic scene at SEMICON Japan 2018 was staged by Rhizomatiks, a media arts company that produced the Rio Olympic Games closing ceremony and is famous for its pop music spectacles. The company’s CTO, Motoi Ishibashi, the event’s first keynote speaker, described his team’s development of drones and vehicles guided by motion and precision-control technologies. It was some of these SMART vehicles that maneuvered the opening ceremony performers from the dance company Elevenplay onstage. Only Rhizomatiks, Ishibashi said, has this capability. In its mission to enrich people’s lives through new media arts, Rhizomatiks uses the latest virtual and mixed-reality technologies to orchestrate not only dance performances but music videos, commercials, fashion shows and festivals.Toru Nishikawa, the second keynote speaker and CEO at Preferred Networks, a leading Japan-based developer of deep learning software programs, surprised the SEMICON Japan audience with his discussion of his company’s work to develop a specialized chip for deep learning processing, joining technology giants Apple, Google, Alibaba and Microsoft in chip design. As more IT and software companies develop specialized, differentiated chips, the devices are quickly becoming the heartbeat of SMART technologies. The company’s approach has taken hold. Only four years old, Preferred Networks is enjoying rapid growth by working with global powerhouses including Toyota, NTT, Panasonic, Fanuc, NVIDIA, Intel and Microsoft. Ishibashi’s and Nishikawa’s fresh visions and the media arts extravaganza reflected the success of SEMICON Japan, held again at Tokyo Big Sight: The event’s 1,881 booths – filled by 727 exhibitors from 14 regions – was the highest count in six years. With Japan home to companies that supply about 40 percent of semiconductor equipment and materials worldwide, top suppliers historically have occupied the largest spaces on the SEMICON Japan show floor.According to IDC, personal computers and smartphones, long the largest revenue sources for the semiconductor industry, will remain top revenue drivers in the coming years. But revenue from new SMART technologies for applications such as automotive and factory automation is growing, a trend expected to continue with a 2018-2022 CAGR of 9.5 percent for automotive and 5.2 percent for manufacturing, compared to 1.1 percent for PCs and 2.9 percent for smartphones.SEMICON Japan’s new SMART Applications zone highlighted these and other new market opportunities for semiconductor growth with product and technology exhibits from companies including Bosch, IBM, Microsoft, NEC, Preferred Networks, Sony, SAS, Siemens, Tesla and Toyota. But the zone wasn’t all work and no play. The ROBOT SQUARE and SPORTS x IOT robot exhibits took visitors back to their school days, with robot anime – from Astro Boy to Gundam and Evangelion – that they could ride and control! As the World Gets Smarter, So Must SEMICON and the IndustryWe all agree the world is getting smarter at a fast pace. New cars are easier to drive – some models are almost fully autonomous on highways and streets. Your SMART speaker has gone well beyond an audio playback device and is more like a home AI platform. Almost all storefronts are equipped with video cameras. Your workplace, whether an office or a factory, is driven by automation. The reliance of these environments and devices on semiconductors is driving exponential chip and changing the world. Businesses need to adapt and so do SEMICON events. We’re doing just that as SEMICON Japan 2018 demonstrated – from an opening ceremony enabled by technology innovation to new faces of the industry to the SMART Application zone. As the SEMICON Japan presidents’ reception concluded the first day of the show, a robot from the ROBOT SQUARE suddenly appeared in the reception hall in front of about 250 executives from the global industry. Everyone at the reception was impressed and stepped forward to the stage, reflecting the overall excitement about SEMICON Japan, which for many years showcased only chip manufacturing equipment and materials. This year, to keep pace with the changing world, it was much more than that.SEMICON Japan 2019 will again take place in December at Tokyo Big Sight. However, organizers of the Tokyo Olympics will be using the East Exhibit Hall usually occupied by SEMICON Japan to prepare for the games. As a result, SEMICON Japan will be held in the West and South Halls instead. Look for more changes to the event. I hope to see you next year!Jim Hamajima is president of SEMI Japan.

Going to CES? Check out the demo by Saankhya Labs. They just announced the launch of their latest next-gen digital terrestrial TV demodulator chipsets, SL3000 and SL4000. As reported by The Times of India and many other media outlets, the chipset is part of the Pruthvi-3 series, and it's being manufactured on Samsung Foundry's 28nm FD-SOI technology. Saankhya Labs says they'll be sampling in the 1st Quarter of 2019. [UPDATE 9 January 2019: Per a press release issued at CES, the chipset was launched by ONE Media 3.0, LLC, a subsidiary of Sinclair Broadcast Group, and Saankhya Labs in collaboration with VeriSilicon and Samsung Foundry. This announcement follows Sinclair Broadcast Group’s recent commitment to a nationwide roll-out of ATSC 3.0 ("Next Gen TV") service and its past announcement to fund millions of chipsets giveaways for wireless operators. Sinclair is a major TV station operator in the US. The PR goes on to say that the demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option.] [caption id="attachment_13581" align="alignright" width="300"] (Courtesy: @SaankhyaLabs)[/caption] The Pruthvi-3 is an upgrade of Saankyha's Software Defined Radio (SDR) chipsets for Direct to Mobile (DTM) applications, which address video bandwidth congestion and other challenges, including internet access for the vast populations of rural users found in India and worldwide. (DYK half the world still lacks access!?) The company says the SL300x will be the industry’s first SDR-based DTV Demodulator that supports all the leading broadcast terrestrial, cable and satellite TV standards including the ATSC 3.0. The SOC is designed to deliver high performance and high throughput in static and multipath environments. A power-efficient, small footprint device, it targets DTV receiver applications such as digital televisions, set top boxes, home theatres and automotive entertainment systems. The SL400x – for mobile phones and tablets – is designed to be the most technologically advanced and highly-integrated single chip Mobile DTV Receiver in the industry. The full featured front-end SOC integrates UHF RF tuner, baseband DTV demodulator, FEC decoder, de-interleaver memory and Analog to Digital Converter (ADC) in a single chip. Here is a brief YouTube video of the company's CEO at the launch event, explaining why they see this chipset as a game changer. India Times reports that there are already 5 million of the chipsets in pre-order to companies in the US and China.