Today’s post is the last of four Q&A-style feature posts based on presentations during SEMICON West 2025’s “The Convergence of Semiconductor Manufacturing and Design” organized by the ESD Alliance (ESDA).
Bob Smith interviewed Joe Kwan, Director of Product Management from Siemens EDA, about his presentation, “3D Design Brings Multi-physics Requirements While Manufacturing Yield Improvements Require Digital Twin Modeling and Ingesting Design Data.” They covered a range of topics from partner collaboration and integrated design flows to digital twins, AI and more.
Smith: How does Siemens EDA define collaboration between design and manufacturing? What does that look like?
Kwan: Manufacturers and designers have been cooperating for a long time. The most familiar example is the design rule check (DRC) rule deck provided by the foundry to the design team. It enforces designers to adhere to the layout rules that must be followed for a design to be manufacturable.
What’s different now are new problems arising from the latest advances in technologies. Close collaboration is needed between the design team and foundry to identify and share data necessary for a successful final product. Foundries are challenged to encapsulate information that provides design teams with critical information for success without divulging proprietary data.
Smith: Can you elaborate with a few examples of what technologies you are referring to that are driving these new collaborations?
Kwan: Sure. A great example is the industry’s move from monolithic single chip solutions to chiplet-based solutions that require 2.5D, 3DICs, heterogeneous integration and the like. These approaches require multi-physics simulations to verify physical phenomena in ways that were not necessary when previously focusing on just a single chip design. Thermal, electrical and stress are not independent variables anymore.
Design teams need to understand how these effects come in to play with functionality, performance and other design specifications. Most important, they need to be aware of factors that could cause the chip or system to fail. To do this, close collaboration between all parties involved (design team, foundry and packaging) is required so designers know what to look for in their analyses and what to avoid. It adds a whole new layer of complexity necessary for getting to the finish line.
Smith: I imagine some scenarios that fit into what you are talking about. For example, if the design includes stacked die, the team will need to be concerned about heat distribution and potential hot spots in the stack.
Kwan: That is a good example. Heating problems cannot be overlooked. How does the heat escape from the stack? What is the thermal profile across the stack from the die on the top all the way through to the bottom of the stack. Is there a sufficient pathway for heat to get out?
We can do rough estimates early on to see if putting this die on top of this other one, is it going to work? Or be reliable? Back of the envelope calculations might show that the dies need to be positioned differently or even designed differently.
Smith: What can be done to improve design success?
Kwan: This is where collaboration comes in. The product owner should establish a cross-domain team of experts from chip design, package engineering and process engineering. The product spec and design decision trade-offs must be evaluated against impact to all domains.
EDA also plays a critical role. EDA is the link between designers, packaging and manufacturing. We hear and capture concerns from designers and package engineers. We prototype solutions, collaborating with packaging and IC manufacturers to encapsulate requirements for successful production.
Smith: At SEMICON West, we also talked about how design data can help foundries during the manufacturing flow.
Kwan: Yes, going back to our discussion at SEMICON West, I spoke about that important topic, which is embodying design data into the manufacturing platform in the context of a digital twin for virtual metrology.
In an ideal world, we would measure everything. If we could do that, we would have all the data needed to make perfect manufacturing decisions. But it would be extremely expensive. What we can do instead is apply AI virtual metrology. We collect the usual sparse metrology and then combine design data to train a predictive engine. The result is the ability to accurately predict where metrology was not collected.
With traditional process-of-record, foundries run a qualification wafer every 10 or so wafers. That’s very expensive. With virtual metrology, we can predict when drift becomes significant enough to blow up a wafer and you can intervene to restore individual nominal tool performance.
Smith: Engineers are writing their own agents to automate parts of the design flow such as analyzing the outputs of simulations.
Kwan: We see a lot of interest in AI and Agentic AI. There is a lot of potential to improve engineering productivity. But as we race to develop Agentic AI flows, we must also approach this in a rigorous manner that cross-checks to ensure accurate and robust results.
About Joe Kwan
Joe Kwan is the Product Director for Calibre AI/ML Fab Solutions at Siemens EDA. He has more than 30 years of experience in the EDA semiconductor industry. He previously worked at VLSI Technology Inc, COMPASS Design Automation, Silicon Access Networks and Virtual Silicon. Kwan received a Master of Science degree in Electrical Engineering from Stanford University and a Bachelor of Science degree in Computer Science from the University of California, Berkeley.
Robert (Bob) Smith is an independent consultant who has been involved directly in multiple roles in the EDA industry over the past 38 years. His career experience spans analog engineering, marketing, sales, business and strategy development and others including numerous c-suite roles. He holds a Master of Science degree in Electrical Engineering from Stanford University.
