Contamination Control: Enabling High Yield Manufacturing
New challenges and opportunities in process and design continue to emerge in parallel to ever shrinking semiconductor device geometries. While Moore’s Law is driving scale reduction, the industry is facing ever-increasing process sensitivity, integration challenges of new materials, and the need for unprecedented purity at process maturity. Today, with such increased process sensitivity and complexity, the industry is redefining on-wafer defect tolerance. Total wafer environment contamination characterization and control are essential for yield enhancement to ensure the success of the latest technology nodes. The key is to maintain process stability while controlling contamination. It is imperative to have improved defect detection, characterization metrology, and stringent quality across the process areas, including advanced filtration in place.
This tutorial provides an overview of semiconductor manufacturing defect sources, demonstrates proactive contamination control approaches, and highlights the need for collaboration across the supply chain in order to enable advanced technology yield enhancement. This tutorial is given with a focus on end user’s and supply chain partner’s perspective on the critical roles of chemicals, equipment, advanced filtration, and purification for controlling wafer-contamination.
- Ryan Pavlick, PhD, Filtration & Purification Technologist, Intel Corporation
- MaryTheresa Pendergast, PhD, Director of Engineering, Entegris
- Archita Sengupta, PhD, Sr. Technologist, Intel Corporation
The ASMC 2020 tutorial is sponsored through the generous support of Air Water Mach.