semiconductor manufacturing

Silicon carbide (SiC) has become a cornerstone of next-generation power electronics, driving advancements in electric vehicles, renewable energy, and industrial applications. After several years of rapid capacity expansion, the SiC industry is now entering a new phase focused on optimization, quality, and long-term scalability.This transition reflects a broader realignment across the global semiconductor ecosystem. As new fabs come online and supply chains mature, the industry is prioritizing stability, cost efficiency, and technical excellence over sheer capacity growth. SiC has moved from being a niche technology to a critical enabler of the energy transition, and this maturity demands not only investment in tools and materials, but also in process knowledge, cross-industry standards, and long-term partnerships that can sustain innovation at scale.To understand how this shift is unfolding, SEMI Europe spoke with Dr. Mark Puttock, Senior Director, Technology and Innovation at Entegris. Puttock shared his perspective on the industry’s evolution and how strategic collaboration and process innovation are shaping the next chapter of SiC manufacturing.From Ramp-Up to RefinementThe early growth of SiC manufacturing was driven by surging demand for high-efficiency power devices, particularly in electric vehicles. According to Puttock, that expansion period has given way to a new focus on yield, uniformity, and process control.The industry is entering a stage of maturity where success depends on optimization rather than scale alone. Improving consistency across crystal growth, wafer, and device fabrication is becoming just as important as adding capacity. This refinement phase calls for closer integration between materials science and manufacturing technology to ensure reliability and cost efficiency.A Focus on Process and Materials InnovationAs SiC moves toward high-volume production, challenges related to contamination control, defectivity, and wafer uniformity are taking center stage. Puttock noted that addressing these issues requires collaboration between materials suppliers, equipment manufacturers, and device makers.Efforts across the industry are converging on similar goals: enhancing purity, improving process repeatability, and developing new methods to enable larger wafer formats. Moving from 6-inch to 8-inch SiC wafers, for example, is widely recognized as a key step toward higher throughput and cost efficiency. Puttock emphasized that innovation in materials science and manufacturing technology must go hand in hand to support this scaling trend.Insights from Cross-Industry CollaborationA recent Entegris blog post featuring insights from Volkswagen Group Components and Porsche Consulting explores how SiC adoption is reshaping manufacturing strategies beyond the semiconductor industry. The post also highlights the strategy paper developed by Porsche Consulting in collaboration with Entegris. This joint effort demonstrates the value of aligning semiconductor-grade precision with automotive manufacturing demands. By sharing perspectives across industries, partners can accelerate best-practice adoption and strengthen the overall ecosystem for wide-bandgap technologies.Building a Sustainable FutureSustainability remains an integral part of this optimization phase. SiC devices themselves enable energy efficiency in end applications, but the way they are manufactured is equally important. Optimizing material use, recycling process consumables, and improving chemical delivery efficiency all contribute to a smaller environmental footprint. As production scales, attention to both performance and sustainability will be key to long-term success.Looking ForwardThe transition from expansion to optimization marks a pivotal moment for SiC manufacturing. Industry focus is shifting from building capacity to mastering control, quality, and resource efficiency. Puttock sees the future of SiC as one shaped by deeper digital integration, data-driven process development, and continued collaboration across disciplines. These advancements will help enable more consistent, sustainable, and cost-effective production—laying the foundation for the next generation of high-performance power devices.At the same time, Entegris continues to invest in materials science, contamination control, and advanced process technologies that help its customers overcome the complex challenges of SiC manufacturing. By combining technical expertise with a collaborative approach, the company plays an active role in supporting the industry’s transition toward more efficient and sustainable production.James Lam is Business Development Manager at SEMI Europe.

John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collaboration is the key to growing the semiconductor industry to $1 trillion and how we will get there.Smith: What is the major industry evolution or dynamic that's making collaboration essential today?Kibarian: The semiconductor industry has dramatically evolved from a simple, linear process to a complex, collaborative ecosystem. Previously, everything happened at the wafer fab. Testing occurred at wafer sort, package yields were high, final testing was straightforward, and products were shipped. Collaboration was mainly between foundries and fabless customers, intensive during early qualification and test chip stages, then evolved to routine yield monitoring once production stabilized.Today's advanced packaging puts multiple chiplets into single packages, creating an explosion of test insertion points. This has driven up both test complexity and costs significantly. Front-end fabs now house the most complex machines, while test and assembly facilities, once relatively simple, now feature sophisticated system-level testers with integrated robotics. Assembly tools have become highly complex, with die-attach processes requiring increasingly tight tolerances. Success now requires collaboration across the entire chain, from system companies to equipment vendors, both for new product launches and ongoing production maintenance.Companies are adopting AI and machine learning (ML) to manage these complex production flows, whether for testing or equipment control. This demands even broader collaboration since AI requires combining data from multiple sources across foundries, fabless companies, OSATs, equipment vendors, and more, data that no single entity controls. What was once a straightforward handoff between two parties has become an intricate web of interdependent relationships requiring continuous coordination.Smith: Chiplets and chiplet-based architecture is in the news and seems to be a key solution or practical solution in response to the slowing down of Moore's Law. This demands incredible levels of collaboration and coordination across the whole value chain. Is this doable at scale where it starts to move into the mainstream?Kibarian: The semiconductor industry will need unprecedented collaboration to make chiplet manufacturing work at scale. But this can be done! Consider EUV lithography: Initially expected during the 65nm generation, it took years longer than anticipated despite being an incredibly complex technology. Extraordinary engineering was needed but it also required extensive collaboration between ASML, suppliers, customers, and the broader fabless community.If the industry achieved this level of coordination for EUV, it can do the same for chiplets. However, chiplet manufacturing will require even greater collaboration as more companies will build systems using chiplets from multiple suppliers.Today's chiplet-based systems typically source all components from one manufacturer, making standards like UCIe less critical since companies control their entire supply chain. This will change as companies increasingly use third-party components for cost-effectiveness.More and more, we will see systems using components from multiple players to get to market more cost-effectively. Consequently, future production flows will be significantly more complex, requiring coordination of substrates and base dies, third-party dies and interposers, OSAT and specialized testers with specific configurations.This orchestration must work not just for initial bring-up but for the ongoing production as well, and when reconfiguring chiplet combinations for different products, all requiring rapid, automated responses.All of that must be automated for quick reaction. Considering the complexity of the manufacturing flow, people will want to apply AI/ML to anticipate what is going on in each individual product built.Manual oversight of every chip and package during manufacturing isn't feasible at scale. Automated AI agents must handle this monitoring and quality control. Expanding this automation will require close collaboration between the manufacturing entity and engineering teams at the product companies.This will also require a different level of alignment and orchestration across all the software packages managing this complex multi-company process. The financial enterprise resource planning (ERP) systems know where material is going, what the demand is, and what the forecasts are. While separately, the manufacturing execution systems needs to know which tools are going to be available when. Most often, these manufacturing systems operate in factories the product company doesn't own. The product company’s PLM systems control the bill of materials and test flows, but these tests will be conducted at the OSAT requiring complex coordination between the software systems of multiple companies controlling different process domains. This orchestration spans organizational boundaries and must be able to take data from upstream test results and make decisions on what tests to run downstream. This is required to get the right chiplets put together into a package in an efficient manner within a short cycle time and not require a Formula 1 pit team to keep everything running.Smith: The volume of data is staggering, especially now with design data. What will it take to enable this vision, at scale, where everything's connected? Kibarian: It’s a marriage of the human establishing the bounding box within which the systems operate that employ agents to do a lot of the work on a day-to-day or hour-by-hour basis. A good example is how manufacturing execution systems (MES) connect to ERP systems to share data. When a company sets up an orchestration, it creates rules that govern how information flows between systems. These rules tell the ERP system: "To calculate costs for each process step, here's the recipe information you should use."Once these rules are in place, they work like guidelines that control daily operations. An AI agent automatically creates insights based on actual data collected from the MES and moves data between systems according to these rules. The ERP AI agent will use this data to spot when costs are rising and send alerts, to notice when production yields drop, to calculate what lower yields mean for costs, and will take action to fix problems.This same process happens between equipment suppliers and manufacturing facilities. They share data automatically based on pre-set rules, and AI helps identify issues and take corrective action. Fabs determine who can access which machines and when, what types of data can be transmitted and through which channels, and how frequently these transmissions occur. When new software or AI models are introduced to run equipment, the systems specify what virus scanning and security checks must be completed before installation.Human operators primarily configure these control systems by determining the most effective collaboration protocols. However, the day-to-day execution is handled by automated agents due to the enormous scale involved, both in terms of data volume and the sheer number of transactions that occur continuously throughout operations.A human will not go through and review that data. I'll give two examples of this. One outside of our industry and one in our industry. At our 2019 user conference, board member Marco Iansiti, a Harvard Business School professor, shared insights from his book on AI in business. He compared traditional banks with Ant Bank, Alibaba's banking arm, which was experiencing explosive growth before Chinese government intervention.Ant's AI wasn't particularly sophisticated, but its process was revolutionary. While traditional banks require customers to fill out loan applications that then go to human loan officers for review, Ant's system would automatically scrape the internet and social media to verify applicant information. Within seconds, an algorithm would approve or deny the loan.The crucial difference is that Ant could scale exponentially because its only constraint was computing power. Traditional banks need to hire more loan officers to double their business, a human bottleneck that limits growth.I invited him to speak because I believed in this principle six years ago, and I'm even more convinced now.For the semiconductor industry, to build a trillion-dollar industry with complex, integrated systems, we need to minimize human intervention in data intensive processes. Despite the trust issues between stakeholders in our sector, collaboration remains essential. The solution requires establishing systematic principles that allow AI agents to operate autonomously. This is a way forward to achieving exponential growth.The Ant Bank example perfectly illustrates what our industry needs. At PDF, we believe this approach is crucial for industry advancement. Consider this: We manage petabytes of data, yet humans only examine 5-10% of it. This shows AI's potential to handle the vast majority of operations without human oversight.The reality is that our customers build millions of chips a week, billions a year. They cannot look at every dataset. Algorithms can, AI can. We launched a product called Guided Analytics last year. An engineer spoke about it during our user group last year. Her company has a couple of thousand products. Her group could not keep track of them every day, but Guided Analytics could. When her group came in the morning, the daily report noted 90% of the chips were fine or alerts pointed to where issues are. It's a simple AI bot crawling over data and identifying where the root cause seems to be.Our industry will require more agents to scale. Those agents will span the industry, and yet we as humans need to set up the governing principles under which they can operate. That's how we're going to deal with the massive amounts of design and manufacturing data to get the velocity the industry will need, and to benefit from the AI that we create for our businesses.Notes: Kibarian’s keynote, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” is scheduled for Wednesday, October 8, at 10:20 a.m.SEMICON West adds design to its program with “The Convergence of Semiconductor Manufacturing and Design” to highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session will be held Tuesday, October 7, from 1 p.m. until 4 p.m. Learn more about the design program in our latest blog. SEMICON West 2025 will be held in Phoenix, Arizona from October 7-at the Phoenix Convention Center. SEMICON West’s homepage has links to the full program, including more details about “The Convergence of Semiconductor Manufacturing and Design,” special features, sponsor and exhibits. Registration is open. About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

How Cool is That - Northrop Grumman’s “World’s Fastest Microchip” won the 2024 “Coolest Thing Made in California” contest, organized by the California Manufacturers Technology Association (CMTA). Public votes were cast for 138 California-made products in four rounds, culminating in this microchip—boasting speeds up to 1 terahertz—being crowned the winner. Manufactured in Redondo Beach, CA, the chip is 1,000 times faster than smartphone processors and represents California’s cutting-edge manufacturing sector. The contest and award ceremony were celebrated during CMTA’s MakingCA Conference, honoring manufacturing’s $310 billion contribution to the state’s economy. Doing the Green Wave - NIST scientists have successfully created a compact, full-spectrum laser covering the green-yellow-orange wavelengths, long considered challenging to produce. Traditional semiconductor lasers struggled with green wavelengths due to material limitations, so NIST turned to nonlinear optics, producing different wavelengths by adjusting silicon nitride device geometry and laser input. This breakthrough enables more precise, pure wavelengths ideal for quantum computing, medical devices, and underwater communications. Their method combines pump laser tuning and device adjustments, achieving 150+ wavelengths, demonstrating a significant advancement in accessible, high-quality lasers.Source: NIST’s Compact Green Semiconductor Laser - IEEE SpectrumEnergy Hero - At the 2024 ITF World conference, AMD CEO Lisa Su spotlighted a new goal: a 100x boost in computing efficiency by 2027. As shrinking transistor sizes yield diminishing returns, materials innovation has become essential for boosting performance and efficiency. Applied Materials has responded with advanced materials engineering solutions, harnessing exotic elements and 3D chip designs to improve efficiency. For instance, Applied’s Integrated Materials Solution™ combines six process technologies to reduce chip wiring resistance by 25%, a critical advance as semiconductor nodes shrink to the atomic scale. These methods promise breakthroughs in power efficiency across AI, personal electronics, and more. Building Automation of the Future - Imagine a future where every device in newly built structures— from HVAC systems and appliances to light switches and sensors—is equipped with a microprocessor and linked through a reliable communication network. This could transform how buildings operate, yielding substantial benefits across various sectors. Chip manufacturers would see new growth opportunities, while builders could offer smarter, more efficient homes. Consumers would gain convenience and comfort, as buildings could dynamically adjust to personal preferences and real-time needs. For instance, rooms would automatically adapt their temperature as people move through them, making manual thermostat adjustments obsolete. This automated approach wouldn’t just create a more comfortable environment but would also optimize energy use, potentially lowering costs and benefiting the environment.Source: Building Automation of the Future - EE TimesDo you have a fun fact to share? We invite SEMI members to share fun facts about the industry or their company. We’ll consider your tidbits for inclusion in future blog articles and or posting on social media. Complete our survey form or email [email protected]. Learn more about the SEMI Foundation and its initiatives to promote industry awareness and help provide a path for those interested in rewarding careers in microelectronics. Follow the SEMI Foundation on LinkedIn, Instagram, X and Facebook. Margaret Kindling is Senior Program Manager for Diversity, Equity, and Inclusion at the SEMI Foundation. She promotes inclusion and belonging via Women in Semiconductors, Semiconductor PRIDE and SEMICON West Workforce Development Pavilion programming.

In the rapidly-evolving semiconductor industry, maintaining a competitive edge is crucial. To position Europe at the forefront of global semiconductor innovation, imec is leading the NanoIC pilot line initiative. Aligned with the European Chips Act, this initiative is a strategic move to bolster Europe's leadership in key markets like high performance computing, automotive, and healthcare.SEMI spoke with Srikanth Samavedam and Jo De Boeck from imec, Belgium, to learn more about the NanoIC pilot line and to better understand its goals, challenges, and prospects. From transitioning to gate-all-around (GAA) nanosheet devices, to developing advanced memory technologies and interconnects, this conversation highlights the cutting-edge advancements made possible through collaboration across the industry’s value chain.SEMI: How is the NanoIC pilot line working to revolutionize the semiconductor industry, and what are its main objectives?Samavedam: The NanoIC pilot line is a European initiative aimed at bridging the gap between R D and industrial innovation. The project is creating a beyond-2nm system-on-chip (SoC) pilot line, developing advanced logic, memory, and interconnect technologies. This effort supports the European Chips Act's vision for leadership and competitiveness in global semiconductor innovation, particularly in critical markets like high performance computing, communication, automotive, energy, and healthcare. However, advanced technologies come with more complexity, and addressing these complexity challenges requires more mature module baseline flows. By improving baseline flow repeatability and variability while reducing defectivity, we can accelerate the development of future technologies. The NanoIC pilot line is working to provide access to these advanced technologies and baselines to develop future compute systems. This will help ensure European competitiveness across the industry – from semiconductor materials, equipment and design to systems and applications.SEMI: Who are the core partners involved in this initiative?De Boeck: Key partners of the pilot line include CEA-Leti, Fraunhofer-Gesellschaft, VTT Technical Research Centre of Finland, Tyndall National Institute, and the Center for Surface Science and Nanotechnology of the University POLITEHNICA of Bucharest. This project is also supported by the Flemish government, other participating states, and the Chips Joint Undertaking of the EU Chips Act.These institutions and organizations bring a wealth of knowledge and resources, and imec compliments their efforts by providing access to its global partnerships with key industry leaders. The NanoIC pilot line is helping strengthen Europe’s global semiconductor industry leadership while aligning efforts with other regional Chips Acts. SEMI: Can you elaborate on the significance of transitioning from field-effect transistors (FinFETs) transistors to GAA nanosheet devices in CMOS technology?Samavedam: The transition from FinFETs to GAA nanosheet devices is a significant advancement in CMOS device technology. FinFETs have been the backbone of CMOS technology from the 22nm to the 3nm node. But starting at the 2nm node, nanosheet devices will need to be introduced. Nanosheet devices, including variants like Forksheet devices, are expected to drive scaling and performance through three generations – 2nm, A14, and A10. Complementary FET (CFET) architectures are also expected to be introduced around 2031 at the A7 node, which will represent another major inflection point in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities using high numerical aperture extreme ultraviolet (high NA EUV) lithography – all of which will be implemented on the NanoIC pilot line. FIGURE PROVIDED BY IMEC │ SCHEMATIC ILLUSTRATION OF A FUTURE COMPUTE SYSTEM. THE SYSTEM IS MADE OF LARGE MULTI-DIE ELECTRICAL-OPTICAL INTERPOSER PROVIDING ELECTRICAL AND OPTICAL INTERCONNECTS BETWEEN THE VARIOUS CHIPLETS (CPUS, GPUS, HBM). ALSO SHOWN ARE CONNECTIONS TO PACKAGE SUBSTRATE, AS WELL AS FIBER CONNECTORS AND AN INTEGRATED LASER SOURCE. CENTRAL PROCESSING UNIT (CPU); GRAPHICS PROCESSING UNIT (GPU); HIGH BANDWITH MEMORY (HBM); PROCESSING UNIT THAT CAN INCLUDE CPUS, GPUS, AND OTHER SPECIALIZED PROCESSORS (XPU); APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); ELECTRONIC INTEGRATED CIRCUIT (EIC); FF-LEVEL: FEMTOFARAD-LEVEL; FIELD-PROGRAMMABLE GATE ARRAY (FGPA); GAAS QD: GALLIUM ARSENIDE QUANTUM DOT; INTEGRATED SILICON PHOTONICS PLATFORM 300MM (ISIPP300); REDISTRIBUTION LAYER (RDL); SILICON PHOTONICS (SIPHO); THROUGH PACKAGE VIA (TPV). SEMI: What are the key innovations necessary for advancing memory technology?Samavedam: As SRAM scaling slows, the exploration of novel, dense embedded memory concepts will become imperative. Technologies like spin orbit torque magnetic RAM (SOT-MRAM) and 2-transistor 0-capacitor (2T0C) embedded DRAM using deposited semiconductors like indium gallium zinc oxide (IGZO) are promising. These innovations address memory capacity and bandwidth challenges from new workloads in compute systems. Additionally, developing a 3D memory platform to explore future memory options will be essential for improving SRAM and DRAM. These advancements will help meet the demands of new applications like machine learning, augmented and virtual reality, and autonomous vehicles.SEMI: How do advanced interconnect technologies contribute to the future of semiconductor design?Samavedam: Advanced interconnect technologies, like chip-to-chip lateral (2.5D or interposer technologies) and vertical interconnects (3D technologies), play a crucial role in addressing memory capacity and bandwidth challenges. These technologies enable the partitioning of SoC functions into separate dies, allowing for more efficient and scalable designs. Advances like pitch scaling of micro-bumps and copper (Cu) hybrid bonding are facilitating this fine-grained partitioning of SoC functions. Additionally, optical interconnects and 3D interconnect-enabled co-packaging provide high-bandwidth and low-power connectivity at wafer scale. The rise of chiplet architectures and standardization will also increase the demand for low-cost, tight-pitch interconnect technologies like Cu/polymer redistribution layers.SEMI: How do your collaborators benefit from the NanoIC pilot line? De Boeck: One of the biggest collaborator benefits is the pilot line’s commitment to knowledge sharing through R D access and training. We invite foundries, IDMs, materials suppliers, equipment suppliers, and system companies/OEMs to jointly develop the materials, process modules, and integration flows to accelerate the development of beyond-2nm SoC technology pillars.Design pathfinding and system exploration process design kits (PDKs) will be available for start-ups, small- and medium enterprises, universities, and design and system companies to aid in prototyping and testing their designs. The NanoIC pilot line will also offer comprehensive training programs, including virtual PDK training, bootcamps for faculty, and internships and expert courses for students. To learn more, experts and key partners of the NanoIC pilot line will be presenting from 14 -16:40 at SEMICON Europa on November 12. imec’s program, ITF Chip into the Future, will highlight advancements in digital technology, capacity building through the European Chips Act, and the role of the NanoIC pilot line in accelerating beyond-2nm innovation. The conversation will also address industry requirements for pilot lines, emerging initiatives boosting Europe’s innovation and competitiveness, and perspectives on advanced materials and semiconductor equipment. Srikanth Samavedam, Senior Vice President of Semiconductor Technologies at imec, oversees programs in logic, memory, photonics, and 3D integration. Previously, he was a senior director at GlobalFoundries, leading 14nm FinFET technology into production and developing 7nm CMOS. Starting his career at Motorola, he worked on strained silicon and other advanced materials. He holds a Ph.D. in materials science and engineering from MIT and a master's degree from Purdue University. Jo De Boeck, Executive Vice President and Chief Strategy Officer at imec, oversees the company’s strategic direction and serves on its executive board. He joined imec in 1991 after earning his Ph.D. from KU Leuven and has since held various leadership roles, including head of imec’s Smart Systems and Energy Technology business unit and CTO. De Boeck is also a part-time professor at KU Leuven. Maria Daniela Perez / Communications Manager, SEMI EuropePhone: +49 160 2562977Email: [email protected]

Use of machine learning and artificial intelligence (ML/AI) is on an exponential rise across fields1 including all aspects of the semiconductor industry. In the last decade, the use of ML/AI exploded in the areas of speech recognition, facial recognition, smart phone features, search engines and now large language models like ChatGPT, Bard AI, and CoPilot. The ML/AI growth has been enabled by massive data storage capacity and increased compute performance, leading to projections for the semiconductor industry to reach over $1 trillion in annual revenue by 2030, with about 50% of the industry’s growth related to GenAI2. Figure 1: McKinsey Company on GenAI driving semiconductor industry growthAs semiconductor manufacturing drives toward Industry 4.0, SEMI member companies have a vision of Industry 5.0, truly adaptive manufacturing, integrating human creativity with robotic precision enabled by AI. Along that path, automation and data exchange in every step of manufacturing is essential, with data acquisition, data integrity and relevance, and operational Digital Twins3 as defined steppingstones to the factory of the future.Based on growing member interest in ML/AI, in 2019, SEMI assembled technology communities that quickly engaged in AI discussions and proofs of concept, discovering gaps in the path to Industry 4.0. Successful demonstrations of the value of AI in chip manufacturing process development and factory efficiency, not to mention GenAI uses in society, hastened the pace to produce faster, more powerful chips to accommodate the computation and communication requirements. Recognizing the industry opportunity and the mounting role AI plays in the semiconductor supply chain, SEMI initiated several thought leadership efforts, namely the Smart Manufacturing Initiative, Smart Data-AI Initiative, and the Future of Computing think tank.Smart Manufacturing According to the SEMI World Fab Forecast, over 100 new and expanded wafer fabs will begin volume production by 2027. This massive capacity expansion will need to achieve the highest possible operational efficiency and performance. To this end, the Smart Manufacturing Initiative is a technology community with over 120 member companies collaborating pre-competitively to transform manufacturing. The SEMI Smart Manufacturing Global Executive Committee (GEC), outlined a roadmap vision for the cognitive factory of the future based-on technology, sustainability and future talent. The GEC has been working with members to realize that vision. Figure 2 describes this vision in terms of the technology progression needed and the approximate timeline for implementation by most manufacturers. The proliferation of this vision through Smart Manufacturing Forums at SEMICON events around the globe, newsletters and blogs has garnered enormous interest and participation in the initiative and is central to the mission of connecting and raising awareness within the ecosystem. Figure 2: AI-Driven Smart Factory (Point Systems to Autonomous Solutions) To move the needle on this vision, industry experts in the initiative successfully created and launched the Industry 4.0 Readiness Assessment Model (IRAM) to help assess technology deployment progress. IRAM adoption is steadily growing. Modern front-end and back-end lines produce an extraordinary amount of multi-modal data from a variety of sources, and this is key to success in unlocking the potential of AI in manufacturing environments. The initiative’s global working groups on Data Architectures and Smart Control Room among others are working towards a holistic Cognitive Factory framework uniting the vertical and horizontal flow of information. Integral to the Cognitive Factory are smart manufacturing standards, that will accelerate the vision outlined above, and without which local solutions are unlikely to scale.In 2023, the Smart Manufacturing Initiative brought together industry leaders in a unique Digital Twin workshop to align on the state of semiconductor development and usage. The key takeaways from this workshop are captured in a white paper that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months. that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months.The GEC has identified critical interrelationships in addition to the technology focus. At the intersection with sustainability, the initiative has formed a collaborative task force with the SEMI Semiconductor Climate Consortium (SCC) to develop a bottom-up technology roadmap that can be used as a blueprint for device makers to meet their proclaimed sustainability goals faster. The task force organized a technical session at SEMICON West 2024 and will be releasing a white paper in the near future. Similarly, the initiative is working with the SEMI Foundation to identify necessary future skills and to make training available through SEMI University. Smart Data AI – Applying AI to Semiconductor OperationsSEMI’s Smart Data-AI Initiative started by assembling a group of interested companies to explore the pivotal role AI could play in the industry and to address the criticality of data. All stakeholders agreed that a formidable challenge was (and still is) the integrity of that data and the security of sharing that data, which is considered IP to most. The optimal implementation of ML/AI techniques can only be gained by access to the comprehensive data set which is owned by numerous supply chain partners. Consequently, semiconductor R D, process and design have not yet realized the full benefit of Data-AI advances. In response, the initiative developed a framework to create value for members and support industry progress. Four pillars underpinning the strategy are:Educating stakeholdersBuilding communitiesExecuting proof-of-concept projectsDeveloping industry standardsTo explore the data challenges the subject matter experts highlighted, a collaborative proof-of-concept (POC) project was proposed in 2019 and accepted by the initiative's partners at Army Research Laboratories4 along with academic and industry partners. The project has completed two phases and is starting on its third phase under the expert guidance of an Industry Advisory Council (IAC) comprised of leaders in the Smart Data-AI community.The POC project, being conducted by principal investigators at Cornell University, demonstrated significant accomplishments from the first two phases, including:An AI model to predict device geometry by optimizing photolithography and plasma etching processesInitial demonstration of secure data-sharing techniques with software-hardware co-optimizationInnovative metrology ideas to train AI algorithms rapidlyStudents trained in cross-disciplinary skills to address the industry’s critical talent shortageFurthermore, the visionary objectives laid out at the initial stages of the POC proved to be synergistic with the strategic goals of the CHIPS Act5, which articulates the need for “collecting, aggregating, and sharing data sets that enable benchmarking and operational improvements, tools development, the creation of digital twins, and training AI models,” and that “the NSTC could develop a methodology for the voluntary sharing of data that protects the proprietary component and national security while enabling access to appropriate performance data.” Phase 3, to be completed by August 2025, will advance the state-of-the-art toward the following specific objectives:A framework to create and integrate Digital Twins of semiconductor R D and manufacturing process toolsAbility to explore processes and generate virtual devices swiftlyDefined interfaces to combine models for each process module or toolAccurate AI-based models for executing virtual process flows to build virtual devicesAdvanced solutions for secure data-sharing across the ecosystem – for example, federated learning where raw data is protected for each entity by building models locally, and only the outputs of the local models are used to build flow-level AI modelsFoundation for future industry standards for secure data-sharing and for interfaces in the virtual innovation environmentSEMI continues to build the collaborative community for Data-AI and strives to synergize with broader efforts such as the Digital Twin Manufacturing Institute, NSTC, and NAPMP in the U.S., and international standards development. Smart Data AI – System-level Innovation for AI – Future of ComputingThe cross-collaborative and synergistic objectives of Smart Manufacturing, the Smart Data-AI proof-of-concept work, and SEMI Standards merge to advance the state-of-the-art. The objective is to help members realize the full value of technology and innovation. In addition to improving semiconductor operations using AI, the efforts also strive to enable SEMI members to participate in, and ultimately profit from, market growth opportunities. Continued progress in AI is crucial both for the industry’s march towards $1 trillion in annual revenue, and for continuing to realize AI’s benefits to society.There are some hurdles to overcome in such a dynamic market. AI models, and the data they process, are outpacing hardware advances, posing a major roadblock for continued progress. As GenAI becomes more pervasive, the performance and power challenges continue to multiply, and require significant innovation in both hardware and software. While individual companies will develop competitive products in this domain, the entire ecosystem needs to evolve in a synergistic manner. As a global industry association, SEMI can play an important role in ensuring this. SEMI started a series of workshops and technology sessions to develop the community and identify opportunities and challenges. The first in this series was a joint workshop with McKinsey Co., held in October 2023, with a focus on innovations in “Domain-Specific Architectures.” Strategically, it brought together thought leaders from three diverse communities - start-ups, investors, and SEMI member companies across the supply chain. This was followed by an overcapacity audience at the Future of Computing session at SEMICON West 2024, where we explored AI-specific hardware with leaders in academia and industry. The Initiative’s next planned event in October 2024 is a focused workshop that is designed to be highly interactive and bring together visionaries and thought leaders from across the value chain – materials, devices, architectures, algorithms, and critical enabling technologies such as photonics, chiplets, advanced packaging, and 3D and heterogeneous integration. The overarching goal is to identify pre-competitive collaborative actions that would help the entire industry. The “Future of Computing” is the broad path to the industry’s future success. While AI systems are the current major wave on this path, future waves may be about heterogeneous integration of photonics and other components, and ultimately, quantum technologies joining the mainstream. SEMI continues to monitor these future trends, strengthen the ecosystem and enable innovation through pre-competitive collaboration, and accelerate implementation through standards.SEMI is fostering today’s collaborations while helping the industry navigate the future of electronics.Melissa Grupen-Shemansky is CTO at SEMI, Pushkar Apte is a Strategic Technology Advisor and Leader of the SEMI Smart Data-AI Initiative, and Mark da Silva is Senior Director of the SEMI Smart Manufacturing Initiative.Definitions and References:1https://arxiv.org/abs/2405.15828 Eamon Duede, William Dolan, Andre Bauer, Ian Foster, Karim Lakhani2McKinsey Company3Digital Twins for semiconductor manufacturing operations are dynamic, predictive, data-driven virtual models of a physical asset, process, or an entire factory, constantly synchronized with its real-world counterpart through real-time data streams and analytics4Research was sponsored by the Army Research Laboratory and was accomplished under Cooperative Agreement Number W911NF-19-2-0345. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Laboratory or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.5“A Vision and Strategy for The National Semiconductor Technology Center (NSTC)” published by the CHIPS R D Office.

John Kibarian, CEO and founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, is a keen observer of the semiconductor ecosystem. Since PDF Solutions sits between design and manufacturing, Kibarian shared unique perspectives on both in a recent discussion.Smith: What trends are you seeing in the semiconductor industry. Are there any that surprise you? Kibarian: We see several trends that have been going on for quite a while.As much as we hear Moore’s Law is dead, there's still a strong drive to get to advanced nodes. The benefits are harder to achieve and require more than geometry scaling, but demand for these advanced nodes continues to grow. Another emerging trend is the need for insatiable compute power in data centers to support the explosion in AI applications. In recent history, the mobile phone market has been the key driver of the push to new advanced nodes, but that is changing as the performance needs of data centers and AI applications are now driving the shift.Next, as companies are still learning from the disruptions in the supply chain due to the pandemic, there’s a tremendous amount of movement to make the supply chain more resilient by expanding sourcing options for critical products or test applications. This is happening in conjunction with significant investment in high-performance compute from many countries that want to bring silicon to their shores.The next trend is that electronics companies are looking to limit investing solely in China or the U.S. Their China Plus One or U.S. Plus One strategies results in adding significant additional infrastructure and overhead. If it's not done right, it will cost the industry more money. It will be hard to sustain the cost benefits and economies of scale of the current single source model just by brute force and adding human capital. A new approach is required to manage cost effectively smaller and globally distributed manufacturing facilities.The final trend is the general electrification of the economy. Cars are moving from internal combustion engines to electric. That means more and more of our energy needs are met with electricity, putting a premium on solar and batteries. Batteries require power conversion.Silicon such as high bandwidth semiconductors on silicon carbide and gallium nitride have a tremendous amount of capacity. What is interesting is how fast and aggressive China is in that part of the market; they could be a major producer of the technologies needed to support electrification. With our exposure to the China market as well as the European and U.S. markets, Chinese manufacturers have come up quickly, and we may see a world with more viable suppliers than originally anticipated.Smith: You mentioned data centers and AI. AI is everywhere and revolutionizing the semiconductor industry. EDA companies are talking about incorporating AI. What are you observing? Kibarian: AI is used for chips that are manufactured for use in data centers. For example, our customers use PDF analytics or the Exensio platform via the cloud to analyze large amount of manufacturing data and product or test engineering data. Without this type of automated solution, only a small proportion of these data sets would actually be utilized.Companies staff their product design and test engineering using a budget based on a percentage of revenue. If a company has billions of dollars of revenue, it will put so much more into product and test engineering. But how productive can these people be? Without AI, they can only use some simple reports and graphics to analyze the subset of data they are looking at. AI solutions such as PDF’s Guided Analytics capability apply sophisticated machine learning tools to analyze entire large data sets. AI is enabling engineers to be more productive by allowing them to work with large data sets that ultimately deliver better results in the products.The amount of compute keeps going up at a rate that outpaced the rate of geometric scaling. More compute power makes it cost effective to go through large data sets and identify what is relevant.Additionally, AI is helping semiconductor companies build products. A conventional compute system is chips assembled on boards. AI is making system-in-package take off.The production flow is more complex, as fabless companies are becoming system companies. Conversely, system companies are becoming fabless companies and manufacturers. In the past, they ordered parts from their foundry of choice. Essentially, the foundry was the system manufacturer, supplying package and test yields of 99%.Now companies are building systems in more complex packages potentially with foundry partners, but this requires getting known good die. High bandwidth memory or other components from other suppliers means the company must make sure these products are available at the right time. In essence, they are becoming manufacturers and changing the way customers manage the problem of product test. They're adding more test insertion points and using machine learning and AI to be more productive.Smith: Let’s talk about digital twins or creating virtual models of everything from chips to the whole system. How do you see the impact or effectiveness of digital twins in manufacturing? Kibarian: From a manufacturing perspective, digital twins had been models for chamber behavior on a processing tool like an etch tool or TCAD simulation of devices and structures.The problem is that purely physics-based digital twins don't exist, and we must utilize empirical data. The joke was that the modeling for tomorrow’s systems was based on yesterday's technology. Trying to have the physics catch up with the materials, device structures and behaviors is why it’s so expensive to develop new technology.Principles-based models will never catch up with production. We can model 90-nanometer technology, but it doesn’t work for one or two nanometer wafers. AI and machine learning – and ways of building models using more sophisticated algorithms – can help close that chasm, and that’s starting to happen at the R D level.In production, no one has yet achieved a good merger of the physics-based and AI-modeling worlds to create a virtual model. Virtual modeling is a big opportunity.The rate of change and improvement in algorithms in large language models moves fast because machine learning can scrape the Internet for data to build huge training sets. In the semiconductor world, however, data sources are typically siloed within organizations and often not shared with vendors. This limits the rate at which the industry can take full advantage of existing data and create tangible economic benefit.By and large, there is a lot of wasted capacity in semiconductor manufacturing. The operational effectiveness of factory equipment is up to 90-95%. The reality is that most factories today process product wafers 40-60% of the time – maybe 70-75% of the time on a test floor. It is critical for the industry to start leveraging new types of AI models to increase the productivity of its manufacturing capacity.The industry needs to look at how companies can share data to take advantage of more sophisticated AI and create a new kind of operational digital twins. If the industry doesn't make a change; it will only be the largest facilities with the largest datasets able to take advantage, leaving one or two winners, with the others not being competitive.Smith: Is it possible for the industry to come up with a standard or some way of sharing information to build better models without giving away the underlying proprietary data? Kibarian: We can look at computer science with technology like homomorphic encryption. The relationships between parameters remain, but the underlying numbers or raw data is not visible after encryption. Pharma and the medical industry have ways to add noise to the data while preserving the information, as required by the Health Insurance Portability and Accountability Act (HIPAA).Our industry has a knee jerk reaction when it comes to looking at how to take full advantage of data and prefers to solve it as if information and data is more proprietary than medical data or financial data. And I don't think that’s true.Bob Smith: Is the open-source movement destined to bring change to the industry? Kibarian: PDF is a big believer in open source when it comes to OS-level virtualization and Kubernetes versus proprietary alternatives. We also use open-source database technology like Cassandra but are skeptical of the value of open-source solutions for end-market verticals. Having an underlying open and available IT layer has tremendous value, because it means a more rapid rate of innovation and greater ability to adjust security vulnerabilities and patches versus proprietary systems.Smith: PDF sits right between manufacturing and design. On the EDA side, more collaboration is going on between designers and manufacturing. How would you bring these two domains closer together? Kibarian: That's a good question. My first instinct is to look at the largest design organizations and manufacturers. They often invest heavily to figure out how to get jobs done right. This results in the concentration of the industry on a smaller number of players and leads to less innovation. However, in the world of chiplets and advanced packaging, there are more opportunities to become a chiplet supplier, because the whole system doesn’t need to be built by a single company. A supplier of chiplets could sell it into many systemsFrom a system view, connecting the pieces together through software, data sharing and analytics could drive more productivity gains that will offset some of the natural headwinds. This needs to be addressed in a way that changes the paradigm with software and systems used to bring manufacturing and design closer together.About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

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