Electronic Design Automation

Presentations from SEMICON West’s “The Convergence of Semiconductor Manufacturing and Design” offer great insights into the collaboration between the two, as I was recently reminded by presenter Sutirtha Kabir, R D Engineering, Executive Director at Synopsys.Reviewing his talk “Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” was a good kick-off for our discussion that covered the continuous need for collaboration and where AI fits. Kabir, as I quickly learned, is a technical innovator and articulate communicator passionate about ongoing collaborations between design and manufacturing. Today’s blog post is the second in a four-part series featuring presentations from the SEMICON West design program, organized by the ESD Alliance, a SEMI Technology Community. The first blog, with Dave Kelf, CEO of Breker Verification Systems, appeared on January 6 (“Circular Collaboration Leverages EDA Advances”).Smith: How do you define collaboration between design and manufacturing?Kabir: Multi-die design and advanced packaging are a big focus of high-performance computing (HPC) and AI chips. Engineers are trailblazing and foundries are coming up with new stacking combinations. For this reason, design and manufacturing teams need to be closer than ever. Solutions must be made available to give ample visibility to manufacturing from the very start of the design process. Single die design has been done for 15 to 20 years with a continuity of power, area, and performance (PPA). Design flows, methodologies and the ecosystem between design houses, EDA vendors and foundries are mature and stable. The conundrum is that it's a different situation with multi-die designs. Not only is multi-die emerging rapidly, but the types of design innovations are different.We have been working closely with our foundry partners to move multi-die innovation forward by enabling more advanced process and packaging technologies. I don't see this slowing down as they are coming up with different ways of doing designs. Design teams are collaborating closely with the foundries to take advantage of the benefits of these new multi-die designs.Smith: You mentioned new stacking combinations and collaboration with the foundries. What about collaboration with the OSATs? Kabir: Generally, it’s both silicon foundries and OSATs. With advanced packaging, both play a significant role depending on the types of applications being targeted. Design house targets may shift from the traditional silicon foundry to several OSATs. For example, if an organic interposer is required, the collaboration could be with an OSAT in conjunction with the silicon foundry. There are many possible collaborations that may be required. The point I’m trying to make is that there is a strong need for collaboration between EDA and the foundries during design that continues through manufacturing and test.Smith: What trends in general are driving the need for this collaboration?Kabir: The trends are performance and scalability and the need for high-performance compute. Look at some of the mega-chip systems coming out today compared to the bigger systems from five years ago. HPC was not driving that much in 2.5D. The big interposers used to be on silicon, maybe 1.2 to somewhere around less than three reticle sizes. Today, the reticle limit is more than 5X. Leapfrog to today, and the configuration has changed where the state of the art is to use an organic interposer with multiple embedded bridges (up to 20 or more) buried inside the interposer to support high-speed interconnect. The organic interposer with multiple layers on the front side and back side communicates with bridges and the SoC and HBM that sit on top of that interposer.3D architectures stack dies with GPUs and a large amount of HBM such as an HBM4 memory stack. The memory stacks may be 8 or 16 high. All of this memory needs to be as close as possible to compute for scalability. In terms of the high-power demand, the designer needs to make sure that the voltage that is pushed from the bottom of the stack can feed the power hungry SoC blocks on top of the 3D stack. At the end of the day, EDA is all about giving design and manufacturing houses the capability to predict how a design is going to perform in all different kinds of scenarios. EDA must keep up with this trend and that requires collaboration.Smith: What about the verification side, specifically system verification? Kabir: Let’s say I am using a spreadsheet and doing back-of-the-napkin calculations, a technique that used to work well for single die or design blocks. Multi-die doesn't scale since multiple heterogeneous dies in a single package must be considered. Design planning must include directional changes to measure the effects with key performance indicators. The challenge is to correlate signoff and verification. Signoff engineers can no longer just verify at the end of the design cycle. Instead, it has become a continuous process that transcends the flow from design planning through implementation and signoff and release to manufacturing.The industry is repeating a pattern from about 20 years ago, when single-die design evolved from relatively naive approaches to much more sophisticated EDA-flow-driven methodologies.Smith: As you drive the tools forward, who are your counterparts on the manufacturing side? Kabir: It depends on the different stages of design—design planning, implementation or signoff. It starts at the architecture stage from the left when architects and physical design engineers are doing floorplanning. The term design technological co-optimization (DTCO) has evolved into S (system)TCO now because we are trying to co-optimize system design and technology. I'll give you a simple example. A working chip manufactured in a certain technology node is going to be used in a multi-die design. Is the existing chip technology good enough to support the design or will it require a new chip at a different node? In either case, how does an engineer work with the manufacturing house to make sure it has the right metal layers or a different number of metal layers or a different metal width or some other property on the technology side? Designers need to make data-driven decisions based on the configuration and technology numbers to meet power budgets.In the past, what was once managed through designer-ASIC house-manufacturing interactions are now increasingly being handled by EDA flows as part of design implementation.Smith: Ultimately, it's driven by business. The hard work and decisions are made by two teams of knowledgeable technical people who must come together.Kabir: And then of course it has to be rolled into program management, business development and all this needs to be supported by data. We all recognize that the design window is not increasing. It’s always about trying to get more out in less time with less people. That doesn't help the equation.Bob Smith: How does AI fit into this and how is it best leveraged? Kabir: I’m hearing, learning, and reading about the tremendous advantages AI could bring. AI has a huge role to play, but it won’t eliminate the need for savvy design and verification engineers.Multi-die design brings together different users from different tool backgrounds. Even the language between a packaging person and a silicon person is different. The terminologies they use are different, as are the ways they have done design over the last 15-20 years. The same applies to thermal, power or signal integrity engineering. Bringing them together requires that EDA will provide platforms where the whole system design, including chip design, is managed. That’s a tall ask for people from all different backgrounds to come in, learn different technologies and tools within a short time. This is where ChatGPT or Microsoft’s Co-Pilot can be applied in the EDA world today to quickly find solutions by reading through manuals, application notes, forums and the like to find solutions. This use of AI agents can save tremendous amounts of time for designers. Another aspect that can be positively impacted are roles. We have customers coming to us and brainstorming on the use of workflows and methodologies, instead of the design aspect. Scalability from the human perspective has become difficult because of the need to closely guide engineers to get them up to speed on new technologies and workflows. This is where Agentic AI can deliver a huge productivity boost. It's not replacing anyone. It's getting them to decisions and end results faster.Smith: Can Agentic AI play a big role? Kabir: Current AI is like the person who, when asked a question, has to give an answer even if it’s the wrong answer. The same thing is going to happen when we bring in all these EDA technologies with AI capabilities.The point I'm trying to make is how do we verify that AI is doing the right thing? In EDA, one of the biggest questions and concerns is if a result or outcome or design can be verified. If it can't be verified accurately, verification engineers will not trust what AI is telling them no matter how fantastic the algorithm is. The verifiability of AI solutions is important for EDA. The key question is: Why would I trust what your tool is telling me to do?EDA flows that are more mature rely on decades of expertise, thorough documentation, and various scenarios to train AI algorithms. Those are the AI-powered EDA flows that I trust the most. About Sutirtha KabirSutirtha Kabir, an Executive Director of R D for Synopsys’ 3DIC Compiler, has over 20 years of product engineering experience, driving, building, and inspiring teams across companies in the EDA industry. In his role at Synopsys, he supports construction and analysis of multi-die systems including stacked ICs plus Interposer configurations. Prior to joining Synopsys, Kabir was a Group Director of Engineering at Cadence. Kabir has a Master of Science degree in Electrical Engineering. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

The SEMICON West 2025 design program “The Convergence of Semiconductor Manufacturing and Design,” organized by the ESD Alliance (ESDA), a SEMI Technology Community, featured presentations about successful collaborations between the design and manufacturing markets. The three-hour program in a packed conference room included plenty of great material that we’re using as the basis for a blog series that you will see over the next several months. I’m working on them now based on my conversations with four of the speakers where we discuss key drivers behind the need for collaboration and what’s ahead.I’m starting with Dave Kelf, CEO of Breker Verification Systems, a company steeped in front-end chip verification, who describes an actual circular collaboration that effectively leverages AI and other electronic design automation (EDA) advances. We recently talked about collaboration, integrated design and manufacturing flows and AI.Smith: How does Breker define collaboration between design and manufacturing? Kelf: In general, at a technical level, we would define this collaboration as the sharing of data, methodology and/or information that improves both processes. As semiconductors become more complex, this sharing process is increasingly important to effectively manage the overall complexity of today’s chip designs.Smith: What trends are driving the need for this collaboration?Kelf: Apart from the ever-increasing size and density of semiconductors, there are specific trends that require more interaction between design, verification and manufacturing. Obvious developments include the advent of chiplets, given the changes in performance of signal paths, and 3D devices driving complex packaging, power dissipation and other issues. Design issues such as the increased need for SoC coherency testing and complex device structures such as multi-core processors, also play a role. With many of these issues, design and verification (D/V) trade-offs have an impact on manufacturing, and vice versa. For example, differing delays on a Universal Chiplet Interconnect Express (UCIe) interface—an open specification for a die-to-die interconnect and serial bus between chiplets—will have an impact on hazard testing in coherency verification. As another example, thermal hotspots on some parts of a chip package might need additional testing during the verification phase. Smith: What trends and challenges are preventing a fully integrated design and manufacturing design flow?Kelf: Traditionally, the D/V and manufacturing teams have remained separate in most organizations, as well as between the two industries. EDA companies sell primarily to the design teams, although they do interact with the foundries at the back end of the process. Manufacturing companies work directly with different teams at the foundries and not with the D/V teams at all. New relationships need to be built up. The general know-how in these disciplines is different, and methodology approaches tend to be disconnected. The tradition is to separate the processes and use standardized interfaces for communication that leaves little room for improvisation. All this needs to change so that teams can begin to work more closely.Smith: What is circular EDA-manufacturing collaboration and vertical integration?Kelf: In past EDA flows, we have seen disparate tools performing specific functions. As semiconductors got smaller, their physics changed and this led to the design process absorbing new characteristics. For example, abstract designs were run through synthesis to create gates connected by wires. This format was then passed to place and route (P R) tools that would lay out the gates in terms of transistors and interconnects on the silicon wafer. On large devices, the gate level signal delays were larger than the interconnect, allowing design to be separated from layout. As silicon became denser, the interconnect delays became the dominant factor, and the layout of the device impacted the design synthesis process. The two tools required forward integration—synthesis projected layout rules to P R, and a reverse integration where layout characteristics were sent back to synthesis for redesign where required delays could not be handled during P R. The methodology went from a simple flow to a circular design approach as synthesis and P R cooperated. The same is now true of design and manufacturing where solving the problems noted above requires this same circular cooperation. Smith: What will it take to have an integrated design and manufacturing flow?Kelf: A lot of cooperation between different groups. As we reach limits in areas such as signal integrity and thermal management that will squeeze silicon efficiency improvements, these methodology linkages will be required for continued progress and growth. The industry (both design and manufacturing) will be highly motivated to make this happen. Smith: From a personnel perspective, who (on both sides) are the typical touchpoints? Kelf: It will be the engineering staff from both the design side and manufacturing that work closely to develop technical solutions. Executive-level support is, of course, needed to cement the collaboration. Smith: Where does AI fit?Kelf: AI will have a role to play in this. Estimating the factors that drive efficient design to manufacturing to design flows is a critical step in speeding interaction and providing sensible estimated starting points. AI can process the large amounts of data necessary to provide these estimates as we now see complex chips that contain billions of transistors. AI will be needed to accelerate the interactions for different tools through the development process.As design and manufacturing collaboration becomes a critically important industry strategy, companies are turning to SEMI and its Technical Communities such as the ESDA and their wide-ranging initiatives. For details and to get involved, visit the ESDA website at https://www.semi.org/en/communities/esda. To learn more about Breker and its solutions that provide test content portability and reuse to solve complex semiconductor challenges across the functional verification process, go to: https://brekersystems.com.About Dave KelfDave Kelf holds the position of CEO of Breker Verification after serving as its Chief Marketing Officer responsible for all aspects of Breker’s marketing activities, strategic programs and channel management.Earlier, he served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions, was president and CEO of Sigmatix, Inc., and held senior positions at Cadence, Synopsys and Springsoft. Kelf holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collaboration is the key to growing the semiconductor industry to $1 trillion and how we will get there.Smith: What is the major industry evolution or dynamic that's making collaboration essential today?Kibarian: The semiconductor industry has dramatically evolved from a simple, linear process to a complex, collaborative ecosystem. Previously, everything happened at the wafer fab. Testing occurred at wafer sort, package yields were high, final testing was straightforward, and products were shipped. Collaboration was mainly between foundries and fabless customers, intensive during early qualification and test chip stages, then evolved to routine yield monitoring once production stabilized.Today's advanced packaging puts multiple chiplets into single packages, creating an explosion of test insertion points. This has driven up both test complexity and costs significantly. Front-end fabs now house the most complex machines, while test and assembly facilities, once relatively simple, now feature sophisticated system-level testers with integrated robotics. Assembly tools have become highly complex, with die-attach processes requiring increasingly tight tolerances. Success now requires collaboration across the entire chain, from system companies to equipment vendors, both for new product launches and ongoing production maintenance.Companies are adopting AI and machine learning (ML) to manage these complex production flows, whether for testing or equipment control. This demands even broader collaboration since AI requires combining data from multiple sources across foundries, fabless companies, OSATs, equipment vendors, and more, data that no single entity controls. What was once a straightforward handoff between two parties has become an intricate web of interdependent relationships requiring continuous coordination.Smith: Chiplets and chiplet-based architecture is in the news and seems to be a key solution or practical solution in response to the slowing down of Moore's Law. This demands incredible levels of collaboration and coordination across the whole value chain. Is this doable at scale where it starts to move into the mainstream?Kibarian: The semiconductor industry will need unprecedented collaboration to make chiplet manufacturing work at scale. But this can be done! Consider EUV lithography: Initially expected during the 65nm generation, it took years longer than anticipated despite being an incredibly complex technology. Extraordinary engineering was needed but it also required extensive collaboration between ASML, suppliers, customers, and the broader fabless community.If the industry achieved this level of coordination for EUV, it can do the same for chiplets. However, chiplet manufacturing will require even greater collaboration as more companies will build systems using chiplets from multiple suppliers.Today's chiplet-based systems typically source all components from one manufacturer, making standards like UCIe less critical since companies control their entire supply chain. This will change as companies increasingly use third-party components for cost-effectiveness.More and more, we will see systems using components from multiple players to get to market more cost-effectively. Consequently, future production flows will be significantly more complex, requiring coordination of substrates and base dies, third-party dies and interposers, OSAT and specialized testers with specific configurations.This orchestration must work not just for initial bring-up but for the ongoing production as well, and when reconfiguring chiplet combinations for different products, all requiring rapid, automated responses.All of that must be automated for quick reaction. Considering the complexity of the manufacturing flow, people will want to apply AI/ML to anticipate what is going on in each individual product built.Manual oversight of every chip and package during manufacturing isn't feasible at scale. Automated AI agents must handle this monitoring and quality control. Expanding this automation will require close collaboration between the manufacturing entity and engineering teams at the product companies.This will also require a different level of alignment and orchestration across all the software packages managing this complex multi-company process. The financial enterprise resource planning (ERP) systems know where material is going, what the demand is, and what the forecasts are. While separately, the manufacturing execution systems needs to know which tools are going to be available when. Most often, these manufacturing systems operate in factories the product company doesn't own. The product company’s PLM systems control the bill of materials and test flows, but these tests will be conducted at the OSAT requiring complex coordination between the software systems of multiple companies controlling different process domains. This orchestration spans organizational boundaries and must be able to take data from upstream test results and make decisions on what tests to run downstream. This is required to get the right chiplets put together into a package in an efficient manner within a short cycle time and not require a Formula 1 pit team to keep everything running.Smith: The volume of data is staggering, especially now with design data. What will it take to enable this vision, at scale, where everything's connected? Kibarian: It’s a marriage of the human establishing the bounding box within which the systems operate that employ agents to do a lot of the work on a day-to-day or hour-by-hour basis. A good example is how manufacturing execution systems (MES) connect to ERP systems to share data. When a company sets up an orchestration, it creates rules that govern how information flows between systems. These rules tell the ERP system: "To calculate costs for each process step, here's the recipe information you should use."Once these rules are in place, they work like guidelines that control daily operations. An AI agent automatically creates insights based on actual data collected from the MES and moves data between systems according to these rules. The ERP AI agent will use this data to spot when costs are rising and send alerts, to notice when production yields drop, to calculate what lower yields mean for costs, and will take action to fix problems.This same process happens between equipment suppliers and manufacturing facilities. They share data automatically based on pre-set rules, and AI helps identify issues and take corrective action. Fabs determine who can access which machines and when, what types of data can be transmitted and through which channels, and how frequently these transmissions occur. When new software or AI models are introduced to run equipment, the systems specify what virus scanning and security checks must be completed before installation.Human operators primarily configure these control systems by determining the most effective collaboration protocols. However, the day-to-day execution is handled by automated agents due to the enormous scale involved, both in terms of data volume and the sheer number of transactions that occur continuously throughout operations.A human will not go through and review that data. I'll give two examples of this. One outside of our industry and one in our industry. At our 2019 user conference, board member Marco Iansiti, a Harvard Business School professor, shared insights from his book on AI in business. He compared traditional banks with Ant Bank, Alibaba's banking arm, which was experiencing explosive growth before Chinese government intervention.Ant's AI wasn't particularly sophisticated, but its process was revolutionary. While traditional banks require customers to fill out loan applications that then go to human loan officers for review, Ant's system would automatically scrape the internet and social media to verify applicant information. Within seconds, an algorithm would approve or deny the loan.The crucial difference is that Ant could scale exponentially because its only constraint was computing power. Traditional banks need to hire more loan officers to double their business, a human bottleneck that limits growth.I invited him to speak because I believed in this principle six years ago, and I'm even more convinced now.For the semiconductor industry, to build a trillion-dollar industry with complex, integrated systems, we need to minimize human intervention in data intensive processes. Despite the trust issues between stakeholders in our sector, collaboration remains essential. The solution requires establishing systematic principles that allow AI agents to operate autonomously. This is a way forward to achieving exponential growth.The Ant Bank example perfectly illustrates what our industry needs. At PDF, we believe this approach is crucial for industry advancement. Consider this: We manage petabytes of data, yet humans only examine 5-10% of it. This shows AI's potential to handle the vast majority of operations without human oversight.The reality is that our customers build millions of chips a week, billions a year. They cannot look at every dataset. Algorithms can, AI can. We launched a product called Guided Analytics last year. An engineer spoke about it during our user group last year. Her company has a couple of thousand products. Her group could not keep track of them every day, but Guided Analytics could. When her group came in the morning, the daily report noted 90% of the chips were fine or alerts pointed to where issues are. It's a simple AI bot crawling over data and identifying where the root cause seems to be.Our industry will require more agents to scale. Those agents will span the industry, and yet we as humans need to set up the governing principles under which they can operate. That's how we're going to deal with the massive amounts of design and manufacturing data to get the velocity the industry will need, and to benefit from the AI that we create for our businesses.Notes: Kibarian’s keynote, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” is scheduled for Wednesday, October 8, at 10:20 a.m.SEMICON West adds design to its program with “The Convergence of Semiconductor Manufacturing and Design” to highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session will be held Tuesday, October 7, from 1 p.m. until 4 p.m. Learn more about the design program in our latest blog. SEMICON West 2025 will be held in Phoenix, Arizona from October 7-at the Phoenix Convention Center. SEMICON West’s homepage has links to the full program, including more details about “The Convergence of Semiconductor Manufacturing and Design,” special features, sponsor and exhibits. Registration is open. About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Electronic Design Automation (EDA) financial analyst Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, carefully tracks the design portion of the semiconductor industry and offers insightful analysis used by this community. He also presents the State of EDA, a yearly report on EDA, during the Design Automation Conference (DAC). After this year’s presentation, he and I talked about trends, the difference between EDA and Architecture, Engineering, and Construction (AEC), security and chiplets. A condensed version of our talk follows. Smith: Now that the Synopsys-Ansys merger closed, what changes? Vleeschhouwer: Synopsys is now the largest company by revenue and backlog in all of Engineering Software, a well over $30-billion industry, including all the parts of that market—AEC, EDA and Technical Software. The pro-forma backlog, about $9.84 billion as of the most recently reported quarter, is the largest in the industry. An important question is how will Synopsys integrate, employ and leverage the four-fifths of Ansys that is not strictly EDA? That is, other than Ansoft and Apache, the two entities that mostly comprise Ansys' EDA, and that ties into the convergence theme. Also, the question in any acquisition is the balance between leaving the operations and the portfolios as they were, or not. In other words, let them continue doing what they were doing if they were doing it well or quickly absorbing, integrating and leveraging those portfolios into the buyer's portfolio. That roadmap is something that we would be interested in hearing more about in terms of its purely EDA aspects and as well the convergence aspects.Smith: Have you observed any new trends in 2025 that surprised you? Vleeschhouwer: The short answer is that it's more of the same in terms of the main technical and business trends. Of course, the most recent important exogenous effect is the advent of tariffs and new export restrictions, or the variability around export restrictions. That's perhaps the main thing that's occurred in the last few weeks and months. We're seeing a continuation of trends that have been in place for a number of years in terms of many of the technical and business results that we've highlighted in our reports. From industry data, there continues to be multiple EDA categories that are continuing to grow. It’s observable and important that we see this breadth of product adoption and growth across multiple categories. This has been beneficial to each of the four largest EDA companies. There have been compelling technical reasons for this, and I would expect it to remain the case. In terms of those significant multi-year trends, the answer would be no. Otherwise, in terms of 2025 specifically, the thing that was interesting about this year’s DAC was the presence of more startups, something that we've not seen in EDA for a long time. It's interesting that we are seeing startup activity not only in EDA, but even in one of the other areas of Engineering Software that we cover: AEC has little to do with semiconductors and electronic systems and it too has more startup activity than we've seen for about a quarter of a century. Although the rationales for the startups in these two different areas of Engineering Software are quite different. The rationale for the EDA startups is one set of rationales, whereas in the case of AEC, it's different, which to me is analytically interesting. Smith: What is the difference between the rationales for startup activity in EDA and AEC? Vleeschhouwer: AEC has to do with the design and construction of commercial buildings, residential buildings, infrastructure, meaning roads, bridges, airports, tunnels, civil engineering, public works. Among the companies that we follow in those markets are Autodesk and Bentley Systems. Autodesk has a small connection to EDA because one of their mechanical CAD products has some integration with some PCB design tools. In any case, the rationale for startups in AEC that we've seen has mostly to do with what has been some vocal dissatisfaction with the incumbent or large incumbent products. That's different from EDA, where we can’t make a case that there is dissatisfaction or sufficient dissatisfaction with the incumbent tools that would necessitate, or be a catalyst, for startups. What we're seeing here is the ongoing, complex, rapid evolution of semiconductor design and electronic systems design because of the unusual breadth of EDA tools and functions, far more so than in AEC. There's much more opportunity for niche products to perhaps complement existing tools. As you know, it can be difficult to dislodge an existing tool in EDA. The industry has become consolidated among the big four—Ansys, Cadence, Siemens EDA and Synopsys—and now three with Synopsys/Ansys merger. Backlogs have continued to grow and book-to-bill has been positive for 15 years. It’s hard to infer any dissatisfaction with incumbent tools or insufficient satisfaction showing up in the numbers. Whereas in AEC, it's different in terms of the profile of the customers or the way the tools are used. There are far more customers than in EDA—thousands upon thousands of architectural firms and construction firms and so forth. The installed base of the AEC software is an order of magnitude more than in EDA. It just so happens that there was one tool from Autodesk that has been getting considerable attention from customers in terms of how modern it is and so forth. This created an opening for some startups. Notwithstanding the nominal dissatisfaction with this tool, however, that particular brand continues to grow. It has the largest base in the industry. At the end of the day, the largest product of its kind in the market continues to grow at a decent rate. The vendor in this case, Autodesk, has acknowledged some of the things needed to do to improve the tool, and it's investing toward that. In any case, there are differences in why these startups exist, how they're approaching the market.Smith: The big topics now are 2D and 3D and chiplets. Where is the market relative to chiplet-based design? Vleeschhouwer: It’s still early, based on commentary from the EDA vendors, about developing and delivering the tools. I don't have a precise measure as to how much of the business is attributable to it. It’s still something that has a considerable runway, which is a good thing. As more tools that can enable it come together, then we'll continue to see this cycle of enablement and delivery. That phenomenon will continue to grow. We would love to hear the vendors’ provide more precise attribution in terms of how much of the business is coming from this. For investors, it will be incumbent upon the vendors to be more explicit about the contribution from the new technical phenomena because it is a new growth catalyst. Smith: The ESD Alliance is starting to see more interest in securing the design flow. This is a huge issue. The design flow is more complex and it's going to require cooperation, collaboration and new standards. Vleeschhouwer: Yes. Siemens EDA is the largest in classical product lifecycle management (PLM) or managing the whole process, an important issue for the industrial and manufacturing markets with its Teamcenter product. Interestingly, Siemens EDA still has work to do to integrate Teamcenter with Calibre, which would seem to have been a natural thing to have done, and I think still is. Teamcenter and Calibre are the two billion-dollar brands that Siemens Industry Software has as an entity. Calibre is by far the predominant product of its kind for semiconductor manufacturing. It's got at least two-thirds market share. Teamcenter is the market leader in classical PLM. The connection between those two brands, owned by the same company, would be an interesting executable to observe.About Jay Vleeschhouwer  Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, has more than 40 years of research analyst experience in the technology sector, including software, semiconductors and computer hardware. Vleeschhouwer does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). The slides can be found at: DAC presentation (June 2025) 2.pdf Note: The ESD Alliance will host a three-hour design track “The Convergence of Semiconductor Manufacturing and Design” Tuesday, October 7, from 1 p.m. until 4 p.m. during SEMICON West in Phoenix, Ariz. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

This year’s SEMICON West has new dates, a new location in a new city and a new addition to the program—design! “The Convergence of Semiconductor Manufacturing and Design” will highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session during SEMICON West will be held Tuesday, October 7, from 1-4 p.m. at the Phoenix Convention Center in Phoenix, Arizona.Five 20-minute presentations will describe successful collaborations and address challenges and opportunities about design and manufacturing security, long-term reliability, system performance issues, and modeling and verification that encompass the entire system. Attendees can expect to learn about the key drivers behind the need for collaboration that range from heterogeneous integration to advanced packaging technologies and applications such as automotive and medical.Session moderators are Ming Zhang, PhD, Vice President of Fabless Solutions of PDF Solutions, and me. “As design and manufacturing complexity continues to grow, driven by applications like AI, it is becoming increasingly difficult to account for every manufacturing variation during design and at sign-off or to fully anticipate the entire design space at chip and system levels during manufacturing technology development,” said Zhang. “Achieving tighter integration between design and manufacturing through broader and deeper data and methodology collaboration will be critical to improving predictability, accelerating time to market and enabling the next generation of semiconductor innovation.”It’s within this context that we selected the presenters who include:“Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” by Sutirtha Kabir of Synopsys.“Manufacturing to Development to Manufacturing for Circular Collaboration Leveraging AI and Other EDA Advances” with David Kelf from Breker Verification Systems.“Bridging the Silicon Divide: Converging Chip Design and Manufacturing in the Era of High Integration” from Lu Dai at Qualcomm Technologies.“3D and Chiplets Driving Moore’s Law into the Future” with Joe Kwan of Siemens EDA.“Multiphysics Multiscale Challenges and Solutions for 3D Heterogenous Integration” by Sudarshan Mallu from Ansys, part of Synopsys.The program concludes with a panel moderated by Zhang titled “The Convergence of Semiconductor Manufacturing and Design” and features the session presenters.Join us to learn how the semiconductor manufacturing and design communities are collaborating to deliver advanced systems based on chiplets and rapidly emerging packaging technologies including 2.5D and 3D ICs and MCMs. Audience participation will be encouraged.Also of interest to attendees is a SEMICON West keynote from John Kibarian, CEO, President and Co-Founder of PDF Solutions who is also co-chair of SEMI’s ESD Alliance Governing Council. Kibarian will address “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” during the CEO Summit keynotes on Wednesday, October 8 at 10:20 a.m.SEMICON West 2025 makes its debut in Phoenix, October 7-9 at the Phoenix Convention Center. This milestone event gathers global leaders across the microelectronics supply chain to explore transformative technologies, develop the future workforce and drive strategic collaboration. Moving SEMICON West to Phoenix highlights Arizona as a key hub for innovation and industry growth. Visit the SEMICON West homepage for more details on full program, including “The Convergence of Semiconductor Manufacturing and Design” session, special features, sponsors and exhibits. Registration is open. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

In an era where technology permeates every aspect of our lives, the semiconductor industry serves as the backbone of innovation. From IoT devices to data centers, every piece of technology relies on integrated circuits (ICs) such as intellectual property (IP) cores and system on chips (SoCs). As these technologies become increasingly pervasive, the importance of hardware security assurance in the design and development of IP and SoCs cannot be overstated. Evolving cyber threats and sophisticated attacks make it essential for vendors to integrate advanced security measures into their workflows.Market Pressures Driving Demand for Enhanced Hardware Security The semiconductor market is projected to reach $1 trillion by 2030. At the same time, semiconductor devices and system designs are becoming increasingly complex. With that complexity comes the added difficulty and effort required to conduct thorough security analyses. Additionally, competitive pressure to reduce time-to-market means that vulnerabilities can be more easily overlooked or exploited, making it crucial for the industry to adopt automated security solutions. As more products are deployed in critical systems, from consumer electronics to national infrastructure, the stakes become even higher, underscoring the necessity for robust security measures.According to the SEMI Electronic Design Market Data (EDMD) report, in 2023, the electronic design automation (EDA), semiconductor IP, and related services market reached $17.1 billion, fueled by the increasing complexity of semiconductor designs and the growing emphasis on security. While the overall EDA market is growing at a 7.4% compound annual growth rate (CAGR), the semiconductor IP segment is expanding at 9.7%, and in comparison, the logic verification tools market alone is surging ahead at 24.2%. Deeper verification processes and tools are needed to not only handle the rising complexity of semiconductor designs, but also to support the growing emphasis on secure-by-design principles to ensure robust and reliable products in an evolving technological, security, and threat landscape. As a result, the market for logic verification tools — a key component of the EDA market — is surging. The Rising Cost of Cyber Threats from Data Breaches and Architectural Flaws Pavani Jella, Silicon AssuranceThe average cost of a data breach is $4.88 million1, encompassing lost business, regulatory fines, legal fees, and damage to brand reputation. As the semiconductor market grows, the potential financial impact of security breaches due to hardware vulnerabilities also escalates. Companies must invest in robust security measures to mitigate these risks and protect their financial health.Cyber threats from the exploitation of architectural flaws are another threat. Plundervolt is one example of an architectural flaw that could lead to hardware exploitation. Discovered by ethical hackers, Plundervolt is the name of an attack that exploited voltage fault injection to compromise the security of Intel processors. By manipulating the voltage supplied to the CPU cores, attackers could induce errors in the SGX enclave, allowing them to leak sensitive data or even bypass security protections intended by the enclave. This flaw was particularly concerning because it operated at the hardware level, making traditional software security measures ineffective. The attack leveraged the SoCs’ power management features, specifically dynamic voltage and frequency scaling (DVFS), to achieve its malicious objectives.Exploiting such a vulnerability could lead to the exposure of sensitive data, such as cryptographic keys and proprietary information, compromising the confidentiality of secure enclaves. This breach could erode trust in an IP or SoC provider’s security features, particularly in environments that rely on using the IP or SoC for protecting critical data. In cloud environments, a successful exploit could result in multi-tenant data breaches, impacting numerous users.The vulnerability also poses risks to secure applications, potentially leading to manipulated outcomes and decrypted communications. Businesses could face significant financial losses, operational disruptions, and regulatory consequences due to such an attack. It is a stark reminder of how architectural flaws in SoCs can be exploited, leading to severe security breaches that are challenging to mitigate without hardware-level fixes.Industry Believes Hardware Security Assurance Is a Key Priority A majority of security professionals from a diverse group across industry, defense, government, and academia rate hardware Trojan detection, IP piracy protection, and SoC vulnerability assessment as high priorities. This prioritization reflects the industry's awareness of the critical importance of security measures in maintaining the integrity and reliability of semiconductor products.As a result of this awareness, investments in cybersecurity are expected to reach $345.4 billion by 2026, growing at a CAGR of 9.7%2. This substantial investment demonstrates the global commitment to enhancing security measures across all industries, including semiconductors, to combat the escalating threat landscape.New EDA Tools and Investments Needed to Combat Cyber Threats The adoption of new EDA solutions is essential, despite the initial costs. Costs can range from $100,000 to $1 million per license for general EDA design and verification tools, depending on the complexity and capabilities of the software. Pre-silicon security EDA tools can detect vulnerabilities early in the design phase, significantly reducing the risk of exploitation and the need for costly post-production fixes while enhancing product reliability. Secure-by-design principles ensure that security measures are integrated throughout the development process, rather than added as afterthoughts.Integrating these new tools also requires investment in training and potential adjustments to existing workflows. However, the improved security and efficiency provided by these tools can offset these initial costs.While the costs of acquiring advanced EDA tools and deploying them in the workflow is significant, the investment is justified by the long-term benefits of enhanced security and reduced risk of costly breaches. Secure-by-design practices can prevent significant financial losses from security breaches, offering substantial long-term savings. Companies that invest in robust security measures are better positioned to demonstrate market leadership and build customer trust and loyalty, while avoiding the reputational and financial damage associated with breaches.ConclusionThe semiconductor industry is at a critical juncture where the application of advanced EDA solutions for hardware security is not just beneficial, but essential. The time to act is now.The increasing sophistication of cyber threats and the financial repercussions of security breaches make it imperative for IP and SoC vendors to adopt advanced EDA security assurance solutions to secure their designs. By investing in cutting-edge EDA tools and prioritizing security from the earliest stages of design, vendors can safeguard their products, maintain market competitiveness, and protect against the ever-evolving landscape of cyber threats.References1. IBM Cost of a Data Breach Report 20242. KPMG 2024 Global Semiconductor Industry OutlookPavani Jella is the Vice President of Business Development at Silicon Assurance, a member of the Electronic System Design Alliance (ESDA) a SEMI Technology Community. Silicon Assurance specializes in hardware security assurance solutions. With a strong background in the semiconductor and EDA industries, Pavani plays a pivotal role in driving strategic growth and fostering innovative partnerships. Passionate about the intersection of technology and security, she helps organizations adopt state-of-the-art solutions that ensure the resilience and trustworthiness of their hardware systems.

Executive Advisor Jeff Lewis held the position of Vice President of Marketing and Business Development for Artisan Components, one of the early companies developing blocks of intellectual property. Lewis, who worked at Artisan from 1996-2000, and his colleagues were members of an elite group who built the mega-successful IP market, estimated today at $7.48 billion. Arm acquired Artisan Components in 2004 for $913 million.In my role as Executive Director of ESD Alliance and publisher of the quarterly Electronic Design Market Data (EDMD) report that includes IP, I recently talked with Lewis about what he remembers from the early days of IP.Smith: You were part of the IP revolution. What were the high points and low points that you most remember? Lewis: The high point was starting with a relatively blank slate and innovating. Some things worked, some didn't. We kept trying different things and seeing what would work with plenty of failed tries, successes, and repeats. We got a chance to be on the ground floor of a new industry. Another high point was watching this nascent industry emerge into a powerhouse. In the ‘90s, EDAC (Electronic Design Automation Consortium, the predecessor to the ESD Alliance) wasn't interested in tracking IP. As the IP market started growing, EDAC was all over it because it helped pump up the size of the electronic design automation (EDA) industry. Suddenly, IP had become a big enough industry that people were starting to care. And of course, there were successful public companies like Arm, Rambus, Artisan, and others licensing IP. It was fun being part of that.The low points were the hard part. While everything was new for us, it was also new for customers. They had intense resistance to licensing IP that many viewed as product development. They would want the IP company to develop something under a consulting or NRE contract, and then they would own the product and all the IP around it. They wanted to own everything. Many companies had that mentality in the early days and were resistant to licensing or paying royalties.As a side note, Gary Smith, former analyst for Dataquest, now Gartner Group, who died in 2015, and I had an ongoing debate. We went to lunch quite frequently and he would say, “IP is great, but you aren't IP. You are a standard cell, and it is not IP.” It was one of his standard statements.He would make various presentations, and I would argue: “You can't think of it as a cell, think of it as an entire library. It's an entire library with all the design views, layouts, test and qualification data, and everything else. That’s intellectual property. Plenty of intellectual property goes into developing it.”He eventually changed his mind and agreed when he saw the revenue and the value –– IP companies do it better and cheaper than in-house development.A final high point was getting the idea and value of IP across to customers. Smith: At what point did people start to believe IP was a real market and they could trust a vendor? Lewis: I don't know if there was an inflection point. More and more people started getting used to the idea that IP was an industry. Arm was probably the major catalyst. Artisan had two different engagement models. One was the integrated device manufacturer (IDM) model. Mark Templeton, co-founder and CEO of Artisan who died in 2016, and Lucio Lanza, Managing Partner of Lanza techVentures and Artisan’s Chairman, are credited with developing the royalty model and the intellectual property category. They drove it with the IDM model. Executive Advisor Jeff LewisCustomers knew they were paying for a license, understood the terms and became both the licenser and the user of this technology. It was different when Artisan went to the foundry model, which extended the IDM model to the rapidly growing foundry space. In this model, Artisan had the ability to widely disseminate its IP to all the foundry customers for free. However, calling it a “free library” is a misnomer, because often overlooked in this process is that the foundry paid up front for every one of those libraries, and it also paid a royalty on each design that used them. Artisan was profitable from day one by building a library or memory compiler. The engagement model was one where Artisan could proliferate these to the foundry’s users. They would get the library, and the royalty would come from the foundry. Users were beneficiaries – they had a simple license agreement, but unless they needed some customization, they weren't writing checks to Artisan.From the user’s perspective, it was great. They got free libraries and IP. That helped open people’s eyes to the model that could be a good thing. Artisan had 1,000 users at one point, and it helped drive the proliferation of IP use in the industry.Smith: Is that foundry model still in place? Lewis: Largely, yes, with some exceptions because foundries have a standard library that can be used. They have some specialized IP that customers license. While there are variations, foundries provide libraries to their customers. TSMC has engineers developing libraries for its own processes. For a long time, Artisan was the standard IP provider for most of the foundries. Smith: How did companies overcome verifying and testing IP? Were engineers skeptical about buying from an unknown/unproven company? Lewis: This is an important and critical question. Engineers were skeptical about buying from an unknown or unproven company. Artisan’s library quality was our biggest selling point, and it was the same with Arm and Rambus. Size and reputation were a huge advantage.The key was to have a major win that demonstrated your bona fides, and our biggest early win was our work on the Sony PlayStation. At that time, LSI Logic was developing the chips for the PlayStation, but was looking to outsource some of the critical blocks, such as the embedded SRAMs. Sony engineers were nervous and wanted to meet the IP companies to see what they were doing, because the fate of their chip was resting on these little companies. Artisan developed high-performance embedded SRAMs that replaced the existing LSI SRAMs. Our memories were about half the size of the LSI SRAMs, higher performance, and worked the first time.What’s instructive is how Artisan later got the foundry relationships going and sold libraries. Enabling first-time success is a quality argument, because the design would work the first time. At that time, almost every foundry library had bugs in them that caused silicon failures after tape-out. Our primary argument to engage foundries was our impeccable QA story. We had customer testimonials confirming that the foundries would not have library-related failures. When foundries scheduled a volume like a PlayStation ramp, they couldn’t afford a production “bubble” or “hole” in their production schedule from a library bug causing a chip not to work and requiring a re-spin.That's why the argument on quality and first-time success was critical to TSMC.One more thing on quality, and this ties specifically to Artisan and almost all IP companies. Any company that focuses on a mass proliferation model must ensure their product has no quality problems. Mass proliferation needs to be as low touch as possible, so engineers can use it without constantly calling for support. Quality is an absolute fundamental before mass distribution, because the fastest way to go bankrupt is to massively proliferate a faulty product. Smith: According to the EDMD report two years ago, IP surpassed front-end EDA tools as the highest category. Are we now shifting into a world where IP in the form of chiplets may become the dominant player? Lewis: I think the shift is coming. These are different incarnations of Moore's Law and the Carver Mead-structured VLSI. Sometimes the structure may be a chiplet, or the structure may be embedded.Is it virtual or is it actual? Engineers will make tradeoffs with pros and cons of embedding it or keeping it separate. The deciding factor is which silicon process is best and how it will be implemented. The SEMI EDMD report’s tracking of the Semiconductor Intellectual Property (SIP) and its rise to one of the market’s leading category. Smith: You worked for several IP companies that were offering process-related IP. That's a completely different type of market selling cycle, correct? Lewis: It is, because I focused on technology licenses for manufacturing processes, as opposed to the much more understood design IP that was developed for the existing manufacturing processes. Getting inserted into a company’s manufacturing process is much more difficult and challenging.If a company is licensing a technology that modifies the front-end process, then the process parameters will change, presumably for the better. The re-optimization can be like whack-a-mole. While some parameters get better, some may get worse, and further re-optimization can be required. This can go through several cycles until the process converges. This also means that all existing IP must be recharacterized and/or redesigned, which is why it is best to insert a new technology at the beginning of the node development rather than as a retrofit.Adding new process technologies is inherently difficult unless it’s a separable piece. For example, many new memories such as ReRAM or MRAM are licensed technology and separable, because they are set up separately in the metal stack. They don't touch the transistors.For a long time now, companies have been able to pick and choose whether to do in-house development or procure design IP from a third party. We're now starting to see the same thing in process development, because they are getting so complex, and no one can be an expert in all areas. I see process IP as paralleling the early days of design IP, but with a 30-year delay. Back then, most customers were reluctant to procure design IP because they felt: “We can do it all in-house.” Almost no one says that today, and I think this gradual acceptance will apply to process IP as well.Smith: Should Mark Templeton be considered the innovator and creator of the IP industry? Lewis: I’m not sure there’s anything I can say about him that hasn’t been said already. He was a great guy and an important thinker. I credit him for doing an excellent job crafting a successful company. And, of course, Lucio Lanza was absolutely instrumental as well. He pushed Artisan to do royalties, and Mark helped drive it to fruition.About Jeff LewisJeff Lewis is one of the pioneers of the semiconductor IP industry, participating since its inception in the mid-1990s. Lewis is currently Executive Advisor for senior management and investors for semiconductor and AI companies. He was previously an operating executive serving as Senior Vice President of Business Development and Marketing at Atomera Incorporated, Spin Transfer Technologies, SuVolta Inc., and Innovative Silicon Technologies, and held operating roles at Synopsys, VLSI Technology, and HP. Lewis earned an MBA from the UC Berkeley Haas School of Business, and has a bachelor’s degree in electrical engineering, and a bachelor’s degree in economics from UC Berkeley.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

John Kibarian, CEO and founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, is a keen observer of the semiconductor ecosystem. Since PDF Solutions sits between design and manufacturing, Kibarian shared unique perspectives on both in a recent discussion.Smith: What trends are you seeing in the semiconductor industry. Are there any that surprise you? Kibarian: We see several trends that have been going on for quite a while.As much as we hear Moore’s Law is dead, there's still a strong drive to get to advanced nodes. The benefits are harder to achieve and require more than geometry scaling, but demand for these advanced nodes continues to grow. Another emerging trend is the need for insatiable compute power in data centers to support the explosion in AI applications. In recent history, the mobile phone market has been the key driver of the push to new advanced nodes, but that is changing as the performance needs of data centers and AI applications are now driving the shift.Next, as companies are still learning from the disruptions in the supply chain due to the pandemic, there’s a tremendous amount of movement to make the supply chain more resilient by expanding sourcing options for critical products or test applications. This is happening in conjunction with significant investment in high-performance compute from many countries that want to bring silicon to their shores.The next trend is that electronics companies are looking to limit investing solely in China or the U.S. Their China Plus One or U.S. Plus One strategies results in adding significant additional infrastructure and overhead. If it's not done right, it will cost the industry more money. It will be hard to sustain the cost benefits and economies of scale of the current single source model just by brute force and adding human capital. A new approach is required to manage cost effectively smaller and globally distributed manufacturing facilities.The final trend is the general electrification of the economy. Cars are moving from internal combustion engines to electric. That means more and more of our energy needs are met with electricity, putting a premium on solar and batteries. Batteries require power conversion.Silicon such as high bandwidth semiconductors on silicon carbide and gallium nitride have a tremendous amount of capacity. What is interesting is how fast and aggressive China is in that part of the market; they could be a major producer of the technologies needed to support electrification. With our exposure to the China market as well as the European and U.S. markets, Chinese manufacturers have come up quickly, and we may see a world with more viable suppliers than originally anticipated.Smith: You mentioned data centers and AI. AI is everywhere and revolutionizing the semiconductor industry. EDA companies are talking about incorporating AI. What are you observing? Kibarian: AI is used for chips that are manufactured for use in data centers. For example, our customers use PDF analytics or the Exensio platform via the cloud to analyze large amount of manufacturing data and product or test engineering data. Without this type of automated solution, only a small proportion of these data sets would actually be utilized.Companies staff their product design and test engineering using a budget based on a percentage of revenue. If a company has billions of dollars of revenue, it will put so much more into product and test engineering. But how productive can these people be? Without AI, they can only use some simple reports and graphics to analyze the subset of data they are looking at. AI solutions such as PDF’s Guided Analytics capability apply sophisticated machine learning tools to analyze entire large data sets. AI is enabling engineers to be more productive by allowing them to work with large data sets that ultimately deliver better results in the products.The amount of compute keeps going up at a rate that outpaced the rate of geometric scaling. More compute power makes it cost effective to go through large data sets and identify what is relevant.Additionally, AI is helping semiconductor companies build products. A conventional compute system is chips assembled on boards. AI is making system-in-package take off.The production flow is more complex, as fabless companies are becoming system companies. Conversely, system companies are becoming fabless companies and manufacturers. In the past, they ordered parts from their foundry of choice. Essentially, the foundry was the system manufacturer, supplying package and test yields of 99%.Now companies are building systems in more complex packages potentially with foundry partners, but this requires getting known good die. High bandwidth memory or other components from other suppliers means the company must make sure these products are available at the right time. In essence, they are becoming manufacturers and changing the way customers manage the problem of product test. They're adding more test insertion points and using machine learning and AI to be more productive.Smith: Let’s talk about digital twins or creating virtual models of everything from chips to the whole system. How do you see the impact or effectiveness of digital twins in manufacturing? Kibarian: From a manufacturing perspective, digital twins had been models for chamber behavior on a processing tool like an etch tool or TCAD simulation of devices and structures.The problem is that purely physics-based digital twins don't exist, and we must utilize empirical data. The joke was that the modeling for tomorrow’s systems was based on yesterday's technology. Trying to have the physics catch up with the materials, device structures and behaviors is why it’s so expensive to develop new technology.Principles-based models will never catch up with production. We can model 90-nanometer technology, but it doesn’t work for one or two nanometer wafers. AI and machine learning – and ways of building models using more sophisticated algorithms – can help close that chasm, and that’s starting to happen at the R D level.In production, no one has yet achieved a good merger of the physics-based and AI-modeling worlds to create a virtual model. Virtual modeling is a big opportunity.The rate of change and improvement in algorithms in large language models moves fast because machine learning can scrape the Internet for data to build huge training sets. In the semiconductor world, however, data sources are typically siloed within organizations and often not shared with vendors. This limits the rate at which the industry can take full advantage of existing data and create tangible economic benefit.By and large, there is a lot of wasted capacity in semiconductor manufacturing. The operational effectiveness of factory equipment is up to 90-95%. The reality is that most factories today process product wafers 40-60% of the time – maybe 70-75% of the time on a test floor. It is critical for the industry to start leveraging new types of AI models to increase the productivity of its manufacturing capacity.The industry needs to look at how companies can share data to take advantage of more sophisticated AI and create a new kind of operational digital twins. If the industry doesn't make a change; it will only be the largest facilities with the largest datasets able to take advantage, leaving one or two winners, with the others not being competitive.Smith: Is it possible for the industry to come up with a standard or some way of sharing information to build better models without giving away the underlying proprietary data? Kibarian: We can look at computer science with technology like homomorphic encryption. The relationships between parameters remain, but the underlying numbers or raw data is not visible after encryption. Pharma and the medical industry have ways to add noise to the data while preserving the information, as required by the Health Insurance Portability and Accountability Act (HIPAA).Our industry has a knee jerk reaction when it comes to looking at how to take full advantage of data and prefers to solve it as if information and data is more proprietary than medical data or financial data. And I don't think that’s true.Bob Smith: Is the open-source movement destined to bring change to the industry? Kibarian: PDF is a big believer in open source when it comes to OS-level virtualization and Kubernetes versus proprietary alternatives. We also use open-source database technology like Cassandra but are skeptical of the value of open-source solutions for end-market verticals. Having an underlying open and available IT layer has tremendous value, because it means a more rapid rate of innovation and greater ability to adjust security vulnerabilities and patches versus proprietary systems.Smith: PDF sits right between manufacturing and design. On the EDA side, more collaboration is going on between designers and manufacturing. How would you bring these two domains closer together? Kibarian: That's a good question. My first instinct is to look at the largest design organizations and manufacturers. They often invest heavily to figure out how to get jobs done right. This results in the concentration of the industry on a smaller number of players and leads to less innovation. However, in the world of chiplets and advanced packaging, there are more opportunities to become a chiplet supplier, because the whole system doesn’t need to be built by a single company. A supplier of chiplets could sell it into many systemsFrom a system view, connecting the pieces together through software, data sharing and analytics could drive more productivity gains that will offset some of the natural headwinds. This needs to be addressed in a way that changes the paradigm with software and systems used to bring manufacturing and design closer together.About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

Maheen Hamid is co-founder of electronic design automation company Breker Verification Systems and a member of both the ESD Alliance Governing Council and the SEMI North America Advisory Board. I spoke with Hamid about the EDA industry and her perspectives on the sector where electronics begins.

Niels Faché, Vice President and General Manager of the Electronic Design Automation business at Keysight and a member of the ESD Alliance’s Governing Council, has a diversified career that took him from an academic track to a technology startup to senior management positions.