EDA

Would you buy your next hotdog in parts, from un-coordinated suppliers? For example: Get the bun from a baker, the sausage from a butcher, mustard and/or ketchup and veggies from the nearest supermarket? If yes, you may find the sausage being too small, the veggies too big for the bun, and, when you finally finished adding mustard/ketchup and start eating, you may “enjoy” a cold sausage on a soggy bun!This “hotdog example” is just a very simple way to highlight the advantages of a well-coordinated semiconductor supply chain. What may be a few dollars and cents wasted in this hotdog purchase, can become millions of dollars lost to delays and inefficiencies during the roll-out of a new electronic system.Complexity is Increasing the ChallengeThe very innovative semiconductor industry is continuing to develop more complete and complex building blocks for electronic system solutions, with the intent of making our customers’ lives easier. However, every new technology takes increasingly more time for technical and business interfaces to mature before all the semiconductor supply chain members can serve customers in a smooth, efficient and cost-effective manner. In particular, coordination between design and manufacturing has always turned out to be in the critical path.SEMI, the manufacturers’ trade organization, and the Electronic System Design (ESD) Alliance, representing electronic design automation (EDA) tools vendors, developers of intellectual property (IP = ready-made building blocks for ICs) and IC design service providers, both recognized these challenges. Late in 2018, these two industry organizations decided to jointly address this painful, costly and often a very frustrating, yet critical path and became Strategic Association Partners, The goal is to establish a well-coordinated semiconductor supply chain.To make the value propositions of this partnership highly visible and demonstrate the first joint accomplishments, SEMI’s well-known SEMICON West conference and, in its first year, ES Design West, will be conveniently co-located in San Francisco’s Moscone Center from July 9 to 11, 2019. The synchronized schedules and geographic proximity of these events not only outlines the multi-faceted interdependence of manufacturing and design but encourages and enables conference attendees to do, what previously would have been viewed as “forming cross-border relationships.” It’s a new word now — please join the path to success and expand your network!Navigating SEMICON West and ES Design WestJust in case you are not yet planning to come to San Francisco early July, please check the Agendas-at-a-Glance for SEMICON West and ES Design West, to see how broad and valuable these parallel conferences are for your business. In addition, every customer, partner and semiconductor industry supplier can, from July 9 –11, walk from one conference section to the other, arrange face-to-face meetings, in dedicated meeting rooms, with representatives from both camps and discuss, from the first project planning step to the final production ramp-up, the many topics that need to be coordinated across parts or the entire supply chain to minimize delays and/or cost over-runs.Who Will Lead the Discussions?Conference attendees can, in addition to meeting many important supply chain partners face-to-face, hear about the latest technologies and market trends from key executives in our industry. Featured speakers are: David Pellerin, Head of Global Business Development, Amazon Web Services Lisa Su, President, and CEO, AMD Gary Dickerson, President, and CEO, Applied Materials Laurent Le Faucheur, Principal Engineer, Digital Signal Processing and Machine Learning, Arm, Ltd. Renee St. Amant, Ph.D., Research Engineer in Emerging Technologies and US Innovator of the Year, ARM Dean Kamen, President DEKA Research Development, Founder First and First Global Jeffrey Welser, Ph.D., Vice President and Lab Director, IBM Research-Almaden Dean Drako, President and CEO, IC Manage, Inc. Oreste Donzella, Sr. VP Chief Marketing Officer, KLA Corporation Prakash Narain, President, and CEO, Real Intent, Inc. Aart de Geus, Chairman, and Co-CEO, Synopsys, Inc. Manish Pandy, Fellow, Synopsys, Inc. Nate Baxter, General Manager, Development and Production Group, TEL US Like in previous years, SEMICON West and ES Design West offer a range of special features, addressing Smart Manufacturing, Smart Transportation, Smart MedTech and Smart Workforce development in dedicated pavilions as well as an AI Design Forum. Also, the many exhibitors from both camps will give conference attendees convenient opportunities to get to know new supply chain partners and/or refresh long-term business relationships. Search for the exhibitors you want to meet early July here. Questions to Ask for a Well-Coordinated Semiconductor Supply ChainIf I may, I would like to ask my many friends in the manufacturing camp to spend some time in the ES Design West section and ask the exhibitors a few questions, like: What can you do to get me to profit faster? To reduce development and unit cost? To improve yield, product quality, and reliability? When can you visit my team to discuss how your company can contribute to our goals?Vice versa, I would like to encourage my friends in the design camp to spend time in the SEMICON West section and ask exhibitors what their companies offer. When talking to manufacturers of IC, passive components or circuit boards, assembly and test houses, please ask very specific questions like: How can we help you reduce iterations between you and your customers? How can we help to improve IC test programs? How can we increase the throughput of your manufacturing equipment? How can we apply machine learning (ML) and Artificial Intelligence (AI) to minimize equipment downtime, improve yields and/or shorten production ramp-up?I can assure you that you’ll not only win great friends “across the border” but will be very impressed by the expertise you’ll find in the other camp and the willingness for and benefits of cross-border cooperation.I look forward to meeting you at SEMICON West and ES Design West. Also, if your schedule allows, mark your calendars for the June 12 MEPTEC Luncheon at SEMI in Milpitas, June 18 for the GSA’s Silicon Summit in Santa Clara and June 25 to 27 for the IMAPS SiP Conference in Monterey, CA. Hope to see you at one or all of these important events!Article originally published in 3D InCites. Herb Reiter is president of eda 2 asic Consulting.

New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require.Yet MEMS design also presents some specialized challenges, such as a strong coupling between fabrication technology and design. Complex physical structures that exhibit non-linear behavior, custom packaging requirements, and a final product that requires integration with surrounding CMOS circuitry are just a few examples. What’s more, there is a lack of standardized processes and process validation in MEMS design ecosystems. Pressure Sensor (Courtesy: X-FAB) As with other products based on MEMS technology, designers must increasingly customize pressure sensors for higher performance – sensitivity and linearity, in this case – while decreasing their package size. Designers can accomplish the task by studying sensor performance and manufacturability using computer models prior to fabrication. This can ensure that the sensor meets its required specifications while simultaneously reducing manufacturing cycles and cost.The Power of CollaborationThis is where strong collaboration among EDA providers, MEMS technologists and designers delivers tangible benefits. EDA providers and MEMS foundries can collectively help MEMS designers to incorporate foundry process constraints into their designs.In the semiconductor industry, first-pass successful silicon relies on standardized manufacturing processes, thorough technology characterization, accurate model generation, established simulation and verification, and extensive reuse of proven design blocks. In the MEMS world, where processes and products are developed concurrently, and processes change with every product, is it possible to adopt standardized processes, design methodologies, and tools that enable efficient reuse of existing technology and design knowledge? The challenge lies in maintaining the flexibility to optimize products for a diverse array of requirements. The ideal design platform should ease sharing of technology and design data between the foundry and its customers, enabling two-way collaborative development and allowing foundry technologists to easily perform a feasibility assessment of a customer’s project. This approach offers important benefits, allowing designers to explore and evaluate the suitability of a foundry’s process technology in their unique application. It also supports accurate prediction of device performance prior to fabrication and reduces costly build-and-test cycles. Combining standardized manufacturing processes, MEMS process design kits (PDKs), and a proven design flow are the starting point for development of manufacturing-ready designs.A Real-Life Example using Pressure SensorsAn EDA company, Coventor (a Lam Research company), along with MEMS foundry partner X-FAB, collaborated to develop a PDK that would ensure that manufacturing constraints are automatically considered early in their design process. The design flow is based upon an X-FAB fabrication platform that supports multiple process options for the manufacturing of absolute and relative MEMS pressure sensors. The PDK is a “golden container” for all the process and material characteristics of the silicon membrane and substrate, glass, passivation layers, and piezoresistive components. It enforces material properties and guarantees their correct implementation during the simulation. It also includes a component library containing ready-to-use, 3D parameterized devices (such as membranes and resistors), all pre-designed with foundry-supported materials to support their respective design rules. The components are readily partitioned for optimized meshing and simulation, saving design and simulation time. Figure 1: The elements and design flow of the PDK designed by Coventor and X-FAB. (Courtesy: Coventor)Designers can use components from the library to create a custom design — which might include different membrane shapes and sizes, and resistors of varying shape, size and position — to simulate the impact of different technology variants (such as resistor doping profiles, membrane and substrate thickness, glass material properties, and passivation schemes). This allows them to anticipate the effect of these design changes on sensor sensitivity for varying pressure and temperature regimes.Extensive validation of the pressure sensor design platform is currently underway. So far, the simulations have exhibited very good correlation to actual device measurements across a range of pressure and temperature conditions, including predictions of non-linear behavior for various pressure sensor designs. At the same time, the simulation accounts for mechanical membrane properties and piezoresistivity. With this type of design platform, a foundry can provide guidelines to help customers select both the fab technology and design features that lead to an optimal design solution. Figure 2: Simulation results depicting mechanical displacement in a pressure sensor design (Courtesy: X-FAB) Let’s Face the Next Challenges…A complete design platform for MEMS must eventually include not only MEMS device design, but system integration functions, such as the application-specific integrated circuit (ASIC) design and packaging/assembly of the product. In addition to the design verification that the PDK provides, additional partnerships among foundries, integrated device manufacturers (IDMs), research centers, equipment suppliers, and EDA vendors will help to define requirements and solutions that address every level of design and production. These might include tasks such as describing standardized material properties and process specifications, creating accurate foundry-proven design models, and defining requirements for system-level simulation. In the future, PDK simulations might even include up to tape-out and physical verification. To learn more about this collaborative PDK development work, please click here for the whitepaper.Christine Dufour, MEMS PDK Program Manager, CoventorChristine Dufour is the MEMS PDK program manager at Coventor. She has more than 20 years of experience in the semiconductor industry, leading process design kit development for BiCMOS and CMOS processes at several major semiconductor companies. Ms. Dufour has also worked as a product manager in the RF design environment area. In addition to her extensive experience in MEMS PDK development, she is an expert in all aspects of MEMS design flow and design tool development. Ms. Dufour received an engineering degree at Technological University of Compiegne.For more information on Coventor, a Lam Research Company, visit: https://www.coventor.com/ Viraja Sharma, Development Engineer, MEMS Simulation Design, X-FABViraja Sharma is a development engineer for MEMS Simulation Design at X-FAB. Her work involves the design and simulation of MEMS inertial and pressure sensors. Prior to her tenure at X-FAB, Ms. Sharma performed similar duties for other semiconductor companies. She received her Master of Science degree in Micro and Nano Systems from TU Chemnitz, where she studied MEMS and micro technologies.For more information on X-FAB, visit: https://www.xfab.comCoventor and X-FAB are members of SEMI-MEMS Sensors Industry Group that connects the MEMS and sensors supply network, enabling members to address common industry challenges and explore new markets. 1 Market research firm Yole Développement predicts that MEMS pressure sensors alone will become a $2 billion market by 2023. See: https://yole-i-micronews-com.osu.eu-west 2.outscale.com/uploads/2019/01/YD18018_MEMS_Pressure_Sensor_Market_Yole_Developpement_2018_Sample.pdf

Creating a custom Internet of Things (IoT) IC is challenging because it involves multiple design domains (digital, analog and RF). Creating a sensor-based IC that combines electronics that use the traditional CMOS IC design flow with a MEMS sensor on the same silicon die, however, can seem impossible. Couple the co-design and verification challenges with a lack of traditional process design kit (PDK) support for MEMS, and you have a tough road to travel to get your IoT designs to market.What can we do to make the sensor-based IoT design community successful?Understanding the ChallengesThe sensor-based IoT IC typically features a MEMS sensor (and optional actuator) that interact with the real world. Analog and digital circuitry processes the signals and sends them to a CPU. The CPU provides the “smarts” to process the data from the sensor and then sends processed data via a radio to the Internet; alternatively, the CPU could activate the actuator. A typical sensor-based IoT IC (Source: Mentor: A Siemens Business) Based on the complexity of the system, designers face many co-design challenges: Analog design requirements imposed by MEMS: MEMS devices often require high voltages and multiple power supplies; they emit small signals that need amplification and conditioning; and they are sensitive to the environment and require calibration. Design flow interactions: Parasitics from MEMS devices might affect circuits and vice versa. Circuit designers need MEMS models for impedance and timing. Integration: MEMS devices operate at different timescales than circuits, which adds a layer of complexity. Compounding the problem is a lack of MEMS PDKs and methods to tie together ICs and MEMS PDKs for integration and cross-verification. After conquering the co-design challenges, the design team has to address mixed-domain simulation challenges that include: Simulating the system: This requires verification of MEMS, digital, analog and RF circuitry with embedded software that runs on the CPU. Timescales: These vary widely, from a single deflection of the MEMS transducer in femtoseconds to a seconds-long simulation of the embedded software performing a measurement and transmitting data. Simulation time: Simulation of a behavioral digital design is extremely fast. However, the system simulation requires stand-in models that incorporate the behavior of the analog and MEMS block to simulate in an acceptable amount of time. The challenge of timescales for co-simulation. (Source: Mentor: A Siemens Business) MEMS is the KeyThe reality is that it’s the MEMS device that adds extra complexity to the sensor-based IC design and verification flow. To amplify the problem, the MEMS manufacturing process is not nearly as mature as the standardized IC process. For example, the standardized IC process includes ready-made PDKs that include everything designers need to move through design and verification flows. Foundries often provide soft and hard IP to quickly build-out design, and EDA tools provide high levels of automation enabled by abstraction and a standardized IC flow. How will MEMS-based design evolve?MEMS-based design must catch up to the standardized IC process. The first step is providing MEMS PDKs that include: Multi-physics domain design rules and material properties Packaging information Wafer and bonding information Fabrication information We must also tackle issues associated with these PDKs, including: Ownership, distribution and maintenance of the PDKs Consensus on the contents of the PDKs Merging of CMOS and MEMS PDKs The industry needs to move toward standardized MEMS manufacturing processes with available PDKs. Companies must provide IP and recommend structured design methods for co-design and verification of ICs that incorporate MEMS. How can EDA help with these flows?The EDA ContributionEDA companies must work with teams in the MEMS IC co-design space, collaborating with MEMS fabricators to help enable PDKs. By incorporating PDK support within their own tools, EDA companies can provide an integrated custom IC flow that allows teams to design and verify MEMS-based ICs. For details about this flow, click here to download the Mentor whitepaper: Fusing CMOS IC and MEMS Design for IoT Edge Devices.Greg Lebsack brings 25 years of executive and technical management experience — along with a proven track record of building strong teams and delivering predictable results — to his role as general manager of the ICDS division of Mentor, a Siemens Business. Lebsack joined Mentor in 2015 after that company acquired Tanner EDA, where he was president. Prior to Tanner EDA, he held management and technical positions in a number of different industries and companies, including Sprint, General Electric and McKinsey Co. Greg holds a bachelor’s degree in business administration from Northern Arizona University.Greg Lebsack recently presented on the topic of Integrated Co-design of MEMS/IC at the MEMS Sensors Technical congress, a technical conference organized by the MEMS Sensors Industry Group.

Constant coverage of an invigorating topic like machine intelligence in the media often urges us to consider its use in EDA technology. As is often the case, there are many myths and falsehoods that consume our time and effort when trying to apply machine intelligence to EDA. This article aims to uncover the myths and to provide helpful advice on applying machine intelligence to your EDA project or product.Value PropositionFirst, there needs to be a clear value proposition for adding machine intelligence to an EDA product. Using machine intelligence to create a me-too product adds no value. EDA customers are too busy to understand or care about an EDA tool’s underlying technology. They just want to use the tool and get results. If the tool delivers value, if it delivers tangible benefits, then they’ll use it. Otherwise, they won’t.Currently, EDA tool developers are already experimenting with AI and machine intelligence without considering this fundamental truth – without a higher-end objective. AI must deliver something better or new, whether a speed advantage, a performance advantage, new features, new insights, or perhaps even something pleasantly surprising. Before you write a single line of AI-enhanced code, you need to clearly understand how AI will enhance the product. What is the value proposition?Use ModelThere’s a major barrier to customer adoption of AI and machine intelligence technology for EDA tools: EDA users are averse to make decisions based on probabilistic results. Instead, half a century of EDA tool use has conditioned them to expect deterministic outcomes from their tools.Back in 2003, a prominent visionary and EDA investor was quoted in an interview, saying: “If I open my eyes five years from now, all static analysis in VLSI will be statistical.” Many EDA luminaries have been proven wrong over time for betting that EDA users will accept statistical results. As enthusiastic as I am about using machine intelligence to improve EDA tools, I must urge caution based on the history of EDA failures that employed a probabilistic use model. Decision-makers and EDA tool users want to see deterministic answers to questions about yield or slack, not probabilistic ones.Our experiences at Paripath in developing the PASER (Paripath Accelerated Simulation Environment) tool also bear this out. We discovered that delivering results 50x faster but with 92% accuracy was simply not good enough for end users. EDA users only started to use PASER when its answers became 98+% accurate. To be adopted in the production flow, the tool had to deliver 99% accuracy.Data EngineeringThere are specific ways to achieve these accuracy goals. The first is data engineering. Machine intelligence is a new approach to EDA tool development and it needs to be trained on a data set. If the data is poor or incomplete, training will create an inaccurate model. Fundamental software-development rules still apply. Garbage in, garbage out.Without good training data, there’s no way for you to build good neural-network models. If you train a model with garbage data, you’ll get a garbage model. You must cleanse the data before you use it for training. Otherwise, the model will draw inaccurate conclusions and customers will not use your tool. The model is not to blame here. The model’s not wrong. The problem lies in poor data engineering, poor data cleansing, and a lack of discipline to prepare input data.High DimensionalityNext, machine intelligence has a unique ability to quickly solve problems of high dimensionality. Pure EDA problems often have high dimensionality. Over the years, EDA developers have perfected the art of segmenting the problems into sequencing solutions with lower dimension. Machine intelligence technology can handle problems with thousands of dimensions, but you need to be careful when tackling problems that have high dimensionality. Too many dimensions can produce confused or inaccurate results with AI and deep-learning technology.It helps to visualize the problem and to analyze the data set before using the data to train an AI-enhanced EDA tool. Several visualization methods can help. For example, t-SNE (t-Distributed Stochastic Neighbor Embedding) lets you reduce a data set’s dimensionality from a very large number to a much lower number. Figure 1 shows a high-dimension dataset with a dimensionality of 2000, which has been reduced to a low dimensionality of 3. Figure 1: Visualizing the Data Set with Lower Dimensionality Reducing the dimensionality of a data set to 3 using t-SNE and visualization allows you to quickly see whether the data set defines an easy or a difficult problem. If the problem is difficult, you’ll likely need to lower the problem’s and the data set’s dimensionality before using the data to train a neural network.Technology SelectionOne factor that determines whether it will be easy or difficult to incorporate machine intelligence into your EDA tool is your choice of AI development tools. AI researchers have developed a long list of frameworks, libraries, and languages that they use to develop AI and machine-learning software. Frameworks and libraries such as TensorFlow, Caffe and MXNet are most popular for developing deep-learning models.However, these tools are not yet popular with the EDA development community. The languages of choice in the EDA community are traditionally C and C++ for development and Tcl for prototyping and creating user interfaces. The rest of the software world has moved on to newer development languages such as Python, Java, R, and such. Moreover, machine-learning development segments into two distinct processes: training (i.e. generating the model) and inference (i.e. using the model).Another question to consider is where to generate the model – at the vendor site or the customer site?Consequently, fitting AI and deep-learning development into EDA development environments can feel like fitting a square peg into a round hole. You may need to create corners in your hole.EDA is a very small player in the overall software market. Relatively few software developers are familiar with writing EDA tools. It’s best to select AI and deep-learning development tools that can provide some sort of interface that’s compatible with EDA’s development tools of choice. Some AI frameworks have lower-level C and C++ interface layers that provide a familiar entry point for experienced EDA developers.At Paripath, we chose TensorFlow for exactly this reason. TensorFlow has a lower-level C/C++ interface. Although the resulting development path becomes a longer one using this approach, it’s a more familiar path for EDA developers and therefore it’s a path that can ultimately lead your EDA development team to success. An elaborate study of comparing these frameworks has been published in the book Machine Intelligence in Design Automation.Integration into Legacy SystemsWhen you understand the value that you expect machine intelligence to add to your new EDA tool, when you’ve cleansed and then analyzed the data set, and when you have selected an appropriate set of development tools, you’re finally ready to add machine intelligence to your EDA development. There are two use models for AI-enhanced EDA tools. The first uses a trained model to guide the EDA tool’s decision-making. In this use case, the trained neural network doesn’t change. The software’s accuracy doesn’t improve with use unless the company that developed the EDA tool retrains the underlying neural network. This use case follows the familiar, existing use case associated with EDA tools developed using deterministic algorithms.For the second use case, the end user is able to retrain the underlying neural network, which allows the EDA tool to produce better, more accurate results over time. This use case produces a win/win situation because end users are able to hone their tools and improve them over time, without help from the EDA tool vendor’s application engineers. If the retrained models are also sent back to the EDA developer for incorporation into newer versions of the tool, all users benefit from other users’ training data.It’s not clear how you’d support this second use case in the current EDA business environment where most data sets are proprietary and are carefully guarded. Most large EDA tool customers want to keep their data in house under tight control. Even with this somewhat restrictive situation, however, EDA tools benefit from the incorporation of machine intelligence because each EDA tool customer can customize the tool and improve its results.Machine intelligence has much to add to EDA tools’ capabilities. Only time will tell if the customers want and will accept these new capabilities. Rohit Sharma, founder and CEO of Paripath Inc., is an engineer, author and entrepreneur. He has published many papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna - an advanced characterization software for modern nodes. Sharma has written a book titled “Machine Intelligence for Design Automation.” You can download code examples and other information here.Note from SEMI-ESD Alliance: ESD Alliance’s Interoperability Committee brings together the industry to discuss interoperability. By focusing the efforts of the electronic system design community onto key compute operating systems, the Interoperability Committee seeks to define a stable, interoperable environment for tools and streamline the resources required to support these environments. The EDA Industry OS Roadmap presents guidelines to EDA vendors and customers for compute platforms to target for design starts. Learn more and view the OS Roadmap overview at our website.

I really don’t know clouds at all. – Joni MitchellThe semiconductor industry is finally on the cusp of joining the cloud revolution. The cloud has offered the promise of greatly expanded resources for years, but adoption has been slow due to lingering concerns. The biggest contributing factor for the concern over moving from on-premise EDA servers to cloud-based servers is, surprisingly, the rise of third-party IP. In the old days, if you were developing 100 percent of your own IP, and if you put that IP on a public cloud, and it somehow leaked out, well shame on you. That would certainly be bad for business. It might hurt your reputation a bit. But these days, with so much third-party IP being embedded into chips, if that third-party IP leaks out, that’s a lawsuit-fest in the making.Consequently, semiconductor companies now have even more incentive to protect IP with advanced security. Surprisingly, cloud-based security is far, far better than on-premise security. Why? Because keeping customers’ data secure is the central mission of cloud service suppliers, so they’ve developed a rich set of security tools to protect the data that’s entrusted to them by their clients. In many ways, you can maintain much better security in the cloud than you can with on-premise tools. Image credit: Markus Spiske temporausch.com from Pexels Amazon Web Services: Exemplifying the benefits of cloud computingTake Amazon Web Services (AWS) as an example. (Note: AWS is not the only vendor in the cloud space, but it’s one I’m very familiar with.)AWS has developed the concept of security groups – firewalls that you throw up around any network interface to allow only specific traffic into that secured network. You can do that for just one server or for a fleet of servers, in just seconds. Most on-premise server networks won’t let you work that quickly, or as easily, or with such fine control because most such networks lack the security tools to do this.In addition, AWS allows you to encrypt every bit of data stored on and flowing through its cloud-based storage systems. You can encrypt data at rest in on-premise storage but it’s a lot harder to encrypt data flying through the on-premise network. Amazon’s Elastic File System (EFS), a managed NFS file service, offers the ability to easily encrypt NFS traffic on the wire, a difficult feat at best with an on-premise solution.AWS built-in encryption key-management service can rotate encryption keys automatically. The cloud also allows you to have key policies that are easy to implement and maintain.Internal corporate networks rely heavily on perimeter firewalls for security. Perimeter defense just cannot deliver sufficient security against determined hackers and everyone realizes this. We’ve built big, open, on-premise networks that are just not well-suited to implementing adequate security protocols. Trying to retrofit these network architectures with additional security is time-consuming and costly, and it hurts engineering productivity. Moving to the cloud gives you a greenfield opportunity to right some of the wrongs of the past.Continuing with AWS as an example, here are some additional advantages of EDA in the cloud: AWS provides physical security that’s far above and beyond on-premise security. It doesn’t publish the physical locations of its data centers. It also has professional security staff 24/7, keycard access, and additional security features that far exceed typical on-premise physical security. AWS automatically manages security patches and access controls for their managed services such as database services. AWS gives you plenty of security tools to automate security processes, audits, and so forth to protect your data. AWS gives you so much flexibility that you can get yourself in trouble in you are not careful. If you want, you can create the same sorts of security holes that already exist with on-premise networks. You shouldn’t of course, but you can if you’re not thoughtful about things. You just need to hire the right people to implement and maintain your cloud security.Here are five very big differences between AWS (cloud-based) and on-premise server networking: Elasticity: Cloud-based systems enable you to scale up in minutes. That ability has pluses and minuses depending on how disciplined you are. On the plus side, you can quickly grow your EDA infrastructure as big as you want and then shrink it back down when you no longer need the additional capacity. All you need to do is tell the cloud service that you need more capacity and it will bring that extra capacity online for you in minutes – and will charge you for it. (That’s the minus side.) When you’re done, you can turn off the extra capacity (and stop paying for it) with the same speed. If you want to provision more EDA capacity for your on-premise network, you’ll need to beg, borrow, or steal existing capacity from someone else on your network, or you can order more servers, get the vendor to build and ship them, install them in your server room, provision them, and bring them online. That will take months. Fault tolerance: On-premise networks rely on large, monolithic service architectures, which saddle EDA vendors with more than 30 years of technical debt. The cloud operates on a different model, one that’s based on containers and microservices. This is inherently a redundant, fault-tolerant computing model if you write your code correctly. The difference between redundancy in the cloud and in on-premise networks is night and day. There’s no comparison. No private networks can match the available and growing redundancy of cloud systems, which have redundant servers inside of a data center and redundant data centers in multiple, worldwide geographic locations, which protects your data from natural and man-made disasters. Network segmentation: Many semiconductor developers have several design centers distributed around the world and there may be IP in use on a project that cannot be shared with certain geographic locations either by law or by contract. Cloud networks are already set up with automated tools for network segmentation that can enforce geography-specific rules through VPCs (Virtual Private Clouds), which are easy to set up. VPCs allow you to set up subnets with restrictions based on routing tables so that IP management and control become highly automated. Removal of single points of failure: The typical EDA grid configuration has several built-in single points of failure. For example, a central job dispatcher generally runs on one single node. If that node dies, all EDA work halts. The same is true for EDA license servers and for configuration-management and version-control servers. Again, because cloud networks are based on the microservices concept, the cloud simply doesn’t need to have the same single-point-of-failure vulnerabilities that on-premise networks have. On-premise networksTo get these same advantages with on-premise networks, the grid architecture must fundamentally be changed, starting with the replacement of NFS. EDA systems need to replace huge, monolithic file systems specifically developed for EDA with object storage. That's a tall order – one that requires the rewriting of fundamental assumptions that serve as EDA software’s foundation.In the 1980s, 1990s, and early 2000s, small EDA startups appeared to fill gaps in the offerings of the large EDA players. If they succeeded and grew, they’d eventually be gobbled up by a larger EDA vendor. That flowering of EDA startups seems to have damped down. The market has really matured.Next wave of EDA startups to offer cloud-first toolsGoing forward, I expect the next wave of EDA startups will be offering cloud-first tools that are not burdened by three decades of technical debt. They’ll be able to architect their tools specifically for the cloud.We’re starting to see this happen. For example, Metrics, a Canadian EDA startup, offers a pay-by-the-minute, cloud-based simulator and verification manager. Although one job on one cloud server might run slower than a monolithic simulator running an on-premise server, Metrics has architected its tools so that you can throw more servers at the problem, allowing you to run all of your jobs at once. Here, multiple simulation jobs running concurrently on multiple servers will ultimately finish faster than running the jobs serially on one slightly faster on-premise simulator.That’s the kind of innovation that we’re going to see. That’s the future of EDA.Derek Magill is executive director and president at HPC Pros. Derek has 20 years of experience supporting semiconductor engineering functions. His main focus has been in system architecture and technical management, but over the years he has been involved with technologies such as EDA licensing, ClearCase, HPC architecture, IP management and engineering software support. Derek spent 15 years at Texas Instruments in various technical and managerial roles. He is currently a senior manager, IT at Qualcomm managing the Global License Infrastructure team as well as the lead technical architect for the company's engineering cloud activities. The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, is the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. As an international association of companies providing goods and services throughout the semiconductor design ecosystem, it provides a forum to address technical, marketing, economic and legislative issues affecting the entire industry. The ESD Alliance also stages events that promote networking, learning and collaboration among member companies. To learn more about the ESD Alliance and how to join the group, visit www.esd-alliance.org or contact Bob Smith at [email protected].